JP2881833B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a BiCMOS semiconductor device.

[Conventional technology]

In recent years, many attempts have been reported for BiCMOS ICs because they can simultaneously realize high-speed operation and high driving capability of bipolar transistors and low power consumption of CMOS transistors.
In order to suppress the generation of hot electrons, which is a problem in N-channel MOS transistors as the design dimensions become finer, a double diffusion type drain (hereinafter abbreviated as DDD) that reduces the concentration of electric field at the drain end BiCMOS ・ IC used
The development of the manufacturing method of has been actively carried out.

Previously reported silicon gate BiCMO using DDD
FIG. 3 is a cross-sectional view of the element of the SIC. This manufacturing process will be described step by step.

First, an N ⁺ -type buried region 2 and a P ⁺ -type buried region 3 are formed in a P ⁻ -type semiconductor substrate 1 having an impurity concentration of 1 to 2 × 10 ¹⁵ cm ⁻³ , and an N ⁻ -type epitaxial region 4 is formed to a thickness of about 1 to 5 μm. I do.

Next, after forming the P-type well region 5 and the N-type well region 6, an inter-element isolation oxide film 7 and a gate oxide film are formed.

Thereafter, a polycrystalline silicon layer serving as the gate electrode 9 of the MOS transistor and the collector electrode 10 of the NPN transistor is grown, and impurities are diffused to perform N ⁺
A mold collector region 11 is formed.

Next, the P-type base region 17 is doped with a dose of 1 to 3 × 10 ¹³ cm ^−2.
N-channel MO after ion implantation of boron
DDD type source / drain region 13 of S transistor and NP
The emitter region 14 of the N-type transistor is made of arsenic having a dose of about 5 × 10 ¹⁵ cm ⁻² and a dose of 5 × 10 ^{13 to} 3 ×.
It is formed by ion implantation of about 10 ¹⁴ cm ^-2 of phosphorus.

Further, the P ⁺ type source / drain region 15 of the P-channel MOS transistor and the P ⁺ type base contact region 16 of the NPN type transistor are formed by boron ion implantation at a dose of about 5 × 10 ¹⁵ cm ⁻² to complete the device. I do.

[Problems to be solved by the invention]

Silicon gate BiCMOS I using conventional DDD described above
C is continuously ion-implanted with arsenic and phosphorus in one photolithography process to form source and drain regions. Therefore, if the emitter region is also formed, the emitter region also has a DDD structure. Become.

The base width is determined by the depth of the junction between the P-type impurity such as boron and phosphorus, but phosphorus has a larger diffusion coefficient than arsenic and the depth of the junction tends to vary, so that the base width tends to vary. Therefore, the variation in the current amplification factor of the bipolar transistor increases. Conversely, if the impurity is deeply diffused into the base in order to solve this, there is a disadvantage that the base width is widened and the high frequency characteristics deteriorate.

[Means for solving the problem]

Silicon gate BiCMOS IC having DDD structure of the present invention
Is a method of forming a high-concentration and low-concentration N-type region in the source and drain regions of an N-channel MOS transistor and an emitter region of an NPN transistor and a P-type region in a base region of the NPN transistor. The relationship is high-concentration N-type region> P-type region> low-concentration N-type region, and the relationship of junction depth is high-concentration N-type region <P-type region <
Forming a low-concentration N-type region;

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are process sectional views of an embodiment of the present invention.

First, as shown in FIG.
× 10 ¹⁵ cm ^-3 of P ^- -type semiconductor substrate 1 to form an N ⁺ -type buried region 2, P ⁺ -type buried region 3, the impurity concentration of 2 to 5 × 10 ¹⁵ cm ^-3
Of the N ⁻ type epitaxial region 4 is formed in a thickness of about 1 to 5 μm.

Next, after forming the P-type well region 5 and the N-type well region 6, an inter-element isolation oxide film 7 and a gate oxide film 8 are formed.

Next, as shown in FIG. 1 (b), after opening a diffusion window on a region where a collector is to be formed, a gate electrode 9, a collector electrode 10
A polycrystalline silicon layer is grown to a thickness of about 0.6 μm, and an impurity is diffused to form an N ⁺ -type collector region 11. After oxidizing the polycrystalline silicon surface, a photoresist 12 is formed.

Next, as shown in FIG.
Using 70 as a mask, acceleration energy 70keV, dose 3-5
The ion implantation of arsenic of × 10 ¹⁵ cm ^-2 is performed, the acceleration energy is continuously set to 40 to 50 keV, and the dose is set to 1 × 10 ¹⁴ cm ^{-2, so} that the source / drain regions 13 and 13 of the N-channel MOS transistor have the DDD type. The DDD emitter region 14 of the NPN transistor is formed.

Further, after removing the photoresist 12, using another photoresist pattern as a mask, the P-channel MO is removed.
P ⁺ type source / drain region 15 of S transistor and NPN
The P ⁺ type base contact region 16 of the type transistor is formed by boron ion implantation at a dose of about 5 × 10 ¹⁵ cm ⁻² .

Finally, as shown in FIG.
Boron ions of 30 to 40 keV and a dose of 5 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² are implanted to form a P-type base region 17.

Hereinafter, based on a conventional method for manufacturing a semiconductor device, metal wiring and the like are formed to complete an element.

The concentration distribution of arsenic, phosphorus, and boron on the AA 'line shown in FIG. 1 (d) of the NPN transistor formed by the above steps is as shown in FIG. 2 (a). When synthesized, the N-type and P-type impurity distributions are second
As shown in FIG. 2B, the base width can be reduced.

〔The invention's effect〕

As described above, the present invention relates to a method of manufacturing a silicon gate BiCMOS IC having a DDD structure, wherein high-concentration and low-concentration N-type regions of the source and drain regions of an N-channel MOS transistor and the emitter region of an NPN transistor are provided. And the formation of the P-type region of the base region of the NPN transistor, the relationship of the impurity concentration is high-concentration N-type region> P-type region> low-concentration N-type region, and the relationship of the junction depth is the high-concentration N-type region < By forming the P-type region <the low-concentration N-type region, a base region having a small width can be easily formed, and high-frequency characteristics can be improved.

Further, the emitter-base junction is determined by the high-concentration N-type region and the P-type base region. In general, the high-concentration N-type region selects an impurity such as arsenic having a relatively small diffusion coefficient, so that the variation in the base width is small. Variations in the current amplification factor of the bipolar transistor can also be reduced.

[Brief description of the drawings]

1 (a) to 1 (d) are sectional views in the order of steps of an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are distribution diagrams of impurities in a depth direction in a bipolar transistor according to an embodiment. FIG. 3 is a sectional view showing the prior art. 1 ... P ^- type semiconductor substrate, 2 ... N ⁺ type buried region, 3 ...
P ⁺ type buried region, 4 ... N ^- type epitaxial region, 5 ...
... P-type well region, 6 ... N-type well region, 7 ... element isolation oxide film, 8 ... gate oxide film, 9 ... gate electrode, 10 ... collector electrode, 11 ... N ⁺ type collector region , 12
... Photoresist, 13 ... DDD type source / drain region, 14 ... DDD type emitter region, 15 ... P ⁺ type source / drain region, 16 ... P ⁺ type base contact region, 17 ...
P-type base region.

Claims (1)

(57) [Claims] In a method of manufacturing a semiconductor device in which a silicon gate CMOS transistor having a double diffusion type drain and a bipolar transistor are formed on the same semiconductor substrate, regions where a source, a drain and an emitter of an N-channel MOS transistor are to be formed are provided. Forming a high-concentration N-type diffusion layer by diffusing a high-concentration N-type impurity into the substrate; Forming a P-type diffusion layer deeper than the P-type diffusion layer; and forming the source, the drain, and the emitter of the N-channel MOS transistor in the region where the formation is to be formed, with a lower concentration than the P-type diffusion layer and a junction depth lower than the P-type diffusion layer. Forming a N-type diffusion layer deeper than the diffusion layer.