JP2633559B2 - Method for manufacturing bipolar CMOS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a method for manufacturing a bipolar CMOS type semiconductor device (hereinafter, referred to as a Bi-CMOS type semiconductor device).

(Prior Art) In recent years, in the technical field of semiconductors, CMOS circuits have often been used in semiconductor devices in order to reduce power consumption. Recently, a Bi-CMOS type semiconductor device in which a bipolar transistor is added to a CMOS circuit in order not only to reduce the power consumption but also to increase the speed has attracted attention.

Conventionally, this Bi-CMOS device has been formed according to the manufacturing process shown in FIG.

First, in the step shown in FIG. 3A, after selectively providing an N ⁺ type buried diffusion region 2 in a P type silicon substrate 1,
A P-type epitaxial layer (Pepi) 3 is formed by a vapor growth method. Next, an N well diffusion layer (NWell) 4 serving as a collector region of the NPN bipolar transistor is provided so as to reach the N ⁺ type buried diffusion region 2. Subsequently, a field oxide film 5 is formed, and a deep N ⁺ type diffusion region 6 is formed in the N well diffusion layer 4 for forming a bipolar transistor so as to reach the N ⁺ type buried diffusion region 2. . The N ⁺ -type buried diffusion region 2 and the deep N ⁺ -type diffusion region 6 are effective for reducing the resistance of the N well diffusion layer 4 serving as the collector region of the NPN bipolar transistor.

In the step shown in FIG. 3B, the gate oxide film 7
Is formed, and a P-type internal base region 8 is formed by implanting B ^{+ at} a low dose, and then a P-doped polysilicon film 9 is deposited.

In step (c) of FIG. 2, the polysilicon film 9 is
It is patterned by Method E, to form a gate electrode 9 _1, 9 ₂ of the NMOS and PMOS transistors. Subsequently, As ⁺ is implanted at a high dose to form N ⁺ type source / drain regions 10 ₁ and 10 _{2 of} the NMOS transistor and an N ⁺ emitter region 11 of the NPN bipolar transistor. Next, B ⁺ is implanted with high dose ions to form P ⁺ type source / drain regions 12 of the PMOS transistor.
_1, 12 ₂ and to form a P ⁺ type external base region 13 of the NPN bipolar transistor.

Finally, in the step shown in FIG. 3 (d), after depositing a passivation film 14, a contact is opened and an aluminum electrode 15 is further provided so that the NMOS, PMO
The S transistor and the NPN bipolar transistor are completed on the same semiconductor substrate 1.

As described above, conventionally, a bipolar transistor is manufactured during a CMOS transistor manufacturing process to manufacture a Bi-CMOS semiconductor device.

However, conventionally, since the P ⁺ -type external base region 13 is formed by non-self-alignment (self-alignment), the N ⁺ -type emitter region
The base resistance r _bb ′ under 11 (see FIG. 3 (e)) becomes large, and it is difficult to realize high-speed operation of the bipolar transistor on the same substrate 1 as the CMOS circuit.

(Problems to be Solved by the Invention) As described above, the conventional Bi-CMOS semiconductor device has a problem that it is difficult to mount a bipolar transistor capable of operating at high speed on the same semiconductor substrate as a CMOS circuit. Was.

Therefore, an object of the present invention is to provide a method of manufacturing a Bi-CMOS device in which a bipolar transistor capable of operating at high speed can be easily mounted on the same semiconductor substrate as a CMOS circuit.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, according to the present invention, an emitter electrode is formed on an emitter region of a semiconductor substrate, and a sidewall is provided on a side wall of the emitter electrode. It is like that.

(Operation) According to the above configuration, since the external base region can be formed in a self-aligned manner with respect to the emitter region using the sidewall as a spacer, the base resistance under the emitter region can be reduced, and the bipolar transistor can be formed. High speed operation can be realized.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a view showing a manufacturing process of an embodiment. Before explaining FIG. 1, an outline of the embodiment will be described with reference to FIG.

In recent years, with the development of LSIs, miniaturization of MOS transistors has become indispensable, and the channel length of MOS transistors tends to be short, for example, 0.8 to 1.2 μm. As a result, the short channel effect and the hot electron resistance become severe, and the reliability of the operation of the transistor tends not to be secured.

For this purpose, as shown in FIG. 2 (a), a gate oxide film 42, an As or P-doped polysilicon gate electrode 43 is provided on a P ^- type silicon substrate or an N well diffusion layer 41, and for example, a low dose P ⁺ or B ⁺ N ^- type or
P ^- type source, after the formation of the drain region 44 and 45, by depositing a CVD oxide film, thereby which leave the CVD oxide film 46 _1, 46 ₂ only on the side wall of the etch-back to the polysilicon gate by RIE . Then, for example, by high dose As ⁺ or BF ₂ ⁺ ion implantation, N ⁺ -type or P ⁺ -type source and drain regions 4
Reliable N suitable for VLSI by forming 7,48
A CMOS circuit having a MOS or PMOS transistor is provided.

In this embodiment, as shown in FIG. 2 (b), the high-speed NPN bipolar transistor is mounted on the same semiconductor substrate on which a CMOS circuit is formed by using the above-described technique by substantially the same process. That is, the gate oxide film on the N-well diffusion layer 51 serving as the collector region of the bipolar transistor is peeled off, and the P-type diffusion region 52 serving as the internal base region is first formed by low-dose B ⁺ implantation, followed by As or P-doped. A to-polysilicon film 52 is deposited and processed simultaneously with the gate electrode of the MOS transistor to form an emitter electrode 53 which becomes a part of the emitter region. Thereafter, the CVD oxide film 54 is left on the side wall of the polysilicon emitter electrode 53 by the above-described method, and the high dose BF ₂ ⁺ ion implantation used for forming the P ⁺ type source / drain regions of the PMOS transistor is performed. As a result of the process, a P ^{+ type} external base region 55 is formed by diffusing As or P from the emitter electrode 53 into the P type internal base region 52, and is formed in a self-aligned manner without contacting the N ⁺ type emitter region 56. High-speed bipolar NPN with small base resistance r _bb ′
A transistor is realized.

Now, an embodiment of the present invention will be described in detail with reference to the cross-sectional views showing the manufacturing steps of FIG.

First, in the step shown in FIG.
0), after selectively providing an N ⁺ type buried diffusion region 21 of ρsｓ20 Ω / □ on a P ⁻ type silicon substrate 20 having a specific resistance of 20 to 30 Ω-cm, a thickness of 2.0 μm and a specific resistance of 1 to 1 A P-type epitaxial layer 22 of 2 Ω-cm is grown. Next, xj = 2.5 μm, ρs〜2K, where PMOS and NPN bipolar transistors are formed.
After providing an N-well diffusion layer 23 of .OMEGA ./. Quadrature.
A field oxide film 24 is formed. Then, in order to reduce the collector resistance, a deep N ⁺ -type diffusion region 25 of ρs = 20 to 30 Ω / □ is formed so as to reach the N ⁺ -type buried diffusion region 21.

In the step shown in FIG. 1 (b), a thermal oxide film 26 having a thickness of 300 ° to be a gate oxide film is formed, and B ⁺ is subjected to 5 × at 40 KeV.
10 ¹³ cm ^-2 ions are implanted to perform a heat treatment diffusion depth Xj～0.
The thermal oxide film 26 on the 5 μm P-type internal base region 27 is peeled off to deposit a polysilicon film 28 having a thickness of 0.4 μm, and As ⁺ ions are implanted into the polysilicon film 28 at 5 × 10 ¹⁵ cm ⁻² . .

In the step shown in FIG. 1C, the polysilicon film 28 is patterned by the RIE method to form NMOS and PMOS gate electrodes 28 ₁ and 28 ₂ and an emitter electrode ₃ . A thermal oxide film 29 is formed on the surface of the surrounding and exposed P-type internal base region 27. At this time, As is diffused at a high concentration from the emitter electrode into the P ⁻ -type internal base region to form an N ⁺ -type emitter region 30 of ρs〜30Ω / □ xj〜0.15 μm. Subsequently, in order to ensure the reliability of the NMOS and PMOS transistors, P ⁺ and B ⁺ are implanted at 1 × 10 ¹³ cm ⁻² at 50 KeV into the NMOS and PMOS transistor forming portions, respectively, to form a high breakdown voltage structure. After this, a 0.4μ thick CVD
An oxide film 31 is deposited.

In the step shown in FIG. 1 (d), the CVD oxide film 3
1 is etched back by RIE to leave a CVD oxide film 31 on the side walls of the emitter electrode and the gate electrode of the MOS transistor. Subsequently, As ⁺ is formed at 5 × 10 ¹⁵ cm ⁻² at 40 KeV for forming the source and drain regions of the NMOS transistor, and BF ₂ ⁺ is formed at 40 KeV for forming the source and drain regions of the PMOS transistor and the external base region of the NPN bipolar transistor. After implanting 5 × 10 ¹⁵ cm ^-2 ions at, heat treatment is performed to electrically activate the ion-implanted layer, and the xj-
Source and drain regions 32 ₁ and 32 ₂ composed of an N ⁺ region and an N ⁻ region of about 0.4 μm, and xj of a PMOS transistor of about 0.4 μm.
Source and drain regions 33 ₁ , comprising P ⁺ and P ^- regions,
33 ₂ , a P ^{+ type} external base region 34 of xj0.20.2 μm of the NPN bipolar transistor is formed.

Finally, in the step shown in FIG.
m, a contact hole is formed, an aluminum-silicon electrode 36 is provided, and a
-A CMOS semiconductor device is completed.

According to this embodiment, the gate electrode 28 ₁ , 28 _{2 of} the MOSTR and the side wall oxide film 31 are connected to the emitter electrode 28 _{3 of the} bipolar transistor.
By also be left on the sidewalls of forming the sidewall, the it is possible to form the P ⁺ type external base of the side wall as a spacer in a self-aligned N ⁺ -type emitter region 30, Bi suitable for high speed operation -A CMOS semiconductor device can be realized.

The present invention is not limited to the second embodiment.

For example, in the above embodiment, the case where an As-doped polysilicon film is used for both the gate electrode and the emitter electrode has been described, but a P-doped polysilicon film may be used as the gate electrode. Further, the present invention can be realized even if the N ⁺ -type emitter region is formed in contact with or not in contact with the field oxide film.

Of course, various modifications can be made without departing from the spirit of the invention.

[Effects of the Invention] As described above, according to the present invention, since the sidewall is provided on the side wall of the emitter electrode by the oxide film, the external base region is formed in a self-aligned manner with respect to the emitter region by using this as a spacer. Can be
The base resistance under the emitter region can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of an embodiment of the present invention,
FIG. 2 is a cross-sectional view schematically illustrating one embodiment,
FIG. 3 is a cross-sectional view showing an example of a conventional method for manufacturing a Bi-CMOS semiconductor device. 20 …… P ⁺ type silicon substrate, 21 …… N ⁺ type buried diffusion region, 22
…… P-type epitaxial layer, 23 …… N-well diffusion layer, 24
…… Field oxide film, 25 …… N ⁺ type diffusion region, 26 …… Thermal oxide film, 27 …… P type internal base region, 28 …… Polysilicon film, 29 …… Thermal oxide film, 30 …… N ⁺ Mold emitter area, 31 ...
... CVD oxide film, 32 ₁ , 32 ₂ , 33 ₁ , 33 ₂ ... source and drain regions, 34 ... P ^{+ type} external base region, 35 ... passivation film, 36 ... aluminum-silicon electrode.

Claims (3)

(57) [Claims] 1. A bipolar CM having a MOS transistor and a bipolar transistor on the same semiconductor substrate.
In a method for manufacturing an OS type semiconductor device, a first step of forming a polysilicon film on a semiconductor substrate on which a collector region and an internal base region are formed, and etching the polysilicon film formed by the first step Forming a thermal oxide film on the semiconductor substrate so as to cover the emitter electrode formed by the second step, and simultaneously diffusing impurities from the emitter electrode. A third step of forming an emitter region in the internal base region, a fourth step of forming a deposited film on the thermal oxide film formed by the third step, and A fifth step of etching back the formed deposited film to form a sidewall on the side wall of the emitter electrode, and a sidewall formed by the fifth step. A sixth step of forming an external base region in the semiconductor substrate by ion-implanting impurities into the semiconductor substrate using the metal layer and the emitter electrode as a mask, followed by heat treatment to form a bipolar transistor. A method for manufacturing a bipolar CMOS semiconductor device, comprising: 2. The bipolar CMOS according to claim 1, wherein said second step of forming said emitter electrode is performed simultaneously with said step of forming a gate electrode of said MOS transistor. Of manufacturing a semiconductor device. 3. The step of forming a side wall on the side wall of the emitter electrode is performed simultaneously with the step of forming a side wall on the side wall of the gate electrode of the MOS transistor. 3. The method for manufacturing a bipolar CMOS semiconductor device according to claim 1.