JPH0648717B2 - Method for manufacturing semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an offset gate complementary MOS (hereinafter abbreviated as CMOS) device.

[Background technology]

As a method of manufacturing an offset gate structure of an N-channel MOS (hereinafter abbreviated as N-MOS) transistor, low-concentration ion implantation is performed using a gate electrode as a mask, and then sidewalls of an oxide film are formed on both side surfaces of the gate electrode. Formed by reactive ion etching (RIE) method,
A method is known in which high-concentration ion implantation is performed using this sidewall as a mask, and the source and drain regions have an offset gate structure. (IEEE TRANSACTION ON EL
ECTRON DEVICES, VOL.ED-29, No. 4, PP590 of APRIL 1982 and below).

When the offset gate structure as described above is applied to, for example, the CMOS device of the CMOS inverter circuit shown in FIG. 2, the present inventor has clarified the following problems.

Four photo-etching steps are required to form the source and drain regions of the P-channel (P-MOS) transistor and the N-MOS transistor. Therefore, four masks are added, and the process is complicated and the cost is high. In addition, P-MO
If the sidewalls provided on both side surfaces of the gate electrodes of the S-transistor and the N-MOS transistor are simultaneously formed by the RIE method, the sidewall lengths of the P-MOS transistor side and the N-MOS transistor side become equal, and the P-MOS This is inconvenient when the side walls of the transistor and the N-MOS transistor are required to have different lengths due to their characteristics. For example, the characteristics of the threshold voltage Vth vs. channel length (Lg) are shown as follows.
If you want to have the same characteristics as the OS transistor, use P-MO
Since the diffusion coefficient of boron on the S transistor side is larger than that of phosphorus or arsenic, it is necessary to change the sidewall length.
Further, since boron has a larger diffusion coefficient than phosphorus or arsenic, the electric field relaxation effect cannot be optimally adjusted between the P-MOS transistor and the N-MOS transistor.

[Object of the Invention]

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of manufacturing a CMOS device having an offset gate structure by a simple process.

Another object of the present invention is to provide a method of manufacturing a semiconductor device, which can obtain a highly reliable channel CMOS device having a high breakdown voltage and stable element characteristics.

The above and other objects and novel characteristics of the present invention are
It will be apparent from the description of the present specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

That is, (a). P-MOS transistor and NM on semiconductor substrate
After forming each gate electrode of the OS transistor, the first silicon nitride film formed on the entire surface of the semiconductor substrate is patterned to leave the first silicon nitride film only in the N-MOS transistor formation region. ). P-MOS using the first silicon nitride film as a mask
P-type impurities are implanted in the transistor formation region to form shallow low-concentration P-type diffusion layers in the source and drain formation regions, (c). The first silicon oxide film formed on the entire surface of the semiconductor substrate is etched by RIE to form first sidewalls on both side surfaces of each gate electrode, (d). Using the first sidewall as a mask, the PM
By implanting a P-type impurity in the OS transistor formation region to form a deep high-concentration P-type diffusion layer in the source and drain formation regions, the shallow low-concentration P-type diffusion layer and the deep high-concentration P-type diffusion layer are formed. Forming source and drain regions of a P-MOS transistor composed of a diffusion layer, (e). After forming a second silicon nitride film on the entire surface of the semiconductor substrate, the P-MOS transistor region is masked with a resist, and the second silicon nitride film in the N-MOS transistor formation region and the first side are formed. A wall, removing the first silicon nitride film, (f). Using the second silicon nitride film as a mask, the NM
Implanting an N-type impurity in the OS transistor formation region to form a shallow low-concentration N-type diffusion layer in the source and drain formation regions, (g). The second silicon oxide film formed on the entire surface of the semiconductor substrate is etched by RIE to form the N-MO film.
Second sidewalls are formed on both side surfaces of the gate electrode of the S transistor, (h). Using the second sidewall as a mask, the NM
By implanting an N-type impurity in the OS transistor formation region to form a deep high-concentration N-type diffusion layer in the source and drain formation regions, the shallow low-concentration N-type diffusion layer and the deep high-concentration N-type diffusion layer are formed. The source and drain regions of the N-MOS transistor including a diffusion layer are formed. Therefore, the photo-etching process is performed only twice, and thus the C of the offset gate structure can be inexpensively manufactured by the relatively simple process.
MOS devices can be manufactured. In addition, the sidewalls formed on the gate electrodes of the P-MOS transistor and the N-MOS transistor are formed on the P-MOS transistor side and the N-side, respectively.
-Since it is carried out in separate steps for the MOS transistor, the sidewall length (offset length), which is one of the parameters for determining the device characteristics, should be changed individually for the P-MOS transistor side and the N-MOS transistor side. Therefore, the offset lengths of the P-MOS transistor and the N-MOS transistor can be set separately, and the highly reliable short channel C with high withstand voltage and stable element characteristics is provided.
A MOS device can be obtained.

〔Example〕

FIGS. 1 (a) to 1 (i) show an embodiment of a method of manufacturing a semiconductor device according to the present invention, and in particular, an example when applied to a CMOS device of the CMOS inverter circuit of FIG.
A description will be given below with reference to the cross section taken along the line AA 'in FIG. In FIG. 2, reference numeral 22 denotes P formed on the N-type silicon substrate 1.
-MOS transistor, 23 is an N-MOS transistor formed in the P well 2 formed in the N-type silicon substrate 1,
22a and 22b are contacts formed on the source and drain regions of the P-MOS transistor, 23a and 23b are contacts formed on the source and drain regions of the N-MOS transistor, 24 is a contact, 25 is a gate Al wiring, 26a to 26c are Al wirings.

First, as shown in FIG. 2A, a P well 2 is formed in an N-MOS transistor forming region of an N-type silicon semiconductor substrate 1, then an element isolation SiO ₂ film 3 is formed, and a gate oxide film 4 is formed on the entire surface. Form. Then, after the polycrystalline silicon gate electrode 5 is formed, thermal oxidation is performed to form a thermal oxide film 6, after which a silicon nitride (Si ₃ N ₄ ) film 31 is formed on the entire surface by a CVD method and then patterned by N-. The silicon nitride film 31 is left only in the MOS transistor formation region. The remaining silicon nitride film 31 is used as a mask to implant a boron (B) ion beam 32 in the P-MOS transistor formation region, and the shallow low-concentration boron diffusion layer 3 is formed in the source and drain formation regions.
3 is formed.

Next, as shown in FIG. 1B, the CVD SiO ₂ film 34 is formed on the entire surface.
Are attached and formed by RIE, leaving only the side surface of the gate electrode 5. As a result, SiO ₂ sidewalls 34a and 34b are respectively formed as shown in FIG. Then, the boron ion beam 35 is ion-implanted using the sidewalls 34a as a mask to form a deep high-concentration boron diffusion layer 36. Thereby, the diffusion layer 33
The source and drain regions 37a and 37b of the P-MOS transistor are formed by the transistors 36 and 36.

Next, a CVD silicon nitride film 38 is deposited on the entire surface, and then P
-Only the MOS transistor formation region is masked with the resist 39 and the N-MOS transistor formation region is etched as shown in FIG.
The side wall 34b of SiO _{2 and} the silicon nitride film 31 are removed.

Next, as shown in FIG. 3E, a low concentration phosphorus ion beam 40 is implanted into the N-MOS transistor forming region using the silicon nitride film 38 as a mask to form a shallow low concentration phosphorus diffusion layer 41. . Thereafter, as shown in FIG. 6F, a CVD SiO ₂ film 42 is vapor-deposited on the entire surface, and this is etched by the RIE method, so that the side surface of the gate electrode 5 on the N-MOS transistor formation region side is shown in FIG. As shown, a side wall 42a of SiO ₂ is formed. After that, a high concentration arsenic (As) ion beam 43 is implanted using this sidewall 42a as a mask, and a deep high concentration arsenic diffusion layer 44 is formed as shown in the figure.
To form.

As a result, source and drain regions 45a and 45b composed of the diffusion layers 41 and 44 are formed, respectively. Then, if the silicon nitride film 38 is removed, a CMOS device having an offset gate structure is formed as shown in FIG.

Further, the interlayer insulating film 46 and the Al wiring 47 using, for example, phosphorus silicate glass (PSG) are formed by a usual method.
C of the offset gate structure corresponding to FIG.
The MOS device is constructed as shown in FIG.

In the above CMOS device manufacturing method, the photomask process can be performed only with the resist, but the silicon nitride films 31 and 38 are used without using the resist for the following reason. First, if the resist is used as a photomask,
When the CVD SiO ₂ sidewalls 34a and 42a are formed, the resisting temperature of the resist is about 200 ° C., so the resist is at a high temperature in the electric furnace of the CVD method (for example, about 700 ° C. or higher).
I can't stand it. In addition, Si is used as a mask in the photomask process.
If an O ₂ film is used, the element isolation SiO ₂ film 3 will be removed when this mask is removed.
Will also be etched, and in terms of etching selectivity, Si
Cannot use O ₂ film. Therefore, FIG. 1 (a) (c) (e)
As can be seen from the process diagram of (g), when the silicon nitride films 31 and 38 are used as photomasks at the time of ion implantation, the silicon nitride films are excellent in heat resistance and etching selectivity. C with the mask left
The sidewalls 34a and 42a of the VDSiO ₂ film can be formed, and the element isolation SiO ₂ film 3 is not etched when the mask of the silicon nitride films 31 and 38 is removed.

According to the method for manufacturing the offset gate structure CMOS device as described above, the sidewalls 34a and 42a are formed separately in the P-MOS transistor formation region and the N-MOS transistor formation region, not in the same step. Two times with respect to four times of the photomask process (see FIGS. 1A and 1E), and the silicon nitride films 31 and 3
P-MOS transistor and N-MOS using 8 as a mask
Four diffusion layer regions for forming an offset gate structure of a transistor, that is, two low concentration (N ⁻ , P ⁻ ) diffusion layers 3
3, 41 and two high-concentration (N ⁺ , P ⁺ ) diffusion layers 36, 4
4 can be formed. Therefore, a CMOS device having an offset gate structure can be obtained at low cost by simplifying the manufacturing process.

Since boron has a larger diffusion coefficient for silicon than arsenic, the diffusion layer for forming the source and drain of the P-MOS transistor is formed deeper than that of the N-MOS transistor. For this reason, in a CMOS device having an offset gate structure, when the offset gate structure is optimized from the viewpoint of electric field relaxation, etc., the offset amount that is one of the parameters that determines the device characteristics, that is, the sidewall length P- MOS transistor side and N
-It may be necessary to change it on the MOS transistor side. With respect to such a problem, the present invention provides a PM
Sources of OS transistor and N-MOS transistor,
Since the sidewalls 34a and 42a necessary for obtaining the deep diffusion layers 36 and 44 in the drain region are formed not in the same step but in separate steps, the sidewall length is P-
The MOS transistor formation region and the N-MOS transistor formation region can be individually changed, so that P-
The offset amounts of the MOS transistor and the N-MOS transistor can be set separately, whereby the characteristics of the threshold voltage (Vth) and the channel length (Lg) can be matched, and the offset gate in the CMOS device can be relaxed from the viewpoint of electric field relaxation. The structure can be optimized easily and the above problems can be solved. In this way, it is possible to obtain a short-channel CMOS device having a high breakdown voltage, high reliability, and stable element characteristics.

〔effect〕

(1) By forming the sidewalls provided on the side surfaces of the gate electrodes of the P-MOS transistor and the N-MOS transistor individually for each MOS transistor instead of in the same process, the photomask process can be performed in comparison with the conventional four times. 2
A CMOS device having an offset gate structure can be manufactured in a single operation. Therefore, a CMOS device having an offset gate structure can be manufactured at low cost by simplifying the manufacturing process.

(2) The sidewall length required for forming the diffusion layers of the source and drain regions of the P-MOS transistor and the N-MOS transistor is not formed in the same step but is formed separately. The transistor and the N-MOS transistor can be changed individually, so that the P-MOS transistor and the N-M transistor can be changed.
The offset amount of the OS transistor can be set separately. As a result, the P-MOS transistor and the N-MOS transistor can easily realize the optimization of the offset gate structure from the viewpoint of matching the Vth-Lg characteristics to each other and the optimization of the electric field relaxation effect. It is possible to obtain a short channel CMOS device having high stable element characteristics.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. Nor. For example, although the CMOS device is formed on the N-type silicon substrate 1 in the above embodiment, the present invention is not limited to this, and the P
The offset gate structure CMOS device may be formed on the silicon substrate. In this case, it is needless to say that the N well is formed instead of the P well 2 and that it is changed as necessary.

[Field of application]

In the above description, the case where the invention made by the present inventor is mainly applied to the CMOS device of the CMOS inverter circuit which is the field of application which is the background of the invention has been described, but the invention is not limited thereto and, for example, a CMO.
It can be applied to CMOS devices such as S gate arrays and CMOS logic circuits.

[Brief description of drawings]

FIGS. 1 (a) to 1 (i) are cross-sectional views of main process steps showing an embodiment of a method of manufacturing a semiconductor device according to the present invention. FIG. 2 is a layout diagram of the CMOS inverter circuit. 5 ... Gate electrode, 6 ... Thermal oxide film, 22 ... P-MO
S transistor, 23 ... N-MOS transistor, 3
4a, 42a ... Sidewalls, 37a, 45a ...
Source regions, 37b, 45b ... Drain regions.

Claims (2)

[Claims] 1. A sidewall is formed as a mask on both sides of each gate electrode of a P-channel MOS transistor and an N-channel MOS transistor which form a complementary MOS device, and the sidewall is utilized to form the P-channel MOS transistor. The N channel MOS
A method for manufacturing a semiconductor device, in which each source and drain region of a transistor is formed in an offset gate structure to manufacture an offset gate complementary MOS device, including the following steps (a) to (h): Of manufacturing a semiconductor device. (a). After forming the gate electrodes of the P-channel MOS transistor and the N-channel MOS transistor on the semiconductor substrate, the first silicon nitride film formed on the entire surface of the semiconductor substrate is patterned so that only the N-channel MOS transistor forming region is formed. A step of leaving the first silicon nitride film, (b). A step of implanting a P-type impurity into the P-channel MOS transistor forming region using the first silicon nitride film as a mask to form a shallow low-concentration P-type diffusion layer in the source and drain forming regions, (c). A step of etching a first silicon oxide film formed on the entire surface of the semiconductor substrate by an RIE method to form first sidewalls on both side surfaces of each gate electrode, (d). By implanting P-type impurities into the P-channel MOS transistor formation region using the first sidewall as a mask to form deep high-concentration P-type diffusion layers in the source and drain formation regions, the shallow low-concentration region is formed. Forming source and drain regions of a P-channel MOS transistor consisting of a P-type diffusion layer and the deep high-concentration P-type diffusion layer, (e). > After forming a second silicon nitride film on the entire surface of the semiconductor substrate, the P-channel MOS transistor region is masked with a resist, and the second silicon nitride film in the N-channel MOS transistor forming region and the first silicon nitride film are formed. Sidewall, a step of removing the first silicon nitride film, (f). Step (g) of implanting N-type impurities into the N-channel MOS transistor formation region using the second silicon nitride film as a mask to form shallow low-concentration N-type diffusion layers in the source and drain formation regions. A step of etching a second silicon oxide film formed on the entire surface of the semiconductor substrate by an RIE method to form second sidewalls on both side surfaces of the gate electrode of the N-channel MOS transistor, (h). By implanting N-type impurities into the N-channel MOS transistor forming region using the second sidewall as a mask to form deep high-concentration N-type diffusion layers in the source and drain forming regions, the shallow low-concentration region is formed. Forming a source / drain region of an N-channel MOS transistor comprising an N-type diffusion layer and the deep high-concentration N-type diffusion layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the length of the first sidewall is different from the length of the second sidewall.