JP2728424B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which a small signal circuit and a high breakdown voltage or power transistor coexist on the same chip. The present invention relates to multifunctional and high-value-added large-scale integrated circuits composed of a so-called LDD structure MOSFET having an impurity layer.

[Conventional technology]

A conventional device is disclosed in IEE, Transaction on Electron Devices, EDE33, December 1986, 1985 to 1991 (IEEE, Tran).
s.Electron Devices ED33 (Dec.1986) PP.1985-1991)
3 μm of the polycrystalline Si gate, as discussed in
Low voltage CMOS and high voltage CMOS using mCMOS process
Devices were being integrated.

[Problems to be solved by the invention]

In order to further improve the performance of the integrated circuit by using the above-described conventional technology, miniaturization can be considered. However, if the gate length is 3μ
m to 1.3μm, 0.8μm, small signal according to the prior art
In the structure of the MOSFET, problems such as a decrease in breakdown voltage and a decrease in reliability due to hot electrons occur. Therefore, in order to solve this problem, an LDD structure MOSFET is used, and a step of forming a high-pressure low-temperature oxide film sidewall and an ion implantation step are added.

In the coexistence of the small-signal MOSFET and the high-voltage power transistor, such a change in the structure and process becomes inconvenient because the structure and process of the high-voltage power transistor unit are complicated.

An object of the present invention is to provide a structure optimal for coexistence of an ultra-miniaturized MOSFET and a high breakdown voltage / power transistor and a method of manufacturing the same.

[Means for solving the problem]

The above object is achieved by coexisting an LDD structure MOSFET and a lateral power MOSFET, and simultaneously forming the low impurity concentration layer for the LDD structure and the offset layer of the power MOSFET under the same forming conditions.

[Action]

Simultaneously forming the low-concentration layer of the LDD structure and the offset layer of the power MOSFET under the same forming conditions can shorten and simplify the manufacturing process compared to forming the low-concentration layer and the offset layer separately. to enable. Then, the coexistence technology of the LDD structure MOSFET and the lateral power MOSFET using such a method is an optimum technology for coexistence of the small signal MOSFET and the high withstand voltage / power transistor in the ultrafine process.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows a part of a cross-sectional structure of a large-scale integrated circuit in which an LDD structure MOSFET and a lateral power MOSFET coexist on the same chip. 1 is an n-channel small signal MOSFE having an LDD structure
T and 2 are n-channel lateral power MOSFETs having a drain / offset layer. Although only the n-channel is shown here, the p-channel can also be made to coexist. 3
Is a p-type low-concentration substrate used in normal VLSI, 4 is a p-type well
Layer 5, a high-concentration n-type layer serving as a drain / source region;
Is a high-concentration p-type layer for taking the potential of the source and the WELL layer in common, 7 is an n-type low-concentration layer in the LDD structure, and 8 is a power MOS.
FET n-type drain / offset layer, 9 is a polycrystalline Si gate electrode, 10 is a side wall for LDD structure, 11
Is an Si oxide film, 12 is an insulating film, 13 is an Al first layer electrode, 14 is an interlayer insulating film, 15 is an Al second layer electrode, and 16 is a surface protective film.
FIG. 2 shows a manufacturing process of the integrated circuit shown in FIG.
The manufacturing process will be described step by step. First, in (a), after the surface of a p-type substrate is oxidized, a p-type WELL layer is formed by WELL photo, B + ion implantation and drive-in, and subsequently, Si ₃ N ₄ deposition, L photo, and thermal oxidation are performed. Perform LOCOS separation. Next, as shown in FIG. 2B, a gate oxide film having a thickness of 200.degree. Is formed, and after polycrystalline Si is deposited, phosphorous treatment is performed, and a gate electrode is heated, P + ions 17 are implanted. This allows LDD
The low-concentration layer of the structure MOSFET and the offset layer of the lateral power MOSFET are formed. Subsequently, as shown in (c), a high-temperature and low-pressure oxide film is deposited and anisotropic etching is performed to form a side electrode of the gate electrode.
After the formation of the wall, a P + ion implantation of 19 is performed through a photo step of 18 to form a high-concentration n-type layer. At this time,
The distance between the gate electrode end of the LDD structure MOFET and the high-concentration n-type layer is determined in a self-aligned manner by the side wall. However, that of the lateral power MOSFET is determined by the alignment accuracy with the dimension of the resist mask. Further, after forming a high-concentration p-type layer as shown in (d), an insulating film is deposited. Finally, a contact hole is formed, an A1 layer wiring, an interlayer insulating film is deposited, a through hole is formed, an Al2 layer wiring and a protective film are formed as shown in FIG. According to this embodiment, by simultaneously forming the low-concentration layer and the offset layer having the LDD structure, the LDD structure MOSFET and the lateral power MOSFET can coexist in the simplest process. That is, there is no need to perform a photo step, an ion implantation step, and an annealing step for forming the p, n type offset layer, and the LDD structure MOSFET may be used as it is. In this embodiment, Si is used as the semiconductor substrate. However, the present invention can also be implemented using other materials, for example, a compound semiconductor such as GaAs. Further, as the wiring material, a material such as Cu, which has high conductivity and is unlikely to cause electromigration, other than Al, and a material having a high dielectric constant and high reliability such as Ta ₂ O ₅ other than the Si oxide film is used as the gate insulating film. Can also.

Another embodiment of the present invention will be described with reference to FIGS.
FIG. 3A is a circuit diagram of a multi-stage CMOS driver including a small signal LDD structure MOSFET and a mesh gate lateral power MOSFET,
(B) is a plan view in which the layout is actually laid out. 20
Is a p-channel MOSFET with an LDD structure, 21 is an n-channel MOSFET, 22, 24, and 26 are p-channel lateral power MOSFETs with a mesh gate structure of −30 V, and 23, 25, and 27 are n-channel lateral power MOSFETs with a drain breakdown voltage of 30 V. MOSFET, 28 is its unit cell, 29, 30, 31 are 5V, 20V, 0V power supply terminals, 32 is an input terminal, and 33 is an output terminal. FIG. 4A is a plan view of the unit cell 28, and FIG. 4B is a sectional view of the unit cell. 34 is a contact hole between the A1 layer and the Si crystal, 35 is A
One and two layers of through holes. Here, the circuit of FIG. 3A will be described. This circuit obtains a 20V output signal from a 5V input signal. 22,23 for this
The size of 22 and 23 was adjusted so that the CMOS constituted by switches at an input voltage that is half of the power supply voltage of the preceding CMOS. The threshold voltages of 22 and 23 are −1 V and 1 V, respectively.
Considering that the electron mobility is three times the hole mobility and the channel lengths of 22, 23 are equal, the channel width of 23 is set to be about 30 times that of 22. The size of the transistors other than 22 and 23 was adjusted so that they could be switched at half the input voltage of their own. This driver consists of an output stage of a micro processor composed of an LDD structure MOSFET and EPROM.
Etc. are used for a boosting circuit for writing in a nonvolatile memory. According to the present embodiment, an output driver for boosting an output signal of a large-scale integrated circuit including an LDD structure MOSFET can coexist on the same chip.

〔The invention's effect〕

According to the present invention, since a large-scale integrated circuit composed of an LDD structure MOSFET and a lateral power MOSFET can coexist on the same chip, there is an effect of reducing the package cost and the mounting area. Further, coexistence can be achieved without changing all the manufacturing processes of the large-scale integrated circuit, and thus there is an effect that there is no concern about an increase in manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a sectional view of an LSI in which an LDD structure MOSFET and a lateral power MOSFET coexist according to an embodiment of the present invention, FIG. 2 is a manufacturing process of the first element, and FIG. 3 is another embodiment of the present invention. Example LD
FIG. 4 is a circuit diagram and a plan view of a multi-stage CMOS driver including a D-structure MOSFET and a mesh gate structure lateral power MOSFET, and FIG. 4 is a plan view and a cross-sectional view of a unit cell constituting the power MOSFET of FIG. 1 ... Small signal MOSFET, 2 ... Power MOSFET, 7 ... LDD
N-type low-concentration layer, 8... N-type offset layer, 10.

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical display location H01L 29/792 (72) Inventor Koji Kojima 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi, Ltd. Inside the laboratory (72) Inventor Takeaki Okabe 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-60-64473 (JP, A) JP-A-54-109794 (JP, A) JP-A-61-5571 (JP, A)

Claims (1)

(57) [Claims] A source and a drain region of a second conductivity type are formed on a surface of a semiconductor substrate of a first conductivity type so as to be separated from each other, and an insulating film is provided between the source and drain regions at a position separated from the drain region. A second gate electrode is provided to reach a channel region below the gate electrode from the drain region;
In a semiconductor integrated circuit device having a plurality of insulated gate field effect transistors provided with a conductive type low-concentration impurity layer, an insulator is provided so that a part of the transistors reaches the drain region from a side wall of the gate electrode. A first transistor formed, a part of which is a second transistor whose distance from a gate electrode to a drain region is longer than that of the first transistor, wherein the structure of the second transistor is a planar transistor; A semiconductor integrated circuit device having a mesh gate structure including source and drain regions two-dimensionally arranged above.