JPS54109794A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54109794A
JPS54109794A JP1648878A JP1648878A JPS54109794A JP S54109794 A JPS54109794 A JP S54109794A JP 1648878 A JP1648878 A JP 1648878A JP 1648878 A JP1648878 A JP 1648878A JP S54109794 A JPS54109794 A JP S54109794A
Authority
JP
Japan
Prior art keywords
resistance
layer
island
poly
phosphorus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1648878A
Other languages
Japanese (ja)
Inventor
Shigeru Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1648878A priority Critical patent/JPS54109794A/en
Publication of JPS54109794A publication Critical patent/JPS54109794A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To form the 2nd rsistance wiring through the insulator thin film by forming the island-shaped poly Si layer on the insulator thick and thin films on the Si substrate and changing the island-shaped layer into the 1st resistance wiring via injection of the ion.
CONSTITUTION: SiO2 thick film 2 and thin film 3 are formed selectively on p-type Si substrate 1 and then covered with the poly Si, and island layer 4 is formed through the selective etching. Then the phosphorus ion is injected to form high- resistance gate 4a', n--type high-resistance layer 5a and 5b, high-resistance wiring 4b' and 4c', and high-resistance layer 5c and 5d respectively. Then CVDSiO2 mask 6a and 6b are formed selectively, and the n+-layer is formed through the phosphorus diffusion. At the same time, the phosphorus is added partially to the high- resistance poly Si layer to obtain n-channel FET at region I, resistance layer 4b' of about 30Ω/cm2 and high-resistance layer 4c' of several GΩ/cm2 at resion II, and diffusion resistance 5c' of about 15Ω/cm2 and high resistance 5d of KΩ/cm2 at region III respectively. Thus, the four types of resistance are obtained in this constitution, which is advantageous for the layout of the circuit design.
COPYRIGHT: (C)1979,JPO&Japio
JP1648878A 1978-02-17 1978-02-17 Manufacture of semiconductor device Pending JPS54109794A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1648878A JPS54109794A (en) 1978-02-17 1978-02-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1648878A JPS54109794A (en) 1978-02-17 1978-02-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54109794A true JPS54109794A (en) 1979-08-28

Family

ID=11917667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1648878A Pending JPS54109794A (en) 1978-02-17 1978-02-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54109794A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01235369A (en) * 1988-03-16 1989-09-20 Hitachi Ltd Integrated-circuit semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01235369A (en) * 1988-03-16 1989-09-20 Hitachi Ltd Integrated-circuit semiconductor device

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