JPS5513953A - Complementary integrated circuit - Google Patents
Complementary integrated circuitInfo
- Publication number
- JPS5513953A JPS5513953A JP8729378A JP8729378A JPS5513953A JP S5513953 A JPS5513953 A JP S5513953A JP 8729378 A JP8729378 A JP 8729378A JP 8729378 A JP8729378 A JP 8729378A JP S5513953 A JPS5513953 A JP S5513953A
- Authority
- JP
- Japan
- Prior art keywords
- area
- film
- covered
- multicrystal
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To increase operating speed by providing a multicrystal Si gate electrode to form a mask through a gate insulation film, on well areas that are provided in a semiconductor substrate and are used for P and N channels, then by forming source-drain regions within each well area by the use of the above mentioned mask. CONSTITUTION:A P type well area 42 is formed to a N type Si substrate 41 by means of a diffusion process, and the entire surface is covered by a thick field SiO2 film 43, and then an opening is made in an element forming area. A thin gate SiO2 film 44 is covered in the opening, and ions are supplied through this film 44 to form a P type well area 45 at the adjoining area to 42. Then a multicrystal Si layer is laid on the entire surface before forming a gate electrode 46 on the area 42 by etching through the film 44. With this as a mask, N<+> type source-drain regions 50 and 51 are formed in the area 42 by means of a diffusion process, and this surface is covered by a Si3N4 film 48. Likewise on the other area 45, a multicrystal Si gate electrode 47' is formed, and is covered by a Si3N4 film 49, then P<+> type source-drain regions 53 and 54 are formed in the area 45 by means of the diffusion process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8729378A JPS5513953A (en) | 1978-07-18 | 1978-07-18 | Complementary integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8729378A JPS5513953A (en) | 1978-07-18 | 1978-07-18 | Complementary integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5513953A true JPS5513953A (en) | 1980-01-31 |
Family
ID=13910754
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8729378A Pending JPS5513953A (en) | 1978-07-18 | 1978-07-18 | Complementary integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5513953A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57109363A (en) * | 1980-12-26 | 1982-07-07 | Seiko Epson Corp | Semiconductor device |
JPS5955054A (en) * | 1982-09-24 | 1984-03-29 | Hitachi Ltd | Manufacture of semiconductor device |
WO2001080310A1 (en) * | 2000-04-12 | 2001-10-25 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device |
-
1978
- 1978-07-18 JP JP8729378A patent/JPS5513953A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57109363A (en) * | 1980-12-26 | 1982-07-07 | Seiko Epson Corp | Semiconductor device |
JPS5955054A (en) * | 1982-09-24 | 1984-03-29 | Hitachi Ltd | Manufacture of semiconductor device |
WO2001080310A1 (en) * | 2000-04-12 | 2001-10-25 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device |
US6461908B2 (en) | 2000-04-12 | 2002-10-08 | Koninklijke Phillips Electronics N.V. | Method of manufacturing a semiconductor device |
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