JPS5617039A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5617039A
JPS5617039A JP9358479A JP9358479A JPS5617039A JP S5617039 A JPS5617039 A JP S5617039A JP 9358479 A JP9358479 A JP 9358479A JP 9358479 A JP9358479 A JP 9358479A JP S5617039 A JPS5617039 A JP S5617039A
Authority
JP
Japan
Prior art keywords
film
substrate
coated
resist mask
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9358479A
Other languages
Japanese (ja)
Inventor
Akira Ando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9358479A priority Critical patent/JPS5617039A/en
Publication of JPS5617039A publication Critical patent/JPS5617039A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the generation of an inversion layer under a film by a thin oxide film in a semiconductor device by forming a conductive substance durable for relatively high temperature in a field oxide film and connecting it to a substrate. CONSTITUTION:An SiO2 thin film 9 is formed on an Si substrate 1, a resist mask is formed thereon, an ion is implanted to form an inversion preventive layer 1' thereon, and an SiO2 film 9 is then perforated. Thereafter, a conductive substance 11 durable for relatively high temperature such as polysilicon or the like is accumulated thereon to diffuse the same conductivity impurity as the substrate 1 therein, and an SiO2 thin film 12 is coated thereon. Subsequently, a resist mask is coated thereon, openings are etched thereat, a gate oxide film 6 is formed on the substrate 1 being exposed, and a polysilicon film 7 is laminated thereon. Then, a resist mask is coated thereon, openings are selectively perforated thereat, and source and drain layers 5 are formed thereon. Since this configuration has equal potential in the film 11 to the substrate even if a voltage higher by double than the power supply voltage is applied to the polysilicon layer 8 for wiring, the inversion layer is formed only on the surface of the film 11 in the boundary between the films 12 and 11, but is not produced on the surface of the substrate.
JP9358479A 1979-07-20 1979-07-20 Semiconductor device Pending JPS5617039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9358479A JPS5617039A (en) 1979-07-20 1979-07-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9358479A JPS5617039A (en) 1979-07-20 1979-07-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5617039A true JPS5617039A (en) 1981-02-18

Family

ID=14086322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9358479A Pending JPS5617039A (en) 1979-07-20 1979-07-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5617039A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58124953U (en) * 1981-09-18 1983-08-25 三洋電機株式会社 Semiconductor integrated circuit device
JPS6045038A (en) * 1983-08-23 1985-03-11 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS6175555A (en) * 1984-07-02 1986-04-17 テキサス インスツルメンツ インコ−ポレイテツド Making of cmos twin well semiconductor device
JPS61248459A (en) * 1985-04-25 1986-11-05 Nippon Telegr & Teleph Corp <Ntt> Complementary type mis semiconductor integrated circuit
JPS6248041A (en) * 1985-08-28 1987-03-02 Nec Corp Semiconductor integrated circuit device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58124953U (en) * 1981-09-18 1983-08-25 三洋電機株式会社 Semiconductor integrated circuit device
JPS6244535Y2 (en) * 1981-09-18 1987-11-25
JPS6045038A (en) * 1983-08-23 1985-03-11 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS6175555A (en) * 1984-07-02 1986-04-17 テキサス インスツルメンツ インコ−ポレイテツド Making of cmos twin well semiconductor device
JPS61248459A (en) * 1985-04-25 1986-11-05 Nippon Telegr & Teleph Corp <Ntt> Complementary type mis semiconductor integrated circuit
JPS6248041A (en) * 1985-08-28 1987-03-02 Nec Corp Semiconductor integrated circuit device

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