JPS61248459A - Complementary type mis semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve total-dose strength by a method wherein different predeter mined voltages are applied to the first conductive type shield plate electrodes and the second conductive type shield plate electrodes formed on semiconductor element formation regions respectively. CONSTITUTION:N-type shield plate electrodes 5 are formed with MIS composi tion in an element separation region on an N-type semiconductor element forma tion region 2 and the first predetermined voltage V1 is applied to the electrodes 5. P-type shield plate electrodes 4 are formed with MIS composition in an ele ment separation region on a P-type semiconductor element formation region 1 and the second predetermined voltage V2 is applied to the electrodes 4. By applying two different voltages as the first predetermined voltage V1 and the second predetermined voltage V2, formation of inversion layers in the N-type semiconductor region and the P-type semiconductor region can be avoided. Therefore, the thickness of a gate oxide film 3 can be made as thin as several hundred Angstrom or less and hence a total-dose strength against radiation can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention provides a highly radiation-resistant complementary MIS (Metal
-In5ulator -Sem1conducto
r) It relates to semiconductor integrated circuits.

[Prior art and its problems]

Conventionally, in this type of semiconductor integrated circuit, a thick field oxide film has been used to isolate elements.

However, when such a device is irradiated with radiation such as an electron beam, the flat band voltage fluctuates significantly due to the charges in the oxide film generated by the radiation irradiation and the state at the oxide film-semiconductor substrate interface. This method has the disadvantage that the separation function is significantly impaired, resulting in a low so-called total dose tolerance.

Furthermore, in the space environment, high-energy heavy particles exist, and when these heavy particles enter a semiconductor integrated circuit, they generate a large number of electron-hole pairs within the semiconductor region. In circuits, this generated charge acts as a trigger and causes latch-up, resulting in loss of circuit function.

There is a problem that the element may be damaged.

In order to prevent the above latch-up, it is necessary to provide sufficient distance between the diffusion layer and the well. Therefore, increasing the latch-up resistance makes it difficult to increase the integration density.
Therefore, it has been difficult to realize a semiconductor integrated circuit with high latch-up resistance and high integration density.

Another possible solution to this problem is to improve latch-up resistance by lowering the parasitic resistance by using a low-resistance substrate and an epitaxial layer grown on it, but the effect is not sufficient, and Even if this method is used, the conventional device isolation technology using a thick field oxide film still has a problem in that the total dose tolerance is still low.

The present invention has been made to solve the problems of the prior art as described above. - The object is to provide a complementary MIS semiconductor integrated circuit with improved dose tolerance.

A further object of the present invention is to provide a complementary MIS semiconductor integrated circuit with improved total dose tolerance and latch-up resistance.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a gate electrode of a second conductivity type of an MIS structure formed on a semiconductor element formation region of the first conductivity type, and a semiconductor element formation region of the first conductivity type. A first conductivity type shield plate electrode (details of the shield plate electrode will be described later) of the MIS structure formed in the upper element isolation region and to which a first predetermined voltage is applied, and a second conductivity type semiconductor. A gate electrode of a first conductivity type of MISIJ structure formed on the element formation region and an element isolation region on the semiconductor element formation region of the second conductivity type, and a second predetermined voltage was applied. The structure includes a second conductivity type shield plate electrode having an MIS structure.

As described above, each semiconductor region is inverted by applying different predetermined voltages to the first conductivity type shield plate electrode and the second conductivity type shield plate electrode formed on the semiconductor element forming region. Since it is possible to prevent the formation of a layer and to make the field oxide film thinner, the total dose resistance can be improved.

In addition to the above structure, in another structure of the present invention, a groove is formed in a predetermined portion of the element isolation region in the semiconductor element formation region, and an insulator is provided on at least the inner wall surface of the groove. It consists of

By configuring as described above, the total dose tolerance is improved, and the groove described above blocks the distance between each element and the parasitic transistor formed between the elements, thereby preventing positive feedback between the parasitic transistors. Therefore, the effect of improving latch-up resistance can also be obtained.

In still another configuration of the present invention, in addition to the above configuration, an insulating film and a groove electrode are provided in the groove, and a predetermined area around the opening of the groove in the semiconductor element forming region is provided. A diffusion layer is formed to electrically connect the conductive electrode, the shield plate electrode, and the diffusion layer.

By configuring as above, the total dose resistance and latch-up resistance are improved, and the groove electrode and the diffusion layer are at the same potential, which prevents problems caused by the insulation resistance of the insulating film. .

When a positive charge is generated in the insulating film by irradiation with radiation such as an electron beam, and an inversion layer is formed around the groove by this charge, this inversion layer and the above-mentioned diffusion layer have the same potential.
No potential difference occurs in the insulating film sandwiched between the inversion layer and the groove electrode, and problems caused by the insulation resistance of the insulating film in this portion can be prevented.

[Embodiments of the invention]

FIG. 1 is a sectional view of a first embodiment of the present invention.

In FIG. 1, 1 is a p-type semiconductor element formation region, 2 is an n-type semiconductor element formation region, and 3 is a gate oxide film.

Further, 4 is a p-type shield plate electrode made of p-type polysilicon, 5 is an n-type shield plate electrode made of n-type polysilicon, and 6 is an n-type gate made of n-type polysilicon. electrode, n-channel MO8F
It becomes the gate electrode of ET. Further, 7 is a p-type gate electrode formed of p-type polysilicon, and a p-channel MO
This becomes the gate electrode of SFET. Further, 8 is an n1 diffusion layer, 9 is a p+ diffusion layer, and V, , Vi, and V2 indicate predetermined voltages.

Note that vl and v2 are voltages with different values, for example,
When the voltage V is Ov, (2) is the power supply voltage Vcc.

Conversely, if ■1 is the power supply voltage Vcc, v2 is Ov
shall be.

Note that vo is generally set to a value equal to v2, but may be a different value.

As described above, in the device shown in FIG.
An n-type shield plate electrode 5 to which is applied is formed in an MIS structure, and a p-type shield plate electrode to which a second predetermined voltage v2 is applied is formed in the element isolation region on the p-type semiconductor element formation region 1. 4 is formed with an MIS structure.

As described above, a method of forming an electrode with a MIS structure by applying a predetermined voltage to an element isolation region is called a shield plate method, and an electrode with this MIS structure is called a shield plate electrode.

By configuring as described above and applying voltages of different values as the first predetermined voltage v1 and the second predetermined voltage v2, the n-type semiconductor region and the p-type semiconductor region form an inversion layer. can be prevented.

Therefore, the oxide film (gate oxide film 3), which is an insulating film, can be made thinner to several hundred Å or less, and therefore, the total dose resistance against radiation can be improved.

Furthermore, in the configuration shown in FIG. 1, the shield plate electrode 5 formed on the n-type semiconductor element formation region 2 is
The shield plate electrode 4 is made of p-type polysilicon and is formed on the p-type semiconductor element formation region 1. The shield plate electrode 4 is made of p-type polysilicon and is formed on the n-type semiconductor element formation region 2. The gate electrode 7 of the p-channel MO8FET is formed of p-type polysilicon, and the gate electrode 7 of the p-channel MO8FET is formed on the p-type semiconductor element formation region 1.
The gate electrode 6 is made of n-type polysilicon.

As mentioned above, by using different conductivity types of polysilicon, which is the electrode material for the MOSFET and the shield plate electrode, for example, even if the thickness of the gate insulating film of the shield plate part and the active element is the same, each electrode Due to the effect of the work function difference between the
It is about 1v smaller than that of channel MO8FET,
In addition, in the p-type semiconductor element formation region, the threshold voltage of the shield plate portion is approximately 1 higher than that of the n-channel MO8FET.
Since v becomes large, it becomes possible to reduce the concentration of the channel stop layer in the semiconductor element forming region under the shield plate or to make the channel stop layer unnecessary.

In addition, as mentioned above, the shield plate electrode and MOSF
Even if polysilicon is used as the electrode material for ET and polysilicon of the same conductivity type is used without using different conductivity types, it is possible to reduce the concentration of the channel stop layer in the semiconductor element formation region under the shield plate, or Although the advantage of being able to omit it is lost, the total
It is clear that there is an advantage in improving the dose tolerance.

Next, FIG. 2 is a diagram showing a second embodiment of the present invention.
The same reference numerals as in the figure indicate the same thing.

In FIG. 2, 10 is a P1 diffusion layer, 11 is an n+ diffusion layer, and 12 is a contact hole in which a part of the gate oxide film directly under the shield plate electrode is removed.

Normally, in order to fix the potential of the semiconductor element formation region, a diffusion layer such as 10.11 shown in FIG. 2 is formed and connected to an electrode on the semiconductor surface to apply a voltage.

In the present invention, by selectively using the conductivity type of the polysilicon of the shield plate electrode depending on the conductivity type of the semiconductor element forming region, it is not necessary to form the diffusion layers 10 and 11 using a special method 1 such as ion implantation. It disappears.

That is, a contact hole 1 is formed in a part of the gate oxide film 3.
2 and shield plate electrodes 4 and 5, step 1 included in the subsequent process, for example, source
By the heat treatment in the drain forming step, impurities are diffused from the shield plate electrode into the semiconductor element formation region, and diffusion layers 10 and 11 are formed.

Furthermore, in FIG. 2, the p-type semiconductor element formation region 1 and the P-type shield plate electrode 4 are electrically connected by providing the p+ diffusion layer 1o. If the second predetermined voltage v2 is applied from the back surface of the substrate (substrate), the voltage is supplied to the p-type shield plate electrode 4 via the p+ diffusion layer 10, so that the voltage from the surface of the semiconductor element to the p-type shield plate electrode 4 is reduced. Application becomes unnecessary.

This eliminates the need for wiring, which has the effect of making it possible to further increase the density of integrated circuits.

Next, FIG. 3 is a diagram showing a third embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same parts.

In FIG. 3, 13 is an n-type semiconductor element forming region 2.
(n-well) is a groove formed around the periphery, and 13' is the groove 13
It is an insulator embedded inside. Further, 14 is a high impurity concentration region.

The device shown in FIG. 3 uses, for example, a high impurity concentration semiconductor substrate as the high impurity concentration region 14, and an epitaxial growth layer formed thereon is used as the p-type semiconductor element formation region 1 and n
It is used as the semiconductor element forming region 2 of the mold.

In the configuration of FIG. 3, an n+ diffusion layer 8, a p-type semiconductor element forming region 1. A parasitic lateral npn transistor formed by the n-type semiconductor element formation region 2 and the high impurity concentration region 14, the P+ diffusion layer 9, and the n-type semiconductor element formation region 2
, the high impurity concentration region 14 and the parasitic vertical pnp transistor formed in the p-type semiconductor element forming region 1 are blocked by a trench 13 filled with an insulator 13'.

Therefore, in combination with the effect of the high impurity concentration region 14, the positive feedback effect between the parasitic transistors described above is hindered.
Latch-up resistance is also improved.

Note that this improvement effect depends on the depth of the groove.

For example, high impurity concentration region 1 due to heat treatment during the process.
Considering impurity diffusion from 4 to the epitaxial growth layer, the depth of the groove 13 is 4 the thickness of the epitaxial growth layer.
It is necessary to form it to a depth of at least 300 mm.

As described above, according to the configuration shown in FIG. 3, it is possible to realize a high-density complementary MIS integrated circuit with improved total dose resistance and latch-up resistance.

Next, FIG. 4 is a diagram showing a fourth embodiment of the present invention, and FIG.
The same reference numerals as in the figure indicate the same thing.

In FIG. 4, 15 is an insulating film (for example, an oxide film) provided on the inner wall surface of the trench 13, and 16 is a polysilicon conductive electrode formed therein.

An MIS structure is formed by the insulating film 15, the conductive electrode 16, and the p-type semiconductor element formation region 1 (or the n-type semiconductor element formation region 2).

In the device shown in Figure 4, the latch-up resistance and the total dose resistance of the flat shield plate are as follows:
3, and since the thickness of the insulating film inside 'a13 can be made thinner than in the case of FIG. 3, the total dose resistance of the groove portion can be further improved.

Next, FIG. 5 is a diagram showing a fifth embodiment of the present invention, and the same reference numerals as in FIG. 4 indicate the same parts.

In FIG. 5, 17 is an n-type groove electrode formed of n-type polysilicon.

In the configuration shown in FIG. 5, the n-type semiconductor element forming region 2
A groove 13 is formed in the element isolation region including the interface between the semiconductor element forming region 1 and the p-type semiconductor element formation region 1, and includes the above-mentioned interface.
A MIS structure is formed together with a p-type semiconductor element formation region 1 and an n-type semiconductor element formation region 2.

The n-type groove electrode 17 and the n-type shield plate electrode 5 are electrically connected, and a first predetermined voltage v1
is applied.

In the above configuration, the n-type shield plate electrode 5 and the n-type
The mold groove electrode 17 is both made of n-type polysilicon, and these electrodes can be integrally formed from the same polysilicon material during the manufacturing process, and these electrodes can be electrically connected. No new wiring is required for this purpose.

In the apparatus shown in FIG. 4, when the oxide film 3 is formed on the conductive electrode 16 at the opening of the trench 13, the semiconductor elements around the trench opening are oxidized as the polysilicon of the conductive electrode 16 is oxidized. Although there is a possibility that crystal defects may occur in the formation regions 1 and 2, in the configuration shown in FIG.
Since it is formed integrally with the n-type shield plate electrode 5, there is no possibility of the above problem occurring.

In addition, in the configurations shown in FIGS. 3 to 5 above, the groove 13 and the conductive electrode 16, 17 are provided only at the lower part of the n-type shield plate electrode 5, but these grooves and groove electrodes are Since the grooves are provided for element isolation, the effect can be obtained even if grooves and groove electrodes having a similar structure are provided in other parts, for example, under the p-type shield plate electrode 4.

Moreover, it may be provided at both the lower part of the n-type shield plate electrode 5 and the lower part of the p-type shield plate electrode 4, or it may be provided at other parts.

However, as shown in the embodiment of FIG. 5, it is most desirable to form it in a portion including the boundary between the p-type semiconductor element formation region 1 and the n-type semiconductor element formation region 2.

Next, FIG. 6 is a diagram showing a sixth embodiment of the present invention, and the same reference numerals as in FIG. 5 indicate the same parts.

In FIG. 6, 18 and 19 are n+ diffusion layers.

In the structure shown in FIG. 6, the n-type semiconductor element forming region 2
An n+ diffusion layer 18 formed around the opening of the trench 13 within the trench 13 and an n+ diffusion layer 19 formed around the opening of the trench 13 within the p-type semiconductor element forming region 1 are provided inside the trench 13. It is electrically connected to the n-type groove electrode 17 and the n-type shield plate electrode 5 of the MIS structure, and a first predetermined voltage v0 is applied thereto.

In the above structure, the n+ diffusion layers 18 and 19 can be formed without adding any special process such as ion implantation.

For example, before forming the n-type shield plate electrode 5 made of n-type polysilicon, it is possible to remove the gate oxide film 3 on a predetermined region (the part where the n+ diffusion layer 18, 19 is to be formed). , n-type impurities are removed from the n-type polysilicon of the n-type shield plate electrode 5 into the semiconductor element forming regions 1 and 2 by a heat treatment step included in the step after forming the shield plate electrode 5, for example, the step of forming the source/drain layer. is diffused, thereby forming an n+ diffusion layer 18.19.

In the device shown in FIG. 6, the total dose tolerance is improved by thinning the gate oxide film using the shield plate method, and the provision of the groove 13 improves the parasitic npn transistor and the parasitic pnp transistor. This improves latch-up resistance,
By roughly providing n+ diffusion layers 18 and 19, n
+ Since the diffusion layers 18 and 19 have the same potential as the n-type semiconductor element formation region 2 and the n-type groove electrode 17 in the groove 13, the n
+Insulating film 15 sandwiched between diffusion layer 19 and n-type groove electrode 17
and n-type semiconductor element formation region 2 and n + diffusion layer 18 and n
Since no voltage difference occurs between the two sides of the insulating film 15 sandwiched between the mold groove electrode 17 and the mold groove electrode 17, it is possible to prevent problems caused by the insulation resistance of the insulating film in this portion.

In addition, positive charges are generated in the insulating film 15 by radiation irradiation such as electron beams, and when an inversion layer is formed around the groove 13 in the p-type semiconductor element forming region 1 due to this positive charge, this n in the inversion layer and p-type semiconductor element formation region 1
Since the +diffusion layer 18 is at the same potential, there is no potential difference between the two sides of the insulating film 15 sandwiched between the inversion layer and the n-type groove electrode 17, so problems due to the insulation resistance of this part can also occur. It can be prevented.

In the above explanation, the embodiment of the present invention was shown in a structure using an n-well, but the present invention can also be applied to a structure using a p-well or a structure using both wells. Of course.

Furthermore, the present invention can be applied to either n-type or p-type high impurity concentration region 14.

Further, the materials of the gate electrodes 6, 7 and shield plate electrodes 4, 5 of the MOSFET may be a so-called polycide structure in which a metal material is bonded to polysilicon in order to reduce the resistance.

〔Effect of the invention〕

As explained above, in the present invention, by using the shield plate method, it is possible to make the field oxide film thinner, thereby improving the total dose resistance due to radiation irradiation, and furthermore, by using the groove, the field oxide film can be made thinner. By separating them, latch-up resistance can be improved.

In addition, by using different conductivity types of the shield plate electrode and the gate electrode of the active element in the p-type semiconductor element formation region and the n-type semiconductor element formation region, channel stop to the semiconductor element formation region under the shield plate electrode can be achieved. Layer concentrations can be reduced or omitted.

In addition, in order to fix the potential of the semiconductor region, a part of the gate oxide film under the shield plate electrode is removed, and the same conductivity type as each semiconductor element formation region is formed by diffusion from the polysilicon that will become the shield plate electrode. Since a high impurity concentration layer can be formed, there is no need to provide a special manufacturing process such as ion implantation in order to form such a high impurity concentration diffusion layer.

Furthermore, by embedding a polysilicon electrode in the groove via an insulating film and integrating the electrode with the shield plate electrode, the potential of the groove electrode can be fixed to the same potential as that of the shield plate electrode.

Furthermore, by providing a diffusion layer around the opening of the groove and electrically connecting the diffusion layer to the shield plate electrode and the groove electrode, problems with the withstand voltage of the insulating film inside the groove can be prevented. It has many excellent effects such as:

[Brief explanation of the drawing]

1 to 6 are cross-sectional views of embodiments of the present invention, respectively. <Explanation of symbols> 1... P-type semiconductor element formation region 2... N-type semiconductor element formation region 3... Gate oxide film

Claims (1)

[Claims] 1. In a complementary MIS semiconductor integrated circuit, a gate electrode of a second conductivity type of an MIS structure formed on a semiconductor element formation region of a first conductivity type; A shield plate electrode of the first conductivity type of the MIS structure is formed in the element isolation region on the semiconductor element formation region of and to which the first predetermined voltage is applied, and a shield plate electrode of the first conductivity type is formed on the semiconductor element formation region of the second conductivity type. A gate electrode of the first conductivity type of the MIS structure formed and a gate electrode of the MIS structure formed in the element isolation region on the semiconductor element formation region of the second conductivity type and to which a second predetermined voltage is applied. A complementary MIS semiconductor integrated circuit comprising a shield plate electrode of two conductivity types. 2. The shield plate electrode of the first conductivity type is electrically connected to the semiconductor element formation region of the first conductivity type located below it, and the shield plate electrode of the second conductivity type is located below it. 2. The complementary MIS semiconductor integrated circuit according to claim 1, wherein the complementary MIS semiconductor integrated circuit is electrically connected to a semiconductor element formation region of the second conductivity type. 3. In a complementary MIS semiconductor integrated circuit, a second conductivity type gate electrode of the MIS structure formed on the first conductivity type semiconductor element formation region, and a second conductivity type gate electrode formed on the first conductivity type semiconductor element formation region. A shield plate electrode of the first conductivity type of the MIS structure formed in the element isolation region and to which the first predetermined voltage is applied, and a shield plate electrode of the MIS structure formed on the semiconductor element formation region of the second conductivity type. A gate electrode of a first conductivity type and a shield of a second conductivity type of the MIS structure formed in an element isolation region on the semiconductor element formation region of the second conductivity type and to which a second predetermined voltage is applied. plate electrode;
A complementary MIS semiconductor integrated circuit comprising a trench formed in a predetermined portion of an element isolation region in the semiconductor element forming region, and an insulator provided on at least an inner wall surface of the trench. 4. The groove is formed in a predetermined portion of the element isolation region including at least the interface between the semiconductor element formation region of the first conductivity type and the semiconductor element formation region of the second conductivity type. 4. A complementary MIS semiconductor integrated circuit according to claim 3. 5. Form an insulating film on the inner wall surface of the above groove, and M
A complementary MIS semiconductor integrated circuit according to claim 3 or 4, characterized in that a trench electrode having an IS structure is provided. 6. Form an insulating film on the inner wall surface of the above groove, and form an M
Complementary MIS according to claim 3, characterized in that a groove electrode of IS structure is provided, and the shield plate electrode of the first or second conductivity type and the groove electrode are connected. Semiconductor integrated circuit. 7. In a complementary MIS semiconductor integrated circuit, a gate electrode of a second conductivity type of the MIS structure formed on the semiconductor element formation region of the first conductivity type, and a gate electrode of the second conductivity type formed on the semiconductor element formation region of the first conductivity type. A shield plate electrode of the first conductivity type of the MIS structure formed in the element isolation region and to which the first predetermined voltage is applied, and a shield plate electrode of the MIS structure formed on the semiconductor element formation region of the second conductivity type. A gate electrode of a first conductivity type and a shield of a second conductivity type of the MIS structure formed in an element isolation region on the semiconductor element formation region of the second conductivity type and to which a second predetermined voltage is applied. plate electrode;
a groove formed in a predetermined portion of the element isolation region in the semiconductor element formation region; an insulating film provided on the inner wall surface of the groove; and a shield plate of the first conductivity type disposed therein. a first conductivity type groove electrode of the MIS structure connected to the electrode; and a first conductivity type groove electrode formed in a predetermined area around the opening of the groove in the first conductivity type semiconductor element formation region. a first diffusion layer formed in a predetermined region around the opening of the trench in the second conductivity type semiconductor element formation region;
A complementary MIS semiconductor integrated circuit comprising a diffusion layer of a conductivity type, and having a structure in which one or both of the two diffusion layers and the shield plate electrode of the first conductivity type are electrically connected.