JP2009026874A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a high element integration degree which has a sufficient element separation characteristic and latch-up resistance at a high power supply voltage circuit with no increase in the number of processes, while a trench separation identical with that of the high power supply voltage circuit is used even at a low power supply voltage circuit. <P>SOLUTION: In the semiconductor device having a trench separation structure, polysilicon layers 771 and 772 are embedded in a trench separation region 301 near ends of well regions 201 and 202, to prevent the formation of an inversion layer formed in a parasitic manner on the surface of the semiconductor substrate because of the potential of wiring. Their conductive types are identical with those of the well region and the semiconductor substrate on the lower surface. The distance between the side surface of the trench separation region and the polysilicon layer is longer than that between the bottom surface of the trench separation region and the polysilicon layer so that the formation of the inversion layer on the lower surface of the trench region is prevented while insulation characteristics for an MOS type transistor is maintained. This effectively prevents the formation of the inversion layer and prevents the occurrence of latch up. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a trench isolation structure such as a CMOS device having multiple power supply voltages using trench isolation as an element isolation structure.

  In a semiconductor device having a CMOS device that uses multiple power supply voltages, the degree of integration of a low power supply voltage part constituting an internal circuit such as a logic circuit is improved and an element isolation region of a high power supply voltage part used for an input / output circuit or the like It is important to prevent the formation of a parasitic transistor in order to ensure latch-up resistance.

  In recent years, a trench isolation method suitable for higher integration than the LOCOS method is often employed for element isolation. However, in the LOCOS method, a region having a high impurity concentration for preventing the generation of a parasitic channel, a so-called channel stopper region or a field doped region can be easily provided, and the inversion of the semiconductor substrate under the LOCOS can be prevented. Therefore, the element isolation characteristics of the high voltage power supply circuit were excellent. On the other hand, in a semiconductor device in which elements are isolated by trench isolation, a parasitic inversion layer is formed on the surface of the semiconductor substrate below the trench isolation region due to the potential of the wiring passing over the trench isolation region, so-called parasitic channels are likely to occur. There was a problem, and in particular, the formation of the high voltage power supply circuit part was hindered.

  Here, the formation of the inversion layer and the parasitic channel and the latch-up caused by them will be described with reference to FIG.

  FIG. 4 is a schematic cross-sectional view showing a part of a high power supply voltage circuit portion of a conventional semiconductor device.

  On a P-type silicon substrate 101 as a first conductivity type semiconductor substrate, a P-well region 201 composed of a P-type low-concentration impurity region as a first well and an N-type low-concentration impurity region as a second well. A well region 202 is formed adjacently, and an N-type high-concentration impurity region 501 that is a source or drain region of an N-type MOS transistor, for example, is formed on the surface of the P-well region 201. On the surface, for example, a P-type high-concentration impurity region 502 which is a source or drain region of a P-type MOS transistor is formed, and a trench isolation region 301 for element isolation is formed therebetween. The trench isolation region 301 is generally filled with an insulator such as a silicon oxide film. In addition, a wiring 901 made of aluminum or the like for electrically connecting each element is disposed on the upper portion thereof via a first insulating film 601 made of a silicon oxide film or the like.

  In a high power supply voltage circuit using, for example, 30 V as the power supply voltage, a potential of 30 V may be supplied to the wiring 901 in some cases. At this time, since the potential of the P well region 201 is at the ground level (0 V), an N-type inversion layer 921 is easily formed below the trench isolation region 301 of the P well region 201. As a result, the parasitic transistor including the N-type high-concentration impurity region 501, the N-type inversion layer 921, and the N-well region 202 becomes conductive, and an on-current is generated. Due to the potential drop in the N-well region 202 due to this on-current, the vertical parasitic PNP transistor composed of the P-type high concentration impurity region 502, the N-well region 202, and the P-type silicon substrate 101 is turned on. As a result, the potential of the P-well region 201 rises, causing a so-called latch-up phenomenon.

  In order to make the high power supply voltage circuit section have sufficient latch-up resistance, it is necessary to reduce the parasitic bipolar operation by increasing the depth of the well, and to suppress the leakage current between the NMOS transistor and the PMOS transistor, and withstand voltage sufficiently Therefore, it is necessary to increase the isolation width of the trench isolation part.

Furthermore, the well depth of the high power supply voltage circuit section is made deeper than the well depth of the low power supply voltage circuit section, or the trench isolation width of the high power supply voltage circuit section is set to the trench isolation width of the low power supply voltage circuit section. A method of making it wider than that has also been proposed. (For example, refer to Patent Document 1.)
JP 2000-58673 (FIG. 1)

  However, in the semiconductor device using the multiple power supply voltage separated by trench isolation as described above, the well bipolar circuit is formed by increasing the well depth in order to give the high power supply voltage circuit portion sufficient latch-up resistance. It is necessary to suppress the operation, and it is necessary to increase the isolation width of the trench isolation part in order to suppress the leakage current between the NMOS transistor and the PMOS transistor and to secure the inversion withstand voltage characteristic. However, when the same trench isolation as that of the high power supply voltage circuit unit is used, there is a problem that the degree of integration of the elements of the low power supply voltage circuit unit that requires a high degree of integration is lowered.

  Also, the well depth of the high power supply voltage circuit section is made deeper than the well depth of the low power supply voltage circuit section, and the isolation width of the trench isolation section of the high power supply voltage circuit section is wider than that of the low power supply voltage circuit section. However, there have been problems such as an increase in manufacturing steps and an increase in separation width leading to an increase in cost.

  In order to solve the above problems, the present invention is configured as follows.

  It has a high power supply voltage circuit portion and a low power supply voltage circuit portion on a semiconductor substrate, and has a trench isolation structure in which each element in the high power supply voltage circuit portion and the low power supply voltage circuit portion is separated by a trench isolation region. The power supply voltage circuit unit includes an inversion layer formed parasitically on the surface of a semiconductor substrate by a potential of a wiring in a semiconductor device having at least one well region, a MOS transistor, and a wiring for electrically connecting each element. In order to prevent the occurrence, a polysilicon layer is buried in the trench isolation region near the end of the well region, and the conductivity type of the polysilicon layer is different from that of the semiconductor substrate or well region located on the lower surface of the polysilicon layer, respectively. It was made to be the same conductivity type.

  The polysilicon layer in the trench isolation region is formed so that the distance between the side surface of the trench isolation region and the polysilicon layer is larger than the distance between the bottom surface of the trench isolation region and the polysilicon layer. The MOS layer transistor formed adjacent to the trench isolation region is effectively suppressed by effectively utilizing the work function difference due to the conductivity type of the polysilicon layer to suppress the generation of the inversion layer that may be parasitically formed in the MOS layer. The insulating property can be maintained even when a high voltage is applied to the drain region and the source region including the impurity concentration region.

  The polysilicon layer is composed of a first conductivity type region and a second conductivity type region, and the first conductivity type region and the second conductivity type region are within the same polysilicon layer. It was made to form continuously.

  Then, the potential of the polysilicon layer is fixed so as to be the same potential as that of the semiconductor substrate or well region located on the lower surface of the polysilicon layer, and the inversion layer at a fixed potential in addition to the work function. The formation of was more strongly prevented.

  Alternatively, when a semiconductor substrate or well region having a relatively high impurity concentration is used, the semiconductor substrate has a high power supply voltage circuit portion and a low power supply voltage circuit portion on the semiconductor substrate. The device has the trench isolation structure in which each element in the circuit part is isolated by a trench isolation region, and the high power supply voltage circuit part has at least one well region, a MOS transistor, and a wiring for electrically connecting the elements. In a semiconductor device, a polysilicon layer is embedded in a trench isolation region near the end of a well region in order to prevent the occurrence of an inversion layer formed parasitically on the surface of a semiconductor substrate due to the potential of a wiring. The silicon layer is formed with the same conductivity type as the region with the lowest impurity concentration in the semiconductor substrate or well region located on the lower surface of the polysilicon layer. In Rukoto and to prevent more easily latch-up by preventing the inversion layer formed concentrate to more easily an inversion layer is formed side.

  According to the present invention, the same trench isolation as that of the high power supply voltage circuit unit is used in the low power supply voltage circuit unit while the high power supply voltage circuit unit has sufficient element isolation characteristics and latch-up resistance without increasing the number of processes. However, a semiconductor device having a high degree of element integration can be obtained.

  FIG. 1 is a schematic cross-sectional view showing a first embodiment of the high power supply voltage circuit portion of the semiconductor device of the present invention.

  On a P-type silicon substrate 101 as a first conductivity type semiconductor substrate, a P-well region 201 composed of a P-type low-concentration impurity region as a first well and an N-type low-concentration impurity region as a second well. A well region 202 is formed adjacently. An N-type high-concentration impurity region 501 that is a source or drain region of an N-type MOS transistor, for example, is formed on the surface of the P-well region 201, and an N-well region 202 is also formed. For example, a P-type high-concentration impurity region 502 which is a source or drain region of a P-type MOS transistor is formed on the surface, and a trench isolation region 301 for element isolation is formed therebetween. In general, the trench isolation region 301 is filled with an insulator such as a silicon oxide film.

  A P-type polysilicon layer 771 is formed in the trench isolation region 301 for element isolation on the P well region 201. Although not shown, the potential thereof is the same as that of the P well region 201. Fixed connection.

  Here, the insulating film thickness 911 on the side surface of the trench, which is the lateral distance between the P-type polysilicon layer 771 and the trench isolation region 301, is the vertical distance between the P-type polysilicon layer 771 and the trench isolation region 301. The N-type high-concentration impurity region 501 is a source or drain region of an N-type MOS transistor formed adjacent to the trench isolation region 301. Even when a high voltage is applied, good insulation is maintained without causing dielectric breakdown, and it is effective to form an inversion layer that may be formed on the lower surface of the trench region 301 by utilizing the work function difference. Can be suppressed.

  In the trench isolation region 301 for element isolation on the N well region 202, an N type polysilicon layer 772 is formed. Although not shown, the potential thereof is the same as that of the N well region 202, so that it becomes, for example, a power supply voltage. Fixed connection. In this embodiment, the P-type polysilicon layer 771 and the N-type polysilicon layer 772 are not in contact with each other and are separated with the trench isolation region 301 interposed therebetween.

  Here, similarly to the relationship between the P-type polysilicon layer 771 and the trench isolation region 301, the relationship between the N-type polysilicon layer 772 and the trench isolation region 301 is also a trench having a horizontal interval. The insulating film thickness on the side surface is set wider than the insulating film thickness on the bottom surface of the trench, which is the vertical interval, and is a source or drain region of a P-type MOS transistor formed adjacent to the trench isolation region 301. Even when a relatively high voltage is applied to the N-type high-concentration impurity region 502, good insulation is maintained without causing dielectric breakdown, and a work function difference is used to form the lower surface of the trench region 301. It is possible to effectively suppress the formation of the inversion layer that may be formed.

  A wiring 901 made of aluminum or the like for electrically connecting each element is formed on the trench region 301 via a first insulating film 601 and a second insulating film 801 made of a silicon oxide film or the like. ing.

  Here, even when a high potential of 30 V, for example, is supplied to the wiring 901, the P-type polysilicon layer 771 is formed in the trench region 301, and the potential is fixed to be the same as that of the P well region 201. Therefore, an N-type inversion layer is not formed on the surface of the P-well region 201.

  Here, even if it is arranged in a floating state without fixing the potential of the P-type polysilicon layer 771 formed in the trench region 301, the lower surface of the P-type polysilicon layer 771 depends on the work function of the P-type conductor itself. Since the effect of preventing the formation of the inversion layer on the surface of the P-well region 201 located in the region is not fixed, the potential of the P-type polysilicon layer 771 is not fixed from the viewpoint of layout restrictions and cost. Usage is also possible in some cases.

  On the other hand, when a low potential such as 0V is supplied to the wiring 901, for example, the potential difference from the surface of the N well region 202 fixed to a high power supply voltage of 30V, for example, increases. However, according to the present invention, the N-type polysilicon layer 772 is formed in the trench region 301, and the potential thereof is the same as that of the N-well region 202. Therefore, a P-type inversion layer is not formed on the surface of the N-well region 202.

  Here, even if the potential of the N-type polysilicon layer 772 is arranged in a floating state as in the description of the P-type polysilicon layer 771, depending on the work function of the N-type conductor itself, Since it has the effect of preventing the formation of an inversion layer on the surface of the N well region 202 located on the lower surface, the potential of the N type polysilicon layer 772 can be fixed from the viewpoint of layout restrictions and cost. Usage methods that are not performed are possible in some cases.

  As described above, according to the present invention, it is possible to effectively prevent the formation of the inversion layer and to prevent the occurrence of latch-up that may be caused thereby.

  In the example of FIG. 1, an example having the first insulating film 601 and the second insulating film 801 is shown, but only one of the first insulating film 601 and the second insulating film 801 is arranged. Sometimes.

  As for the combination of the semiconductor substrate and the well region, the example of FIG. 1 shows an example in which a P-type silicon substrate is used as the first conductive semiconductor substrate, a P well is used as the first well, and an N well is used as the second well. In the case where an N-type silicon substrate is used as the first conductive semiconductor substrate, an N well is used as the first well, and a P well is used as the second well, the polarities in the example of FIG. 1 may be reversed.

  Further, in the case of a structure having only the well region of one conductive direction without having the well region of both the N well and the P well, for example, a P-type silicon substrate as the first conductivity type semiconductor substrate, When the well is composed of an N-well, the same effect can be obtained if the P-type silicon substrate is replaced with the P-well region 201 in the example of FIG. In an example of an N type silicon substrate as a type semiconductor substrate and a P well as a second well, an N type silicon substrate as a first conductivity type semiconductor substrate, an N well as a first well, and a P well as a second well Similar to the case, the polarity may be reversed.

  Although illustration is omitted, in the low power supply voltage circuit portion of the semiconductor device according to the present invention, since the operating voltage is low, parasitic bipolar operation and latch-up hardly occur. Therefore, since the inversion layer formation preventing electrode as described above is not necessary, high integration can be achieved.

  FIG. 2 is a schematic cross-sectional view showing a second embodiment of the high power supply voltage circuit portion of the semiconductor device of the present invention.

  On a P-type silicon substrate 101 as a first conductivity type semiconductor substrate, a P-well region 201 composed of a P-type low-concentration impurity region as a first well and an N-type low-concentration impurity region as a second well. A well region 202 is formed adjacently. An N-type high-concentration impurity region 501 that is a source or drain region of an N-type MOS transistor, for example, is formed on the surface of the P-well region 201, and an N-well region 202 is also formed. For example, a P-type high-concentration impurity region 502 which is a source or drain region of a P-type MOS transistor is formed on the surface, and a trench isolation region 301 for element isolation is formed therebetween.

  A P-type polysilicon layer 771 is formed in the trench isolation region 301 for element isolation on the P-well region 201, and the side surface of the trench serving as a lateral distance between the P-type polysilicon layer 771 and the trench isolation region 301 is formed. The insulating film thickness 911 is set wider than the insulating film thickness 912 on the bottom surface of the trench, which is the vertical interval between the P-type polysilicon layer 771 and the trench isolation region 301, and is adjacent to the trench isolation region 301. Even when a high voltage is applied to the N-type high-concentration impurity region 501 that is the source or drain region of the N-type MOS transistor to be formed, good insulation is maintained without causing breakdown and a work function. By utilizing the difference, it is possible to effectively suppress the formation of an inversion layer that may be formed on the lower surface of the trench region 301.

  Further, in the trench isolation region 301 for element isolation on the N well region 202, an N type polysilicon layer 772 is continuously formed with the same polysilicon layer as the P type polysilicon layer 771, This point is different from the first embodiment described in FIG.

  Since it is not necessary to form a gap between the P-type polysilicon layer 771 and the N-type polysilicon layer 772, it is possible to reduce the lateral size of the isolation region.

  Other operations and functions will be described by adding the same reference numerals as those in FIG.

  As for the combination of the semiconductor substrate and the well region, several combinations are conceivable as in the example of FIG. 1, but the description is replaced with the description of the example of FIG.

  In this way, the present invention can effectively prevent the formation of the inversion layer, and also prevent the occurrence of latch-up that may be caused thereby.

  Although illustration is omitted, in the low power supply voltage circuit portion of the semiconductor device according to the present invention, since the operating voltage is low, parasitic bipolar operation and latch-up hardly occur. Therefore, since the inversion layer formation preventing electrode as described above is not necessary, high integration can be achieved.

  FIG. 3 is a schematic sectional view showing a third embodiment of the high power supply voltage circuit portion of the semiconductor device of the present invention.

  On a P-type silicon substrate 101 as a first conductivity type semiconductor substrate, a P-well region 201 composed of a P-type low-concentration impurity region as a first well and an N-type low-concentration impurity region as a second well. A well region 202 is formed adjacently. An N-type high-concentration impurity region 501 that is a source or drain region of an N-type MOS transistor, for example, is formed on the surface of the P-well region 201, and an N-well region 202 is also formed. For example, a P-type high-concentration impurity region 502 which is a source or drain region of a P-type MOS transistor is formed on the surface, and a trench isolation region 301 for element isolation is formed therebetween.

  A P-type polysilicon layer 771 is formed in the trench isolation region 301 for element isolation on the P well region 201 and the N well region 202, and the lateral direction between the P type polysilicon layer 771 and the trench isolation region 301 is formed. The insulating film thickness 911 on the side surface of the trench that is the distance between the trenches is set wider than the insulating film thickness 912 on the bottom surface of the trench that is the vertical distance between the P-type polysilicon layer 771 and the trench isolation region 301. Even when a high voltage is applied to the N-type high-concentration impurity region 501 which is a source or drain region of an N-type MOS transistor formed adjacent to the region 301, good insulation is achieved without causing dielectric breakdown. In addition, it is possible to effectively suppress the formation of an inversion layer that may be formed on the lower surface of the trench region 301 by utilizing the work function difference. Come.

  Here, the first embodiment described in FIG. 1 and the second embodiment described in FIG. 2 are different from each other in the trench isolation region 301 for element isolation on the P well region 201 and the N well region 202. Only the P-type polysilicon layer 771 is formed, and the N-type polysilicon layer 772 is not formed.

  In the third embodiment, the impurity concentration in the P well region 201 and the N well region 202 is relatively higher than that in the embodiment shown in FIGS. 1 and 2, and the impurity concentration in the P well region 201 is higher than the impurity concentration. Is assumed to be lower than the impurity concentration in the N well region 202.

  When the impurity concentration of the P well region 201 and the N well region 202 is relatively high, an inversion layer is hardly generated and latch-up is not easily generated without taking special measures. In this case, since only the low impurity concentration side needs to be monitored in order to make it safer, the element isolation trench isolation region 301 on the P well region 201 and the N well region 202 has P Only the polysilicon layer 771 of the type is formed to prevent the N-type inversion layer from being formed on the P well region 201 only. By forming only one conductivity type without forming two types of conductivity type polysilicon layers, the process can be simplified and shortened, and the cost can be reduced.

  Other operations and functions will be described by adding the same reference numerals as those in FIGS. 1 and 2.

  As for the combination of the semiconductor substrate and the well region, several combinations are conceivable as in the example of FIGS. 1 and 2, but the description is replaced with the description of the example of FIGS.

  In this way, the present invention can effectively prevent the formation of the inversion layer, and also prevent the occurrence of latch-up that may be caused thereby.

  Although illustration is omitted, in the low power supply voltage circuit portion of the semiconductor device according to the present invention, since the operating voltage is low, parasitic bipolar operation and latch-up hardly occur. Therefore, since the inversion layer formation preventing electrode as described above is not necessary, high integration can be achieved.

It is a typical sectional view showing the 1st example of the high power supply voltage circuit part of the semiconductor device of the present invention. It is a typical sectional view showing the 2nd example of the high power supply voltage circuit part of the semiconductor device of the present invention. It is a typical sectional view showing the 3rd example of the high power supply voltage circuit part of the semiconductor device of the present invention. It is typical sectional drawing which shows a part of high power supply voltage circuit part of the conventional semiconductor device.

Explanation of symbols

101 P-type silicon substrate 201 P-well region 202 N-well region 301 Trench isolation region 501 N-type high-concentration impurity region 502 P-type high-concentration impurity region 601 First insulating film 771 P-type polysilicon layer 772 N-type Polysilicon layer 801 Second insulating film 901 Wiring 911 Insulating film thickness on side of trench 912 Insulating film thickness on bottom of trench 921 N-type inversion layer

Claims (7)

  Having a high power supply voltage circuit portion and a low power supply voltage circuit portion on a semiconductor substrate, and having a trench isolation structure in which each element in the high power supply voltage circuit portion and the low power supply voltage circuit portion is separated by a trench isolation region The high power supply voltage circuit unit is a semiconductor device having at least one well region, a MOS transistor, and a wiring that electrically connects each element. In the high power supply voltage circuit unit, the potential of the wiring In order to prevent the occurrence of an inversion layer formed parasitically on the surface of the semiconductor substrate, a polysilicon layer is embedded in the trench isolation region disposed near the end of the well region. The conductivity type of the polysilicon layer is the same as that of the semiconductor substrate and the well region located on the lower surface of the polysilicon layer. The semiconductor device according to symptoms.   The polysilicon layer in the trench isolation region has a lateral distance between a side surface of the trench isolation region and the polysilicon layer, and a vertical direction between the bottom surface of the trench isolation region and the polysilicon layer. The semiconductor device according to claim 1, wherein the semiconductor device is formed so as to be wider than the distance.   The polysilicon layer is composed of a first conductivity type region and a second conductivity type region, and the first conductivity type region and the second conductivity type region are the same polysilicon layer. 3. The semiconductor device according to claim 1, wherein the semiconductor device is continuously formed in the semiconductor device.   4. The potential of the polysilicon layer is fixed to be the same potential as that of the semiconductor substrate or the well region located on the lower surface of the polysilicon layer, respectively. The semiconductor device according to 1.   The trench isolation having the high power supply voltage circuit section and the low power supply voltage circuit section on the semiconductor substrate, wherein each element in the high power supply voltage circuit section and the low power supply voltage circuit section is separated by a trench isolation region The high power supply voltage circuit unit is a semiconductor device having at least one well region, a MOS transistor, and a wiring that electrically connects each element. In the high power supply voltage circuit unit, A polysilicon layer is embedded in the trench isolation region disposed near the peripheral edge of the well region in order to prevent the occurrence of an inversion layer formed parasitically on the surface of the semiconductor substrate due to the potential of the wiring. The polysilicon layer has the lowest impurity concentration in the semiconductor substrate or the well region located on the lower surface of the polysilicon layer. Wherein a that are formed of the same conductivity type as the region.   The polysilicon layer in the trench isolation region has a lateral distance between a side surface of the trench isolation region and the polysilicon layer, and a vertical direction between the bottom surface of the trench isolation region and the polysilicon layer. The semiconductor device according to claim 5, wherein the semiconductor device is formed so as to be wider than the distance.   The potential of the polysilicon layer is fixed to be the same potential as a region having the lowest impurity concentration in the semiconductor substrate or the well region located on the lower surface of the polysilicon layer. The semiconductor device according to claim 5 or 6.

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