JPS61107759A - Complementary type semiconductor device - Google Patents
Complementary type semiconductor deviceInfo
- Publication number
- JPS61107759A JPS61107759A JP59230608A JP23060884A JPS61107759A JP S61107759 A JPS61107759 A JP S61107759A JP 59230608 A JP59230608 A JP 59230608A JP 23060884 A JP23060884 A JP 23060884A JP S61107759 A JPS61107759 A JP S61107759A
- Authority
- JP
- Japan
- Prior art keywords
- well
- oxide film
- semiconductor
- burying
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 230000000295 complement effect Effects 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 230000000694 effects Effects 0.000 abstract description 6
- 230000003321 amplification Effects 0.000 abstract description 2
- 239000000969 carrier Substances 0.000 abstract description 2
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ランチアップを改善し、消費電力を減少さ
せた相補型半導体装置（以下ＣＭＯ８という）に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary semiconductor device (hereinafter referred to as CMO8) that improves launch-up and reduces power consumption.
微細化された０ＭＯ８において、高集積化を妨げる原因
の一つとして、ラッチアンプ耐圧の向上のために、Ｐチ
ャネルＭＯＳトランジスタ（以下ＰＭＯ８という）とＮ
チャネルＭＯ８）ランジスタ（以下ＮＭＯ８という）の
間隔を小さくできない点があった。これに対して、最近
では、各ウェル間の分離に深い溝を堀り、その中を酸化
膜または酸化膜とポリシリコンの積層により充填するト
レンチアイソレーションと呼ばれる方法が考えられてい
る（例えば、Ｋｏｈｙａｍａ ｅｔａｌ ’８３
Ｉ Ｅ Ｄ ＭＴｅＣｈｎｌＣａｌ Ｄｉｇｅｓｔ
ｐｐ １５１〜１５４参照）。In the miniaturized 0MO8, one of the reasons that hinders high integration is that the P-channel MOS transistor (hereinafter referred to as PMO8) and N
There was a problem in that the interval between channel MO8) transistors (hereinafter referred to as NMO8) could not be made small. In contrast, a method called trench isolation has recently been considered, in which deep trenches are dug to separate each well, and the trenches are filled with an oxide film or a stack of oxide films and polysilicon (for example, Kohyama etal '83
I E D MTeChnlCal Digest
(See pp. 151-154).
第２図は前記従来例のトレンチアイソレーションヲ用〜
為だ０ＭＯ８の断面図である。Ｎ型半纏体基板（以下Ｎ
型基板という）１の表面上に深いＮ型拡散領域（以下Ｎ
ウェルという）２と、深いＰ型拡散領域（以下Ｐウェル
という）３が形成され、Ｎウェル２中に前記ＰＭＯ８の
ドレイン４．ソース５．コンタクト用のＮ 拡散層７が
形成され、Ｐウェル３中にＮＭＯ８のドレイン６、ソー
ス１１、Ｐ＋拡散層１２が形成されている。また、前記
ＰＭＯ８，ＮＭＯ８の各トランジスタはポリシリコンの
ゲート電極８を有し、前記各トランジスタは厚い酸化膜
９によって分離されている。さらに、ＰウェルとＮウェ
ルの間に反応性イオンエッチ技術号を用いて深い溝を堀
り、この中に酸化膜１０が埋込まれている。Figure 2 is for the trench isolation of the conventional example.
It is a sectional view of Tameda0MO8. N-type semi-integrated substrate (hereinafter referred to as N
A deep N-type diffusion region (hereinafter referred to as N-type substrate) 1 is formed on the surface of a
A deep P-type diffusion region (hereinafter referred to as P-well) 3 is formed, and a drain 4 of the PMO 8 is formed in the N-well 2. Source 5. An N 2 diffusion layer 7 for contact is formed, and a drain 6 of NMO 8, a source 11, and a P+ diffusion layer 12 are formed in the P well 3. Further, each of the transistors PMO 8 and NMO 8 has a gate electrode 8 made of polysilicon, and each transistor is separated by a thick oxide film 9. Further, a deep groove is dug between the P well and the N well using a reactive ion etching technique, and the oxide film 10 is buried in this groove.
従来の０ＭＯ８は上記のように構成され、たとえばＰＭ
Ｏ８のドレイン４にＮウェル２の電位よりも低い雑音電
圧が印加されると、ＰＭＯ８のドレイン４よりＮウェル
２に正孔が注入される。このｍｆ［圧の一部はＰＭＯ８
のソース５より外部に流れるが、残りの正孔は横方向に
対しては、埋込みの酸化膜１，０により拡散することが
できず、Ｎ型基板１を経由してＰウェル３に拡散し、コ
ンタクト用のＰ 拡散層１２を通って外部に流れる。The conventional 0MO8 is configured as described above, and for example, PM
When a noise voltage lower than the potential of the N-well 2 is applied to the drain 4 of the O8, holes are injected into the N-well 2 from the drain 4 of the PMO8. This mf [part of the pressure is PMO8
However, the remaining holes cannot be diffused in the horizontal direction due to the buried oxide films 1 and 0, and diffuse into the P well 3 via the N type substrate 1. , flows to the outside through the P diffusion layer 12 for contact.
しかし、通常の埋込みの酸化膜１０がな〜・場合に比べ
て、その拡散長は長くなり途中のＮウェル２やＮ型基板
１中で再結合する確率が増大し、Ｐウェル３内に到達す
る正孔数が減少し、Ｐウェル３の電位変化が小さくなり
、帰還がかかり難くなりて、ラッチアップ耐圧が向上す
る。特にＮ型基板１が高濃度基板の場合は効果的である
。However, compared to the case where there is no ordinary buried oxide film 10, the diffusion length is longer, and the probability of recombination in the N-well 2 or N-type substrate 1 on the way increases, and it reaches the inside of the P-well 3. The number of holes flowing through the p-well 3 decreases, the potential change in the P well 3 becomes smaller, feedback becomes less likely to occur, and the latch-up breakdown voltage improves. This is particularly effective when the N-type substrate 1 is a highly doped substrate.
上記のような従来の０ＭＯ８では、Ｎウェル２とＰウェ
ル３を分離するように埋込みの酸化膜１０が設置されて
いるので、Ｐウェル３とＮ型基板１で形成されるＰ−Ｎ
接合の端面が埋込みの酸化膜１０に接している。したが
って、埋込みの溝を形成する場合忙シリコンエッチを使
用する結果、接合リーク′ｌＥ流が多くなるという問題
点があった。In the conventional 0MO8 as described above, a buried oxide film 10 is installed to separate the N well 2 and P well 3, so the P-N formed by the P well 3 and the N type substrate 1
The end surface of the junction is in contact with the buried oxide film 10. Therefore, when forming a buried trench, a rough silicon etch is used, resulting in an increase in junction leakage.
この発明は、かかる問題点を解決するためになされたも
ので、埋込みの酸化膜をＰウェルとＮウェルの接合面よ
りもずらして設置すること釦より、接合リーク電流を減
少させることができる０ＭＯ８を得ることを目的とする
。This invention was made in order to solve this problem, and it is possible to reduce the junction leakage current by placing the buried oxide film offset from the junction surface of the P well and the N well. The purpose is to obtain.
この発明に係る０ＭＯ８は第１の導電型または第２の導
電型の半導体領域のうち少くとも一方のを埋込んだもの
である。The OMO8 according to the present invention has at least one of the first conductivity type and the second conductivity type semiconductor region buried therein.
この発明においては、埋込みの酸化膜を、１４接する互
いに異なる４電型の半導体領域の少くとも一方の領域内
に設けることによって、導電型の異なる拡散ノーと半導
体基板とで構成されるＰ−Ｎ接合面が埋込みのば化膜と
接しなくなるので、前記酸化膜を埋込むための溝形成圧
よる影響を抑制する作用を行う。In this invention, by providing a buried oxide film in at least one region of four contacting semiconductor regions of four different conductivity types, a P-N formed of a diffusion node of different conductivity types and a semiconductor substrate is provided. Since the bonding surface is no longer in contact with the buried oxide film, the effect of the groove forming pressure for burying the oxide film is suppressed.
第１図はこの発明の一実施例を示す０ＭＯ８の断面図で
ある。第１図において、１〜１２は第２図と同一のもの
を示しており、Ｎ型基板１の表面ｌＣＮウェル２とＰウ
ェル３を形成し、こ、のＮウェル２中にＰＭＯ８のドレ
イン４．ゲート電極８゜ソース５．Ｎウェルコンタクト
用のＮ 拡散層１を形成し、Ｐウェル３中ＫＮＭＯ８の
ドレイン６゜ソース１１、Ｐウェルコンタクト用のＰ
拡散層１２を形成する。さらに埋込みの酸化膜１０をＰ
ウェル３とＮウェル２、Ｎ型基板１とで形成されるＰ−
Ｎ接合面上りＮウェル２側に設置する。FIG. 1 is a sectional view of 0MO8 showing one embodiment of the present invention. In FIG. 1, 1 to 12 are the same as in FIG. ．． Gate electrode 8° source 5. N diffusion layer 1 for N well contact is formed, drain 6° source 11 of KNMO8 in P well 3, P well contact
A diffusion layer 12 is formed. Furthermore, the buried oxide film 10 is
P− formed by well 3, N well 2, and N type substrate 1
Installed on the N well 2 side above the N junction surface.
こめ実施例におけるランチアンプ耐°圧の改善は、第２
図で説明した従来例と理論上は同じであり、埋込みの酸
化膜１０により【横方向へのキャリアの拡散を制限する
ことにより、横方向バイポーラトランジスタの電流増幅
率を小さくして帰還をかかり難くすることを応用してい
る。The improvement of the launch amplifier breakdown voltage in the embodiment is the second
The theory is the same as the conventional example explained in the figure, and the buried oxide film 10 [restricts the diffusion of carriers in the lateral direction, thereby reducing the current amplification factor of the lateral bipolar transistor and making it difficult to cause feedback. I am applying what I do.
さらに、酸化膜１０をＮウェル２内に入れることにより
、Ｐウェル３とＮウェル２．Ｎ型基板１によってできる
Ｐ−Ｎ接合面は酸化膜１０と接しなくなる０このため、
酸化膜１０を埋込むための溝を形成した場合の影響を抑
制することができて、接合リーク電流が低減され、消費
電力が減少する。Furthermore, by putting the oxide film 10 into the N well 2, the P well 3 and the N well 2. The P-N junction surface formed by the N-type substrate 1 no longer comes into contact with the oxide film 10. Therefore,
The influence of forming a trench for burying the oxide film 10 can be suppressed, reducing junction leakage current and reducing power consumption.
なお、上記実施例はＮウェル２中に埋込みの酸化膜１０
を形成した例であるが、Ｐウェル３に埋込んでもよく、
またＮウェル２、Ｐウェル３の両方に埋込んでも同様の
効果があることは明らかである。Note that the above embodiment has an oxide film 10 buried in the N well 2.
Although this is an example of forming a
Furthermore, it is clear that the same effect can be obtained even if both the N well 2 and the P well 3 are filled.
さらに、上記実施例はＮウェル２とＰウェル３の両方を
形成する場合の例であるが、基板とは反対のウェルのみ
を形成する場合も基板またはウェルの少くとも一方に埋
込みの酸化膜を形成すればよい。Further, although the above embodiment is an example in which both the N well 2 and the P well 3 are formed, when only the well opposite to the substrate is formed, a buried oxide film may be provided on at least one of the substrate or the well. Just form it.
さらＫ、埋込む物質は電気的絶縁が可能であり、二酸化
硅素以外にシリコン窒化膜等の絶縁膜または絶縁膜と導
電膜の多層構造でもよい。Furthermore, the material to be buried can be electrically insulated, and may be an insulating film such as a silicon nitride film or a multilayer structure of an insulating film and a conductive film other than silicon dioxide.
この発明は以上説明したとおり、第１または第２０半導
体領域のうち少くとも一方の領域内で。As described above, the present invention is performed in at least one of the first and twentieth semiconductor regions.
前記半導体憤域内に形成されるトランジスタに対して周
辺側に絶縁膜または絶縁膜と導電膜の積層膜を埋込んだ
ことにより、接合リーク電流の少いＣＭＯＳが得られる
効果がある。By embedding an insulating film or a laminated film of an insulating film and a conductive film on the peripheral side of the transistor formed in the semiconductor region, there is an effect that a CMOS with low junction leakage current can be obtained.
第１図はこの発明の一実施例を示す０ＭＯ８の断面図、
第２図は従来の０ＭＯ８の断面図である。
図において、１はＮ型基板、２はＮウェル、３はＰウェ
ル、４はドレイン、５はソース、６はドレイン、７はＮ
拡散層、８はゲート電極、９は酸化膜、１Ｇは酸化膜
、１１はソース、１２はＰ＋拡散層である。
なお、各図中同一符号は同一または相当部分を示す。FIG. 1 is a cross-sectional view of 0MO8 showing an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a conventional 0MO8. In the figure, 1 is an N-type substrate, 2 is an N-well, 3 is a P-well, 4 is a drain, 5 is a source, 6 is a drain, and 7 is an N-type substrate.
8 is a gate electrode, 9 is an oxide film, 1G is an oxide film, 11 is a source, and 12 is a P+ diffusion layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
を有する第１の半導体領域と、この第１の導電型と逆の
導電型である第２の導電型を有する第２の半導体領域と
からなり、第１の半導体領域内に第２の導電型チャネル
のトランジスタを、第２の半導体領域内に第１の導電型
チャネルのトランジスタを形成した相補型半導体装置に
おいて、第１または第２の半導体領域のうち少くとも一
方の領域内で、前記半導体領域内に形成される前記トラ
ンジスタに対して周辺側に絶縁膜または絶縁膜と導電膜
の積層膜を埋込んだことを特徴とする相補型半導体装置
。a semiconductor substrate; a first semiconductor region having the same first conductivity type as the semiconductor substrate; and a second semiconductor region having a second conductivity type opposite to the first conductivity type. In a complementary semiconductor device in which a transistor of a second conductivity type channel is formed in a first semiconductor region and a transistor of a first conductivity type channel is formed in a second semiconductor region, A complementary type characterized in that, in at least one of the semiconductor regions, an insulating film or a laminated film of an insulating film and a conductive film is embedded on the peripheral side of the transistor formed in the semiconductor region. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59230608A JPS61107759A (en) | 1984-10-30 | 1984-10-30 | Complementary type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59230608A JPS61107759A (en) | 1984-10-30 | 1984-10-30 | Complementary type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61107759A true JPS61107759A (en) | 1986-05-26 |
Family
ID=16910420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59230608A Pending JPS61107759A (en) | 1984-10-30 | 1984-10-30 | Complementary type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61107759A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02166761A (en) * | 1988-12-21 | 1990-06-27 | Nec Kyushu Ltd | Semiconductor device |
| US4980953A (en) * | 1987-08-26 | 1991-01-01 | Sumitomo Metal Industries, Ltd. | Binding-up band with locking structure |
| JPH05251551A (en) * | 1992-03-03 | 1993-09-28 | Mitsubishi Electric Corp | Semiconductor device |
| EP0948044A1 (en) * | 1998-03-25 | 1999-10-06 | Nec Corporation | Trench isolated wells in a semiconductor device |
-
1984
- 1984-10-30 JP JP59230608A patent/JPS61107759A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4980953A (en) * | 1987-08-26 | 1991-01-01 | Sumitomo Metal Industries, Ltd. | Binding-up band with locking structure |
| JPH02166761A (en) * | 1988-12-21 | 1990-06-27 | Nec Kyushu Ltd | Semiconductor device |
| JPH05251551A (en) * | 1992-03-03 | 1993-09-28 | Mitsubishi Electric Corp | Semiconductor device |
| EP0948044A1 (en) * | 1998-03-25 | 1999-10-06 | Nec Corporation | Trench isolated wells in a semiconductor device |
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