JPH0222858A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a suppression effect of a latch-up by keeping a small chip area and to reduce a variation in a characteristic of a transistor by a method wherein a power-supply wiring part used to supply a potential to a substrate or a well is buried and formed in a contact region formed under a main face of a substrate in a layer other than a signal wiring part and to be deeper than a source region and a drain region of the transistor. CONSTITUTION:Grooves which are deeper than a source region 6a and a drain region 7a are formed in an N-type well 2; an N<+> type diffusion region 8, for well contact use, formed by implanting ions of in N-type impurity and a diffusion region 8 formed by filling a metal layer of a high melting point are formed in the grooves which are deeper than the source region 6b and the drain region 7b in element formation regions other thin a first wiring part 9 and the N-type well; a P<+> type diffusion region 10, for substrate contact use, formed by implanting ions of a P-type impurity and a P<+> type diffusion region 10 are connected by using a second wiring part 11. Accordingly, it is possible to expand a cross-sectional area of the first wiring part and a second wiring part 9, 11, to reduce a resistance of the wiring part, to enhance a suppression effect of a latch-up and to reduce a variation in a characteristic if a transistor.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

[Prior Art] As shown in FIG. 3, a conventional semiconductor device includes an N-type well 2 provided on the main surface of a P-type silicon substrate 1;
a field oxide film 3 provided on the surface including the element formation region to define an element formation region; a gate insulating film 4 provided on the surface of the element formation region of the N-type well 2; and a gate electrode 5 provided on the gate insulation film 4. N-type well 2 aligned with gate electrode 5
A P channel type MOS transistor constituted by a source region 6a and a drain region 7a provided in the N type well 2, an N1 type diffusion region 8 for well contact provided in the N type well 2,
Gate electric 8! ! The insulating film 12 is connected to the N+ type diffusion region 8 through the opening provided in the insulating film 12 provided on the surface including the insulating film 5.
Wiring 9 extending over the gate electrode 5 and gate electrode 5 provided on the gate insulating film 4 and gate insulating JII 4 similarly provided on the surface of the element formation region other than the N-type well 2. An N-channel type MO3) transistor constituted by a source region 6b and a drain region 7b provided in a P-type silicon substrate 1 in alignment with the P-type silicon substrate 1, and a P+ type diffusion for substrate contact provided in the element formation region other than the N-type well 2. The wiring 11 is connected to the P+ type diffusion region 10 through an opening provided in the insulating film 12 and extends over the insulating film 12. Furthermore, as shown in FIG. 4, in order to improve the effect of suppressing latch-up and stabilize the characteristics of the transistor, it is necessary to provide a large number of contact holes 13 when supplying the potential of the substrate or well over a wide area. be.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, the power supply wiring for supplying the substrate potential is formed in the same layer as other signal wiring, which limits the arrangement of the signal wiring and makes wiring design difficult. The disadvantage is that the dimensions must be increased.

In addition, if it is necessary to supply the substrate potential with low contact resistance in order to improve the latch-up suppression effect and stabilize the transistor characteristics, it is necessary to provide a large number of contact holes to connect the power supply wiring and the substrate, or to It is necessary to form contact holes, but the number and shape of contact holes are limited due to the arrangement of signal wiring connected to the transistor, so the contact resistance value is increased,
This has the disadvantage of reducing the latch-up suppressing effect and making transistor characteristics unstable.

[Means to solve the problem]

A semiconductor device of the present invention includes a reverse conductivity type well provided in a -conductivity type semiconductor substrate, and a MOS transistor provided in each of the well and the semiconductor substrate other than the well, wherein the semiconductor device includes the well and the semiconductor substrate. A contact diffusion region provided deeper than the junction depth of the source and drain regions of the MOS transistor on one or both of the substrates, and a wiring provided embedded in the diffusion region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

As shown in FIG. 1, there is an N-type well 2 provided on the main surface of a P-type silicon substrate 1, a field oxide film 3 provided on the surface including the N-type well 2 to partition an element formation region, and an N-type well 2. Gate insulating film 4 provided on the surface of the element formation region 2
and a gate electrode 5 provided on the gate insulating film and a source region 6a provided in the N-type well 2 in alignment with the gate electrode 5.
and the drain region 7a.
3) N+ well contacts for transistors and well contacts formed by forming trenches deeper than the source region 6a and drain region 7a in the N-type well 2 and selectively ion-implanting N-type impurities.
A first wiring connecting the type diffusion region 8 and the diffusion region 8 formed by burying a metal layer having a melting point higher than the maximum processing temperature in the post-process in the groove, and forming the elements other than the N-type well 2 as well. An N region consisting of a gate insulating film 4 provided on the surface of the region, a gate electrode 5 provided on the gate insulating film 4, and a source region 6b and a drain region 7b provided in the P-type silicon substrate 1 in alignment with the gate electrode 5. A channel type MOS transistor and a P+ type substrate contact are formed by forming grooves deeper than the source region 6b and drain region 7b in the element formation region other than the N type well 2 and selectively implanting P type impurities. It has a diffusion region 10 and a second wiring 11 formed embedded in the trench and connected to the P+ type diffusion region 10.

FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

As shown in FIG. 2, a metal layer is embedded in each of the grooves provided in the N+ type diffusion region 8 for well contact and the P+ type diffusion region 10 for substrate contact, which were provided in the same manner as in the first embodiment. The first embodiment is similar to the first embodiment except that the first and second wirings 9 and 10 formed in the above are formed extending over the N+ type diffusion region 8 and the P+ type diffusion region 10, respectively, at the periphery of the groove. Same as example. In the second embodiment, the cross-sectional area of the first and second wirings can be increased, the resistance of the wiring can be lowered, the effect of suppressing latch-up can be increased, and the fluctuation in characteristics of the transistor can be reduced.

〔Effect of the invention〕

As explained above, in the present invention, a power supply wiring supplying a potential to a substrate or a well is formed by embedding it in a contact region formed deeper than the source/drain region of a transistor under the main surface of the substrate in a layer separate from the signal wiring. As a result, the substrate potential can be supplied to a wide area with a low contact resistance value, which has the effect of increasing the latch-up suppressing effect while maintaining a small chip area and reducing the variation in transistor characteristics.

In addition, when power supply wiring buried under the main surface of the substrate is used as the operating power source for transistors, it has the effect of increasing the tolerance for signal wiring design and reducing the area on the chip required for signal wiring. .

1... P type silicon substrate, 2... N type well, 3...
...field oxide film, 4...gate insulating film, wo...
- Gate electrode, 6a, 6b...source region, 7a, 7
b...Drain region, 8...N1 type diffusion region, 9...
... Wiring, 10... P+ type diffusion region, 11... Wiring, 12... Insulating film, 13... Contact hole.

Claims (1)

[Claims] In a semiconductor device including a well of an opposite conductivity type provided in a semiconductor substrate of one conductivity type, and a MOS transistor provided in each of the well and the semiconductor substrate other than the well, either or both of the well and the semiconductor substrate. A semiconductor device comprising: a contact diffusion region provided deeper than the junction depth of the source and drain regions of the MOS transistor; and a wiring provided embedded in the diffusion region.