JPH03239368A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve breakdown strength between a source and a drain and reliability by separately forming a drain region formed in a substrate between a first gate electrode and a second gate electrode, and a channel stopped formed under an insulating film. CONSTITUTION:A drain region 5 formed in a substrate 1 between first and second gate electrodes 13a and 13b, and a channel stopper 3 formed under an insulating film 2 are provided, and the region 5 and the stopper 3 are separately formed. Since the region 5 and the stopper 3 are separately formed in this manner, a breakdown strength between the source 4 and drain 5 is determined according to a junction breakdown strength between the region 5 and the silicon substrate 1. Accordingly, a decrease in the junction breakdown strength due to direct contact of the high concentration region 5 of different conductivity type with the stopper 3 can be suppressed. Thus, the breakdown strength between the source and the drain is improved, and its reliability is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and in particular to a MO8I
- This relates to improving the withstand voltage between the source and drain of transistors.

[Traditional holding techniques]

MO8 type integrated circuit (hereinafter referred to as MO3) started as a calculator IC.
(referred to as ICs) have continued to develop steadily, increasing their degree of integration and reliability. However, there are still many problems that need to be solved, and it is also necessary to improve the characteristics of the IC itself, such as improving withstand voltage.

Figure 6 shows the structure of a conventional MO8IC as an N-channel type M○S.
7 is a plan view showing a transistor (hereinafter referred to as NMOST), and FIG. 7 is a cross-sectional view taken along the line ■-■ in FIG. 6.

In the figure, (1) a semiconductor substrate made of silicon single crystal or the like (hereinafter referred to as a silicon substrate), +2! A field insulating film is formed on the silicon substrate (1) to isolate between elements, and a channel/channel is formed under the +3+ It field insulating film (2) to electrically isolate adjacent elements.
It is a stopper.

+4) and (5; are the source and drain regions formed on the inner center side of the field insulating film (2) in the silicon substrate (1), and (6) is the region between the source region (4) and the drain region (5). A gate insulating film (7) formed on the silicon substrate (1) located between the gate insulating film (6)
A gate electrode is formed on top of the gate electrode. (8) is an interlayer insulating film formed on the silicon substrate (1) to cover the gate electrode (7) and field insulating film (2), and (9) is an interlayer insulating film formed on the silicon substrate (1) to cover the gate electrode (7) and the field insulating film (2). It is an electrode wiring layer connected to the source fm region +41 and the drain region (5).

GOli;I drain region (5) and channel stopper f3+,! : The junction part (11) is especially the drain part (5) directly under the gate electrode (7) and the channel part.
This is the joint part with the stopper (3).

In this case, the silicon substrate (1) is of P type, the channel stopper (f3) is of P+ type, and the source head (4) and drain region (5) are of N type.

In this way, in the conventional NMO8T structure (well, the drain region (5) is connected to the channel stopper (3) in three directions around it.
It is close to 1. The drain surround (5), which is N-type, will form a junction with the silicon substrate (1), which is P-type, and the channel stopper (3), which is P-type, respectively. Looking at the junction breakdown voltage here, the junction between N-type and P-type14 exhibits characteristics in which the depletion layer is less likely to widen when a voltage is applied, and current flows more easily than in the junction between N-type and P-type. . Therefore, the drain region (5) which is N+ type and the chai le stopper (3) which is P+ type are connected.
) is the junction breakdown voltage between the N-type drain region (5) and the P
This is lower than the junction breakdown voltage with the silicon substrate (1) which is the mold. Also, the drain region (5) and the channel stopper (3)
), the gate “■ junction 5-) (Il
At +, electric field concentration is particularly likely to occur, and the withstand voltage is the lowest.

Therefore, the source (4) and drain (5) of this NMO3T
) was determined by the breakdown voltage at the junction 1ull of the drain region (5) and the channel stopper (3) directly to the gate.

[Problem to be solved by the invention]

Since the conventional MO8IC transistor is configured as described above, the drain region (5) forms a junction with the channel stopper (3). Drain region (5)
The junction breakdown voltage between the drain region (5) and the channel stopper (3) is lower than the junction breakdown voltage between the drain region (5) and the silicon substrate (1).
By forming a junction with 1, the withstand voltage between the source and drain is low (rl, poor reliability).
There was a problem with this.

The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a highly reliable MOS transistor with improved source-drain breakdown voltage.

[Means for Solving the Problems 1] A semiconductor 41 according to the present invention includes a first gate electrode formed on an active frequency region between an isolation insulating film provided on a silicon substrate, and a first gate electrode formed on an active region between an isolation insulating film provided on a silicon substrate; A second game formed from a part of the membrane over the active head)! a drain region formed on the substrate between the first gate electrode and the second gate electrode, and a channel stopper formed on the edge of the e-edge film; The area and the channel stopper are formed apart from each other.

[For production]

In the present invention, the drain 6n region and the channel stopper are spaced apart from each other in the -C formation, so that the source-drain breakdown voltage is determined by the junction breakdown voltage between the drain 6n region and the silicon substrate. Therefore, this has the effect of suppressing a reduction in junction breakdown voltage due to direct contact between the channel stopper and the drain region, which has a high concentration and is of a different conductivity type.

[Embodiment 1] An embodiment of the present invention will be described with reference to the drawings. It should be noted that the description of parts that are partially revised from the description of the conventional technology will be omitted as appropriate.

FIG. 1 is a plan view showing the structure of an NMOS T according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line 111I in FIG. 1.

In the figure, (1) to t51 and 9) are the same as the conventional one, and (12a) is located between the source carrier (4) and the drain region (5) and is formed on the silicon substrate (1). A first gate insulating film (12b) is formed on the silicon substrate film, and a second gate insulating film (12b) is formed between the source region (4), the drain region (5) and the field insulating film (2).
This is the gate insulating film.

(13a) is the first gate electrode formed on the first gate insulating film (12a), and (13b) extends from the second gate insulating film (12b) over a part of the field insulating film (2). This is the second gate electrode formed, and the first gate electrode (13a) and the second gate electrode (13b
) are electrically connected. 04) is a silicon substrate (1) covering the first and second gate electrodes (13a) and (13b) and the field@rim film (2).
This is an interlayer insulating film formed above.

The NMOS T configured as described above is manufactured as follows. This will be explained following FIG. First, a thin silicon oxide film (11a +161) is formed on the entire surface of the P-type silicon substrate (1) by thermal oxidation to a thickness of approximately 500 mm, and then a silicon nitride film (121 Below, it is called 343N4 membrane) +171 is about 1
Formed to a film thickness of 0,000 people. Here, this silicon oxide film (16) acts to relieve the stress of the Si3N4 film (13), which has a net stress of 10 I0 dyn/cm (FIG. 3(a)).

Next, a photoresist film 1181 is formed on the entire surface of the S isN* IPA (171), and this is patterned by photolithography technology.
1111 Mask the underlying Si3N4 film (17
) is removed by plasma etching. After that, from above the silicon substrate t1.1, for example, boron (
For example, the implantation energy of Bl ions is 50 KeV,
Inject with 3.5 x 10'7 m of dosic acid. As a result, P-type impurity loading (3a) is formed (Fig. 3(b)
)).

Next, after removing the photoresist film (141) by an ashing method or the like, wet oxidation using water vapor is performed to oxidize the silicon substrate (1) in the portion not covered with the 5ixN4 film t171, and the field insulating film (141) is oxidized. 2) is about 8
Formed to a thickness of 500 people. At this time, the field insulating film (2) also partially penetrates under the edge of the 5isN4 film (17). In addition, by forming the field insulating film (2), the P-type impurity that had already been implanted (3a
) is diffused to form a channel stopper (3) (FIG. 3(C)).

Next, the 5isN+ film 071 is removed by wet etching using, for example, phosphoric acid, and the silicon oxide film 06'l is further removed by wet etching using a hydrofluoric acid-based etching solution. After that, HC1! A gate insulating film uz is formed to a thickness of approximately 400 nm by oxidation (FIG. 3(d)).

Next, a polycrystalline silicon film is deposited on the entire surface of the gate insulating film tIZ to a thickness of approximately 3,500 nm using the CVD method, and in order to make it conductive, phosphorus (Pl) is doped at an impurity concentration of 10
After that, a photoresist film (not shown) is formed on the entire surface of this polycrystalline silicon film and patterned using photolithography technology. Using this resist pattern as a mask, the base layer is For example, a polycrystalline silicon film is coated with plasma using CF4 gas.
Remove by etching. When the photoresist film is then removed, only a portion of the polycrystalline silicon film remains. This becomes the first gate electrode (13a) and the second gate electrode (13b). Here, the first gate electrode (
13a) is located in the inner center of the field insulating film (2),
The second gate electrode (13b) is the transistor active carrier A.
It is formed in an annular shape around the field insulating film (2), and its inner portion extends on the field insulating film (2) leaving about 2 μm in this case. The first gate electrode (13a) and the second gate electrode (13b) are electrically connected (FIG. 3(e)).

Next, the portion of the gate insulating film 1 excluding the portion covered by the first and second gate 11X poles (13a) and (13b)
121 is removed by wet etching using a hydrofluoric acid-based etching solution. As a result, the first gate insulating film (12a) is placed under the first gate electrode (13a), and the second gate insulating film (12a) is placed under the second gate electrode (13b).
12b) are formed respectively, and the first gate electrode (13
The main surface of the silicon substrate (1) is exposed between a) and the second gate electrode (13b). Then the first
Using the second gate electrodes (13a) and (13b) as a mask, for example, N-type Arsenic (As) ions are implanted from above the silicon substrate (1) at an implantation energy of 40 KeV and at a dose port 4. Inject at X 1015/d. As a result, N-type impurities (4a) (5a)
is formed (Fig. 3(f)).

Next, P was applied to the entire surface of the silicon substrate (1) by CVD method.
SG (Phospho-8ilicate Glass
) An interlayer insulating film (14) is deposited to a thickness of about 6,000 layers. Thereafter, the silicon substrate tn is heat treated at about 950°C. At this time, N-type impurity regions (4a) (5
The As ions in a) are diffused to form a source bright region (4) and a drain region (5) (FIG. 3(g)).

Next, a photoresist film (not shown) is formed on the entire surface of the interlayer insulating film (14) and patterned using photolithography technology. Using this resist pattern as a mask, the interlayer insulating film (141) on the F base is removed by plasma etching. As a result, a portion of the main and complementary regions of the source bright region (4) and the drain region (5) are exposed. A contact hole is formed in the shape 1. At this time, a metal film such as aluminum silicon M (AiSi) is deposited on the entire surface of the interlayer insulating film +141 by sputtering to fill the contact hole. After that, by patterning the metal film, electrode wiring I+4+91 is formed which is connected to the source bright region (4) and drain region (5) through the contact hole (Fig. 3). (h)).

Furthermore, after this, by performing a predetermined process, N
MO8T is completed.

In the NMO8T configured as described above, the first gate electrode (13a) is located in the inner center of the field insulating film (2) and between the source bright region (4) and the drain region (5). The second gate electrode (13b) is formed in an annular shape around the transistor active board A, and the inner part of the second gate electrode (13b) extends over the field insulating film (2) leaving about 2 μm. Also, unlike in the conventional example, the drain carrier (5) is formed at a distance fL<< from which a junction is formed with the channel stopper (3).

This formation can be performed by self-alignment of the gate electrodes (13a) and (13b).

In this way, since the drain region (5) is formed apart from the channel stopper (3), the drain region (5) is formed apart from the channel stopper (3).
) and the silicon substrate +11, N
This will determine the breakdown voltage between the source and drain of MO3T. In addition, as mentioned above, an N-type drain ship (5)
The junction breakdown voltage between the P-type silicon substrate ('') is higher than the junction breakdown voltage between the N+ type drain (5) and the P-type channel stopper (3). Therefore, the breakdown voltage between the source and drain of NMO8T is This is an improvement over the conventional example, which is determined by the junction breakdown voltage between the drain bright region (5) and the channel stopper (3).

By the way, the source/drain breakdown voltage in this case is about 16V, which is about 2V higher than the conventional one.

By the way, in the above embodiment, the second gate electrode (1
3b) shows an IC formed in a ring shape around the active transistor A, but the present invention is not limited to this. That is, FIG. 4 shows N according to the second embodiment of the present invention.
FIG. 3 is a plan view showing the structure of MO8T. This one is the second
The gate electrode (13b) is not arranged on the left side of the source bright region (4) in the figure, but is arranged so as to surround the drain (4). Even with this configuration, the same effects as above can be achieved.

Further, FIG. 5 shows an NMO5 according to a third embodiment of the present invention.
It is a sectional view showing the structure of T. This one consists of a low-sensitivity N-type impurity diffusion layer (20a) on the drain and a high-density N-type impurity diffusion layer (20a).
LD formed from type impurity diffusion rt4 c2ob)
It has a D (Lightly Doped Draim) structure. In this case as well, the same effects as above can be obtained.

In addition, in the above embodiment, the drain is mounted on a ship (5).

2 and the channel stopper (31) are shown spaced apart by about 2 μm, but the invention is not limited to this. The spacing may be set as appropriate depending on the transistor to be formed. In short, the channel stopper 13) and a drain region (5) formed in a self-aligned manner by the gate electrode opening 31.
1 and +21 may be spaced apart by a predetermined dimension KM.

Further, in the above embodiment, NMO8T is shown, but it may be formed with a P-channel type MOS transistor or a complementary type MO3) transistor, and the same effect as above may be obtained. There is.

〔Effect of the invention〕

As detailed above, according to the present invention, since the drain of the MOS transistor is configured to be separated from the channel stopper, the withstand voltage between the source and drain of the MOS transistor is improved, and the element Characteristics and reliability can be improved.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the general structure of NMO8T according to the first embodiment of the present invention, FIG. 2 is a sectional view taken along the line n-■ in FIG. 1, and FIG. FIG. 4 is a plan view showing the a-mounting configuration of NMO3T according to the second embodiment of the present invention, and FIG. 5 is a cross-sectional view showing the main manufacturing process of the product shown in the figure. 6 is a cross-sectional view showing the configuration of the conventional NMO8T, and FIG. 6 is a plan view showing the general configuration of the conventional NMO8T.
FIG. 7 is a sectional view taken along the line ■--■ in FIG. 6. In the figure, (1) is a silicon substrate, (2) is a field insulating film, (3) is a channel stopper, (5) is a drain ship, (13a) is a first gate electrode, (13b)
is the second gate electrode, 121]I is the drain electrode, and A is the transistor active bright region. In addition, the same reference numerals in each figure indicate the same parts, and the same reference numerals indicate corresponding parts.

Claims (1)

[Claims] a first gate electrode formed on an active region of an isolation insulating film provided on a semiconductor substrate; a second gate electrode formed over a part of the insulating film over the active region; a drain region formed on the substrate between a first gate electrode and a second gate electrode, and a channel stopper formed under the insulating film, the drain region and the channel stopper being spaced apart from each other. The formed semiconductor device.