JPH06216380A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the drop of a drain withstand voltage in the case of miniaturization of an element in a semiconductor device having a field effect transistor(FET). CONSTITUTION:An FET and an element isolation part 11 are provided on semiconductor substrates 10a, 110b, and a channel stop region 13a is provided under the part 11. An at least region of a source region 15 and a drain region 16 of the FET in which a high voltage is applied and the region 13a are isolated in a structure, and a first buffer region 24 doped with a threshold value control impurity is provided between the both. A region adjacent to the isolation part under a gate electrode is a second buffer region 25 doped with the thresold value control impurity. When the element is miniaturized by the region 24, a concentration of the region 13a is increased to obtain a satisfactory drain withstand voltage while maintaining an element isolation function, and a leakage current between the drain and the source is prevented by the region 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a field effect transistor (hereinafter referred to as FET) and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a general structure of a semiconductor device provided with a field effect transistor (in particular, a MOSFET having a gate insulating film), there is one shown in FIG. That is, the gate electrode 12 is provided on the silicon substrate 10 of one conductivity type via the gate insulating film. A gate region 17 is formed in the silicon substrate 10 below the gate electrode 12 by doping an impurity for threshold control (hereinafter, referred to as “VT control”), that is, an impurity of the same conductivity type as the silicon substrate 10. There is. In the silicon substrate 10 on the side of the gate electrode 12, a drain region 16 and a source region 15 are formed which are doped with impurities having a conductivity type opposite to that of the silicon substrate 10. With such a configuration, the current between the source and the drain is to be controlled according to the bias voltage applied to the gate electrode 12. Further, in order to electrically insulate the region Rfet where the MOSFET is to be formed from other regions,
An element isolation 11 such as OCOS is provided, and in order to ensure the element isolation characteristics, a region immediately below the element isolation 11 is doped with impurities to form a so-called channel stop region 13a.
Is provided.

FIGS. 13A to 13E show such an FE.
A process of manufacturing an n-channel MOSFET of T is shown.

First, as shown in FIG. 13A, a silicon nitride film 31 is formed on a p-type silicon substrate 10 (or P-well) to open a region 31a where an element isolation is to be formed, and a channel stop is performed. A p-type impurity (boron or the like) for forming is implanted.

Next, as shown in FIG. 13B, LOCOS is formed in the opening 31a of the silicon nitride film 31 by thermal oxidation.
The element isolation 11 is formed. At this time, the p-type impurity implanted previously is diffused to form the channel stop region 13a.

After that, as shown in FIG. 13C, the silicon nitride film 31 is removed, a silicon oxide film 33 is formed on the silicon substrate 10, and phosphorus, which is an impurity for Vt control, is implanted from above. To do. In addition, p-channel MOSFE
A region where other elements such as T are formed is masked with a photoresist mask.

Next, as shown in FIG. 13D, after the silicon oxide film 33 is once removed, a clean gate insulating film 18 (a silicon oxide film or a two-layer film composed of a silicon oxide film and a silicon nitride film) is formed. Etc. are formed, and the gate electrode 12 made of polysilicon is formed thereon.

Next, as shown in FIG. 13E, with the photoresist mask 32 having an opening in the region surrounded by the element isolation 11 and the gate electrode 12 as a mask, a high concentration of a conductivity type opposite to that of the silicon substrate 10 is used. The impurities (for example, arsenic) are implanted to form the source region 15 and the drain region 16.

In the structure of such a MOS type FET, if the integration degree is not so high and the element isolation 11 is sufficiently wide and thick, the channel stop region 13 is formed.
It is not necessary to increase the impurity concentration in a so much,
For example, at a concentration of about 5 × 10 ¹⁶ cm ⁻³ , good element isolation characteristics can be obtained. However, in recent years, the width of element isolation has become narrower as the density of elements has increased, and it is technically difficult to grow a thick oxide film in this narrow pattern width, and it is possible to reduce the step difference. It is not preferable from the viewpoint. Therefore, there is no choice but to thin the oxide film for element isolation.
When the thickness of the oxide film for element isolation becomes thin as described above, unless the impurity concentration in the channel stop region 13a is increased, an inversion layer is generated in the channel stop region, so that the isolation characteristic deteriorates. For example, when the isolation width is 0.6 μm and the thickness of the oxide film is 300 nm, the impurity concentration in the channel stop region 13a is 1 × 10 ¹⁷ cm in order to secure sufficient element isolation characteristics.
^-The concentration must be about ^-3 or higher. However, 5
At an impurity concentration of about 10 ¹⁶ cm ^−3, the breakdown voltage near the boundary between the channel stop region 13 a (p type) and the drain region 16 (n type), that is, at the PN junction does not matter, but the channel stop When the impurity concentration of the region 13a is about 1 × 10 ¹⁷ cm ⁻³ , the depletion layer is suppressed from expanding and the breakdown voltage at the P—N junction is lowered.

Therefore, for example, the structure disclosed in Japanese Patent Laid-Open No. 3-283574 has a structure as shown in FIGS. 14 (a) to 14 (d). 14A is a plan view of the semiconductor device, FIG. 14B is a sectional view taken along line XIVb-XIVb, and FIG.
14C is a sectional view taken along line XIVc-XIVc, and FIG. 14D is XIVd-XI.
It is a Vd line sectional view. As shown in each figure, element isolation 1
1, the channel stop region 13a having a relatively high concentration of impurities is not provided below the entire region 1, but the channel stop region 13a is offset from the end of the element isolation 11 to the element isolation 11 side by a predetermined distance. That is, the offset region 20 having a low concentration of impurities is formed over a predetermined width between the end of the element isolation 11 and the channel stop region 13a. Thus, by ensuring the offset region 20 of the low concentration impurity, the expansion of the depletion layer is ensured and the breakdown voltage at the P-N junction is ensured.

Further, as disclosed in, for example, Japanese Patent Application Laid-Open No. 2-15672, there is one shown in FIGS. 15 (a) to 15 (d). FIG. 15A is a plan view of the semiconductor device, and FIG.
(B) to (d) are XVb-XVb line sectional views, XVc-
FIG. 6 is a cross-sectional view taken along line XVc and XVd-XVd. As shown in each figure, in the overlap region 21 where the element isolation 11 and the gate electrode 12 overlap, a portion 22 adjacent to the drain region 16 is a part of the offset region 20 doped with a low concentration of impurities. It is a division. However, the portion 23 of the overlap region 21 adjacent to the source region 15 is not a part of the offset region 20 but a part of the channel stop region 13a doped with a relatively high concentration of impurities.

[0012]

However, each of the above publications has the following problems.

The former publication (JP-A-3-283574).
14C, the overlap region 2 between the element isolation 11 and the gate electrode 12 in FIG.
In No. 1, when the silicon is thermally oxidized to form the element isolation 11, a low concentration impurity (for example, n
In the channel FET, p-type impurities such as boron are diffused into the element isolation 11 to reduce the interface concentration in the offset region 20. Then, if the inversion layer is generated due to the further decrease of the impurity concentration in the offset region 20, there is a possibility that a leak current may be generated between the drain region 16 and the source region 15 via the overlap region 21. Also in the process, in order to form the offset region 20, it is necessary to provide a sidewall on the sidewall of the silicon nitride film 31 for forming the LOCOS (see FIG. 2C in the publication). Two extra steps need to be added to form and remove the wall.

On the other hand, the latter publication (Japanese Patent Laid-Open No. 2-156).
72), in the overlapping region 21 where the element isolation end portion and the gate electrode 12 overlap, the portion 2 except the portion 22 adjacent to the drain region 16
By extending the channel stop region 13a to 3,
It is possible to prevent the generation of the inversion layer in this portion 23 and prevent the drain-source leak current.

However, even in that case, similarly to the former publication, it is necessary to provide a sidewall on the side of the silicon nitride film for element isolation in order to form the channel stop 13a, and two steps are added. There is a need to. Further, in particular, in order to partition the part 22 adjacent to the drain region 16 and the part 23 adjacent to the source region 15 in the region 21 where the end of the element isolation 11 and the gate electrode 12 overlap, a silicon nitride film is formed. It is necessary to accurately align the mask for patterning with the mask for forming the gate electrode. However, with the miniaturization of the transistor structure, the width of the gate electrode tends to be narrowed, which causes difficulty in alignment.

The present invention has been made in view of the above circumstances, and its object is to add a process, difficulty in alignment, and generation of a leak current in an overlap region between an element isolation and a gate electrode. It is another object of the present invention to provide a low-cost semiconductor device suitable for high integration and a method for manufacturing the same, by taking measures to secure the breakdown voltage between the channel stop and the drain.

[0017]

In order to achieve the above object, specifically, the means taken by the invention of claim 1 is a field effect type in an element forming region of a semiconductor substrate doped with a first conductivity type impurity. A semiconductor device equipped with a transistor is assumed. A gate electrode of the field effect transistor formed on the semiconductor substrate and a region of the semiconductor substrate on both sides below the gate electrode are opposite in conductivity type to the first conductivity type impurity. 2. A source region and a drain region of a field effect transistor doped with a conductivity type impurity, and element isolation formed on a semiconductor substrate around the element formation region to separate the element formation region from other regions, and a semiconductor. A channel stop region formed in the substrate below the element isolation and doped with a first conductivity type impurity, and a region in the semiconductor substrate to which at least a high voltage is applied and the channel stop region. A first conductive type impurity or a second conductive type impurity doped with a concentration for controlling a threshold value;
Below the buffer region and the gate electrode in the semiconductor substrate,
In addition, a second buffer region formed in a region adjacent to the element isolation and doped with a first conductivity type or second conductivity type impurity at a concentration for controlling the threshold value is provided.

According to a second aspect of the present invention, in the first aspect of the present invention, the first buffer region is formed of both the drain region and the source region in a semiconductor substrate and the channel stop region. It is provided between them.

According to a third aspect of the present invention, in the above first aspect of the invention, the semiconductor device has a booster circuit. A source region or a drain region formed separately from the channel stop region by the first buffer region of the field effect transistor is connected to the high potential portion of the booster circuit.

The means taken by the invention of claim 4 is premised on a semiconductor device in which a field effect transistor is mounted in an element formation region of a semiconductor substrate doped with a first conductivity type impurity. And a gate electrode of the field effect transistor formed on the semiconductor substrate, sidewalls provided on both side walls of the gate electrode, and a region in the semiconductor substrate below the sidewall. A low-concentration source region and a low-concentration drain region of a field-effect transistor in which a second-conductivity-type impurity having a conductivity type opposite to that of the first-conductivity-type impurity is lightly doped, and the low-concentration source region in a semiconductor substrate. And a high-concentration source region and a high-concentration drain region of a field-effect transistor formed in a region outside and adjacent to the low-concentration drain region and doped with a relatively high-concentration second conductivity type impurity, and the above element formation. Element isolation formed on the semiconductor substrate around the region to separate the element formation region from other regions, and below the element isolation in the semiconductor substrate. Between the channel stop region formed and doped with the first conductivity type impurity and at least the high-concentration drain region and the high-concentration source region in the semiconductor substrate to which a high voltage is applied and the channel stop region. Adjacent to the first isolation region, which is formed and doped with impurities of the second conductivity type at substantially the same concentration as the low-concentration source region and the low-concentration drain region, below the gate electrode in the semiconductor substrate and above the element isolation. A second buffer region formed in the region and doped with a first conductivity type impurity or a second conductivity type impurity at a concentration for controlling the threshold value is provided.

According to a fifth aspect of the invention, in the invention of the fourth aspect, the first buffer region is formed in the semiconductor substrate, both the high concentration source region and the high concentration drain region, and the channel. It is provided between the stop area.

According to a sixth aspect of the invention, in the invention of the fourth aspect, the semiconductor device has a booster circuit. A high-concentration source region or a high-concentration drain region formed separately from the channel stop region of the field-effect transistor is connected to the high-potential portion of the booster circuit.

According to a seventh aspect of the invention, in the invention of the first, second, fourth or fifth aspect, the source is provided below the element forming region of the semiconductor substrate, continuously with the channel stop region, and with the source. A punch-through stop region is provided, which is formed apart from at least a region to which a high voltage is applied, of the region and the drain region, and is doped with a first conductivity type impurity having a concentration substantially the same as the concentration of the channel stop region.

According to another aspect of the present invention, there is provided a field effect transistor which is formed in a device forming region of a semiconductor substrate doped with a first conductivity type impurity and which includes a gate electrode, a source region and a drain region. An object is a method of manufacturing a semiconductor device having element isolation for isolating the element formation region from other regions. Then, a step of doping an impurity for forming a channel stop into a region of the semiconductor substrate where the element isolation is to be formed, and forming an insulating film for the element isolation in a region of the semiconductor substrate where the element isolation is to be formed. And a step of doping the element forming region with a first conductivity type or second conductivity type impurity at a concentration for threshold control, and forming a gate electrode of the field effect transistor on the element forming region. Steps, and a region of the element formation region on the side of the gate electrode is doped with a second conductivity type impurity having a conductivity type opposite to that of the first conductivity type impurity to form a source region and a drain region of the field effect transistor. And a step of forming the drain region and the source region, in which at least a region to which a high voltage is applied is isolated from the drain region and the source region. A method of performing away from the channel stop region enters the predetermined distance element forming region side from the end portion.

According to a ninth aspect of the present invention, in the manufacturing method of the eighth aspect, the semiconductor device includes an n-channel field effect transistor and a p-channel field effect transistor. Then, the step of forming the source region and the drain region is performed so that, in the element formation region of the n-channel field effect transistor, at least a region to which a high voltage is applied among the drain region and the source region is separated from the channel stop region. On the other hand, in the element formation region of the p-channel field effect transistor, both the drain region and the source region are overlapped with the channel stop region.

According to a tenth aspect of the present invention, in the manufacturing method according to the eighth aspect, the semiconductor device includes an n-channel field effect transistor and a p-channel field effect transistor. Then, the step of forming the source region and the drain region is performed in the device forming regions of both the n-channel field effect transistor and the p-channel field effect transistor, in which at least a high voltage is applied to the drain region and the source region. This is a method of moving away from the channel stop region.

According to the invention of claim 11, in the manufacturing method of claim 8, 9 or 10, the step of forming the drain region and the source region is the source region or the drain region separated from the channel stop region. Then, a method is performed in which impurity ions are diffused after implanting impurity ions using a photoresist mask and a gate electrode, which are inwardly opened from a position that is located at a predetermined distance from the element isolation region, as a mask. Is.

According to a twelfth aspect of the present invention, means is provided in the method for manufacturing a semiconductor according to the eighth, ninth or tenth aspect.
After forming the drain region and the source region, in the source region or the drain region apart from the channel stop region, after forming an electrode made of a conductive material doped with the impurity on the region doped with the impurity The method is performed by heating to diffuse the impurity ions from the electrode into the semiconductor substrate.

According to a thirteenth aspect of the present invention, means is formed in an element forming region of a semiconductor substrate doped with a first conductivity type impurity, and includes a gate electrode, a low concentration source region, a low concentration drain region, and a high concentration source. A method for manufacturing a semiconductor device having a field effect transistor including a region and a high-concentration drain region, and element isolation for isolating the element formation region from other regions. Then, a step of doping an impurity for forming a channel stop into a region for forming the element isolation of the semiconductor substrate, and a step of forming an insulating film to be an element isolation in a region for forming the element isolation on the semiconductor substrate, A step of doping a first conductivity type or a second conductivity type impurity at a concentration for threshold control into the element formation region; a step of forming a gate electrode of the field effect transistor on the element formation region; A step of doping a region of the element forming region on the side of the gate electrode with a second conductivity type impurity having a conductivity type opposite to the first conductivity type at a low concentration, and sidewalls on both sides of the gate electrode of the field effect transistor. And forming the sidewall of the gate electrode, and then doping the second conductivity type impurity in a high concentration in a region on the side wall of the element formation region to a high concentration. A step of forming a source region and a high-concentration drain region, and the step of forming the high-concentration source region and the high-concentration drain region is performed by applying at least a high voltage to the high-concentration drain region and the high-concentration source region. This is a method in which the region is moved into the element formation region side by a predetermined distance from the end of the element isolation and is separated from the channel stop region.

According to a fourteenth aspect of the present invention, in the manufacturing method according to the thirteenth aspect, the semiconductor device includes an n-channel field effect transistor and a p-channel field effect transistor. Then, the step of forming the high-concentration source region and the high-concentration drain region is performed in the element forming region of the n-channel field effect transistor, in which at least the high-voltage drain region and the high-concentration source region are applied. In the device formation region of the p-channel field-effect transistor, both the high-concentration drain region and the high-concentration source region are overlapped with the channel stop region while being separated from the channel stop region.

According to a fifteenth aspect of the present invention, in the manufacturing method according to the thirteenth aspect, the semiconductor device includes an n-channel field effect transistor and a p-channel field effect transistor. Then, the step of forming the high-concentration source region and the high-concentration drain region is performed by using the high-concentration drain region and the high-concentration source region in the element formation regions of both the n-channel field effect transistor and the p-channel field effect transistor. In this method, at least the region to which a high voltage is applied is separated from the channel stop region.

According to a sixteenth aspect of the present invention, in the manufacturing method according to the thirteenth, fourteenth or fifteenth aspect, the step of forming the high-concentration drain region and the high-concentration source region is performed at a high level apart from the channel stop region. In the concentrated source region or the high-concentration drain region, after implanting impurity ions using a photoresist mask and a gate electrode, which are opened inward from a position that is a predetermined distance from the device isolation, as a mask, This is a method performed by diffusing ions.

According to a seventeenth aspect of the present invention, in the manufacturing method of the thirteenth, fourteenth or fifteenth aspect, the step of forming the high-concentration drain region and the high-concentration source region is performed at a high level apart from the channel stop region. In the high concentration source region or the high concentration drain region, an electrode made of a conductive material doped with the impurity is formed on the region doped with the impurity, and then heated to diffuse the impurity ions from the electrode into the semiconductor substrate. It is a method of performing by doing.

The measures taken by the invention of claim 18 are the means of claim 8, 9, 10, 11, 12, 13, 14, 15, 1.
In the manufacturing method of 6 or 17, the step of doping impurities for forming the channel stop region is performed by implanting impurity ions with high energy from above the element formation region and the element isolation region after the element isolation formation step, and at the same time, In this method, the impurity ions are also implanted below the element formation region of the semiconductor substrate as impurities for forming the punch through stop region.

[0035]

With the above construction, in the invention of claim 1, in the field effect transistor, the first buffer region doped with the impurity for controlling the threshold provides a predetermined distance between the source region or the drain region and the channel stop region. Since there is a space, even if the impurity concentration in the channel stop region is increased, the expansion of the depletion layer at the boundary between the source region or the drain region and the channel stop region is secured, and good breakdown voltage characteristics can be obtained. Therefore, in a field-effect transistor having a fine dimension, it is possible to increase the impurity concentration in the channel stop region and ensure the isolation characteristic in element isolation while ensuring good breakdown voltage characteristics of the source region and the drain region. Become. In addition, the region below the gate electrode and adjacent to the element isolation is
Since the second buffer region is doped with the threshold control impurity at an appropriate concentration, an inversion layer is not generated due to the reduction of the impurity concentration, and the generation of a leak current between the source and the drain is prevented. Moreover, in such a configuration, the number of steps in manufacturing does not increase as compared with a general semiconductor device, and the dimension of the gate electrode portion is determined by self-alignment, so that alignment is not difficult.

According to the second aspect of the present invention, even in a semiconductor device including a field effect transistor in which a high voltage is applied to both the drain region and the source region, the withstand voltage characteristic of the source region and the drain region and the isolation characteristic of element isolation. , The source-drain leakage current prevention function is well maintained.

According to the third aspect of the invention, in the booster circuit of the semiconductor device, the source region or the drain region of the field effect transistor connected to the high potential portion is formed apart from the channel stop region. The operation of the booster circuit is ensured without damaging the drain region.

According to a fourth aspect of the present invention, in a field effect transistor having a so-called LDD structure, the low-concentration source region and the low-concentration drain region are located at the boundary between the high-concentration source region, the high-concentration drain region and the channel stop region. Since it exists as one buffer region, the expansion of the depletion layer at the boundary can be ensured and good element isolation characteristics can be obtained as in the case of the first aspect of the invention. Therefore, in addition to the effect of the invention of claim 1, excellent device characteristics due to the LDD structure can be obtained.

According to the fifth aspect of the present invention, the first buffer region is formed between both the high concentration source region and the high concentration drain region and the channel stop region, so that the high concentration source region and the high concentration drain are formed. The effect of the invention of claim 4 can be obtained also in a semiconductor device including a field effect transistor to which a high voltage is applied to both regions.

According to the sixth aspect of the invention, in the booster circuit of the semiconductor device, the high-concentration source region or the high-concentration drain region of the field effect transistor having the LDD structure connected to the high potential portion is formed separately from the channel stop region. Therefore, the operation of the booster circuit is ensured without causing damage to the source region or the drain region.

In the invention of claim 7, since the punch through stop region is formed continuously with the channel stop region, the above-mentioned characteristic improving action by the source region and the drain region apart from the channel stop region and the punch through stop are provided. The effect of preventing malfunction of the field effect transistor due to the region can be obtained.

According to the invention of claim 8, after the element isolation surrounding the element formation region of the field effect transistor and the channel stop region therebelow are formed, the first conductivity type for threshold control is formed in the entire element formation region. Alternatively, the second conductivity type impurity is doped. Then, after that, the gate electrode, the source region and the drain region are formed. Then, at least a region to which a high voltage is applied among the source region and the drain region is formed apart from the channel stop region by entering the element formation region side by a predetermined distance from the element isolation,
Between this source region or drain region and element isolation,
The threshold control impurity is doped and serves as the first buffer region in the first aspect of the invention. Further, a region under the gate electrode and adjacent to the element isolation is doped with a threshold controlling impurity to serve as a second buffer region in the invention of claim 1.
The number of steps in this manufacturing process is the same as that in the manufacturing process of a general semiconductor device having a field effect transistor. In addition, the pattern shape of the mask used when forming the source region or the drain region is different only in the portion facing the element isolation, and the gate electrode portion is formed in a self-aligned manner, which causes alignment difficulty. Absent. Therefore, the semiconductor device having the action of the invention of claim 1 can be easily and inexpensively manufactured.

In the invention of claim 9, the source region or the drain region is formed separately from the channel stop region only in the n-channel field effect transistor in which an inversion layer is likely to occur at the boundary between the source region or the drain region and the channel stop region. Therefore, the manufacturing is relatively easy as compared with the manufacturing method in which all the transistors are formed to have this structure.

In the tenth aspect of the invention, the source region or the drain region is formed separately from the channel stop region for both the n-channel field effect transistor and the p-channel field effect transistor, so that the p-channel field effect transistor is formed. In this case, the withstand voltage characteristic is maintained more reliably.

According to the eleventh aspect of the present invention, since the semiconductor device is manufactured only by changing the pattern of the photoresist mask used for manufacturing the conventional semiconductor device, an increase in manufacturing cost can be suppressed. .

According to the twelfth aspect of the invention, since the source region or the drain region having a structure separated from the channel stop region is formed by diffusing the impurity ions from the electrode on the silicon substrate, the impurity doping depth is shallow. Becomes
The occurrence of punch through will be suppressed.

In a thirteenth aspect of the present invention, in a semiconductor device having a field effect transistor having a so-called LDD structure, at least a high-concentration source region and a high-concentration drain region to which a high voltage is applied are predetermined from element isolation. It is formed to enter the element formation region side by a distance and be separated from the channel stop region. Then, between the high-concentration source region or the high-concentration drain region and the element isolation, an impurity having a conductivity type opposite to that of the semiconductor substrate is doped at a low concentration to form a first buffer region in the invention of claim 4.
In addition, the region below the gate electrode and adjacent to the element isolation is
The second buffer region in the invention of claim 4 is doped with the threshold controlling impurity. The number of steps in this manufacturing process is the same as that in the manufacturing process of a semiconductor device having a field effect transistor having a general LDD structure. In addition, the pattern shape of the mask used when forming the source region or the drain region is different only in the portion facing the element isolation, and the gate electrode portion is formed in a self-aligned manner, which causes alignment difficulty. Absent.
Therefore, the semiconductor device having the action of the invention of claim 4 can be easily and inexpensively manufactured.

In the fourteenth aspect of the present invention, the high concentration source region or the high concentration source region or the high concentration source region or the high concentration source region is formed only in the n-channel field effect transistor of the LDD structure in which an inversion layer is likely to occur at the boundary between the high concentration source region or the high concentration drain region and the channel stop region. Since the concentration drain region is formed apart from the channel stop region, manufacturing is relatively easy as compared with the manufacturing method in which all transistors are formed to have this structure.

According to the fifteenth aspect of the invention, the high-concentration source region or the high-concentration drain region is formed apart from the channel stop region in both the n-channel field effect transistor and the p-channel field effect transistor having the LDD structure. Therefore, the semiconductor device having the effect of the invention of claim 4 can be manufactured more reliably.

According to the sixteenth aspect of the invention, the semiconductor device is manufactured only by changing the pattern of the photoresist mask used for manufacturing the semiconductor device having the field effect transistor of the conventional LDD structure. Will be suppressed.

In the seventeenth aspect of the invention, since the high concentration source region or the high concentration drain region having a structure separated from the channel stop region is formed by diffusion of impurity ions from the electrode on the silicon substrate, the impurity doping is performed. The region and dope concentration can be controlled more accurately.

According to the eighteenth aspect of the present invention, since the punch through stop region and the channel stop region are formed at the same time, the number of steps can be reduced and the manufacturing cost can be reduced.

[0053]

EXAMPLES Examples of the present invention will be described below.

Example 1 First, Example 1 will be described with reference to FIGS. 1 (a) to 1 (d) and 2 (a) to 2 (e).

FIGS. 1A to 1D show C according to the first embodiment.
1A shows a structure of a MOSFET, FIG. 1A is a plan view, and FIG.
(B)-(d) is an Ib-Ib line sectional view, an Ic-Ic line sectional view, and an Id-Id line sectional view, respectively. This semiconductor device includes an n-channel MOSFET 1 and a p-channel MOSF.
ET2 (both surface channel MOSFETs) are provided. Here, on the upper part of the silicon substrate 10,
In the element formation region Rnfet where the n-channel MOSFET 1 is to be formed, the P-well 10a is connected to the p-channel MOSF.
N wells 10b are formed in the element formation regions Rpfet where the ET2 is to be formed. A gate insulating film 18 made of a silicon oxide film is provided on each well 10a, 10b, and a gate electrode made of a two-layer film of a polysilicon film and a silicon oxide film is further provided on the gate insulating film 18. 12 is provided, and impurities for VT control (here, impurities of the same conductivity type as the impurities of each well) are provided in the silicon substrate 10 (well) below the gate electrode 12.
A gate region 17 doped with is formed. That is, in the gate region 17, an n-channel MOSFE
Boron, which is a p-type impurity, is a p-channel MOS in T1.
In FET2, phosphorus, which is an n-type impurity, is doped at a relatively low concentration. However, in a p-channel MOSFET that is not a surface channel type, boron that is a p-type impurity may be implanted. Further, on both end sides of the gate region 17, an impurity of a conductivity type opposite to that of each well, that is, an n-channel M
Source region 1 heavily doped with arsenic in OSFET 1 and boron in p-channel MOSFET 2, respectively.
5 and the drain region 16 are provided.

On the other hand, around the element forming regions Rnfet and Rpfet of the MOSFETs 1 and 2, an element isolation 11 made of LOCOS for electrically insulating and isolating these regions from other regions is provided. In order to ensure the element isolation characteristics, a channel stop region 13a doped with an impurity having a conductivity type opposite to that of the source and drain impurities, that is, the same conductivity type as each well is provided in a region immediately below the element isolation 11. .

The characteristic part of the present invention will now be described. In the nMOSFET 1, the source region 15 and the drain region 16 are both formed in a region inside a predetermined distance or more from the end of the element isolation 11 and apart from the channel stop region 13a without contacting them.
In other words, the gate region 1 is provided between the source region 15 and the drain region 16 and the channel stop region 13a.
There is provided a first buffer region 24 which has the same conductivity type as that of No. 7 and is doped with an impurity (VT controlling impurity) having substantially the same concentration. Further, the region (second buffer region 25) below the gate electrode 12 and adjacent to the element isolation 11 is also doped with impurities of the same conductivity type and the same concentration. The impurity concentration near the surface of each buffer region 24, 25 is 10
It is about ¹⁶ to 10 ¹⁷ cm ^-3 .

On the other hand, in the pMOSFET 2 described above,
Both the source region 15 and the drain region 16 are formed to the end of the element isolation 11, that is, to overlap the channel stop 13a, and there is no buffer region.

Next, the manufacturing process of the semiconductor device according to the first embodiment will be described with reference to FIGS. 2A to 2E, the left side is an n channel M.
Cross section of OSFET1, right side is p-channel MOSFET
2 shows a sectional structure of No. 2.

First, as shown in FIG. 2A, the P well 10a and the N well 10b are formed on the surface of the silicon substrate 10.
And a silicon nitride film 31 having a pattern in which a region 31a where an element isolation is to be formed is formed, and then a photoresist mask 32a covering the element formation region Rpfet of the p-channel MOSFET 2 is formed.
To create. Then, in the element formation region Rnfet and the contact formation region Rcont of the n-channel MOSFET 1, boron (B) which is a p-type impurity for forming a channel stop region is formed in the opening 31a of the silicon nitride film 31 from above the photoresist mask 32a. ) Is injected. Although not shown, phosphorus (P), which is an n-type impurity for forming a channel stop region, is similarly implanted into the p-channel MOSFET 2.

Next, as shown in FIG. 2B, the silicon in the opening 31a of the silicon nitride film 31 is thermally oxidized to obtain L
An element isolation 11 made of OCOS is formed. At this time,
Impurities that have already been injected diffuse with the high temperature treatment,
A channel stop region 13a is formed over the entire area below the element isolation 11.

Next, as shown in FIG. 2C, after removing the silicon nitride film 31, a new silicon oxide film 33 is formed and a photoresist mask 32b covering the p-channel MOSFET 2 side is formed. N channel M from above
Boron (B) which is an impurity for controlling VT of the OSFET 1 is implanted. At this time, the acceleration energy is 20 to 50 KeV.
As a result, the impurity concentration near the surface of each buffer region 24, 25 is set to about 10 ¹⁶ to 10 ¹⁷ cm ⁻³ . And
Although not shown, phosphorus (P), which is an impurity for controlling VT, is also implanted in the region where the p-channel MOSFET 2 is formed.

Next, as shown in FIG. 2D, a photoresist mask 32c is formed in which the source / drain regions of the n-channel MOSFET 1 and the contact formation region Rcont of the p-channel MOSFET 2 are opened.
Arsenic (As), which is a type impurity, is implanted at a high concentration. At this time, on the n-channel MOSFET 1 side, the photoresist mask 32c is formed so as to cover a portion that has entered the inside of the element formation region Rnfet by a predetermined distance from the end of the element isolation 11. As a result, the source region 15
Both the drain region 16 and the drain region 16 are formed apart from the channel stop region 13a. In this implantation step, the gate electrode 12 also functions as a mask, and the source region 15 and the drain region 16 are patterned by self-alignment in this portion.

Next, as shown in FIG. 2E, a photoresist mask 32d is formed in which the source / drain formation region of the p-channel MOSFET 2 and the contact formation region Rcont of the n-channel MOSFET 1 are opened. Boron (B), which is an impurity, is implanted at a high concentration.

Therefore, in the first embodiment, in the n-channel MOSFET 1, the drain region 16 is formed apart from the channel stop region 13a below the element isolation 11. That is, the first buffer region 24 in which an appropriately low concentration VT control impurity (boron (B)) is implanted between the channel stop region 13a and the drain region 16.
Therefore, even if the concentration of the impurity (boron (B)) in the channel stop region 13a is increased to about 1 × 10 ¹⁷ cm ⁻³ or more, it is possible to secure the expansion of the depletion layer. Therefore, the breakdown voltage at the P-N junction can be secured.

That is, in an element requiring miniaturization of the memory region or the like, generation of the inversion layer cannot be effectively prevented unless the impurity concentration of the channel stop region 13a is increased. On the other hand, in the element where the high voltage is applied to the source region 15 or the drain region 16, the channel stop region 13
When the impurity concentration of a is increased, the expansion of the depletion layer is suppressed and the breakdown voltage characteristic deteriorates. However, if it is attempted to change the impurity concentration between the element such as the memory area and the element in the high voltage application side area, a separate mask pattern is required and the number of steps is increased. However, in the above-described first embodiment, the channel stop region 1 is formed by the device such as the memory region and the device in the high voltage application side region.
Since the impurity concentration in 3a is the same, the number of steps does not increase.

That is, the impurity concentration in the channel stop region 13a of the element on the side where the fine pattern is required is increased to prevent the generation of the inversion layer in the channel stop region and to secure good element isolation characteristics while maintaining high voltage. It is possible to prevent the breakdown voltage characteristic from deteriorating in the element to which is applied. The buffer area 2 as in the first embodiment
Although the width of the source region 15 or the drain region 16 may be widened by providing Nos. 4 and 25, since a transistor to which a high voltage is normally applied does not require a relatively fine structure, no problem occurs.

Moreover, the above-mentioned conventional technique (see FIGS. 14 and 15)
The structure shown in FIG.
The first buffer region 24 for separating the drain region 16 from the drain region 16 is provided inside the element formation region Rnfet with respect to the end of the element isolation 11, and the second buffer region 25 below the gate electrode 12 and not included in the gate region 17. (Hatched part in Figure 1)
Since the VT control impurity (boron (B)) is appropriately doped, the impurity concentration in the overlap region 21 is too low as shown in the structure of FIG. No leak current is generated.

Further, in the structure shown in FIG. 15, the overlap region 21 needs to be divided into a part 23 adjacent to the drain region and a part 22 adjacent to the source region. It requires more steps than the method, and when the width of the gate electrode is narrow, alignment of the mask becomes difficult. On the other hand, in the above-described embodiment, the same number of steps as in the normal method shown in FIGS. Further, since the drain region 16 is formed by self-alignment at the end of the gate electrode 12,
There is no need to align the mask at the gate electrode 12 portion, and the difficulty in alignment can be avoided.

In the first embodiment, the source region 15
Although both the drain region 16 and the drain region 16 have a structure in which the buffer region 24 is provided apart from the channel stop region 13a, the present invention is not limited to this embodiment. That is, in a normal semiconductor device, since a high voltage is applied only to the drain region 16, it is sufficient that at least the region to which the high voltage is applied is separated from the channel stop region 13a. However, the source area 15
Also between the channel stop region 13a and the buffer region 24
By providing the structure, there is an advantage that the above effect can be effectively exhibited even in a device in which a high voltage is applied to the source region 15, such as a transfer gate.

In the first embodiment, the p channel MO
Although no buffer region is provided on the SFET2 side, a channel stop region 13a is provided on the p-channel MOSFET 2.
Since phosphorus (P) is the impurity implanted into the semiconductor, unlike boron (B), which is relatively easily diffused and easily absorbed by the field oxide film, there is little risk of forming a P—N inversion layer, and under normal conditions. Almost no problem. However, by providing the buffer region also in the p-channel MOSFET 2, the breakdown voltage characteristic can be more reliably maintained.

In the first embodiment described above, the case where the source and drain have a normal so-called SD structure has been described. However, the invention of claim 1 is not limited to this embodiment, and a DD structure or an LDD structure can be used. The source region or the drain region as a whole is separated from the channel stop region. In Example 2 below, an LDD type FET having such a configuration will be described.

(Embodiment 2) Next, Embodiment 2 will be described with reference to FIGS.

FIG. 3 shows the structure of the CMOSFET according to the second embodiment. The description of the parts having the same structures as those of the first embodiment will be omitted, and only different parts will be described. In this embodiment, a sidewall 19 is provided on the side of the gate electrode 12, and below the sidewall 19,
Low-concentration impurities, that is, phosphorus (P) is doped in the n-channel MOSFET 1 and boron (B) is doped in the p-channel MOSFET 2 to form the low-concentration source region 15b and the low-concentration drain region 16b. Impurities, that is, arsenic (As) in the n-channel MOSFET 1 and boron (B) in the p-channel MOSFET 2 are highly doped, so that the high-concentration source region 15a is formed.
And the high-concentration drain region 16a is formed. In the n-channel MOSFET 1, the high-concentration source region 15a, the high-concentration drain region 16a, and the channel stop region 13a are separated from each other, and a VT control impurity, that is, a buffer region 24 doped with boron (B) is provided therebetween. Is provided. However, p-channel MOSFE
At T2, both the high concentration source region 15a and the high concentration drain region 16a are formed so as to be continuous with the channel stop region 13a. At this time, the impurity concentration near the surface of the low concentration source region 15b and the low concentration drain region 16b is 10 ¹⁸ to 10 ¹⁹ cm ⁻³ , and the impurity concentration near the surface of the high concentration source region 15a and the high concentration drain region 16a. Is about 10 ²⁰ cm ^-3 .

FIGS. 4A to 4C show C according to the second embodiment.
A MOSFET manufacturing process is shown, and the process of forming the element isolation 11 and the channel stop region 13a is performed similarly to FIGS. 2A and 2B in the first embodiment, but the part is omitted.

As shown in FIG. 4A, a photoresist mask 32b in which only the region for forming the n-channel MOSFET 1 is opened on the substrate on which the element isolation 11 and the channel stop region 13a are formed (the above-mentioned embodiment). 1 has the same shape as the photoresist mask 32b of FIG. 2 (c))
Then, boron (B), which is an impurity for controlling VT, is implanted at a low concentration from above. Also, p-channel MOSF
Phosphorus (P), which is a VT control impurity, is similarly implanted into ET2.

Next, as shown in FIG. 4B, a photoresist mask 32c having the same shape as that of FIG. 2D in the first embodiment is formed, and then impurity phosphorus (P) is implanted. As a result, the low concentration source region 15b and the low concentration drain region 16b are formed in the source and drain forming regions of the n-channel MOSFET 1. At this time,
The acceleration energy for implanting impurity ions is 20 to 5
The impurity concentration near the surface of the low-concentration source region 15b and the low-concentration drain region 16b is 10 ¹⁸ to
It is set to about 10 ¹⁹ cm ^-3 . Although not shown,
Also in the p-channel MOSFET 2, the low concentration source region 15
b and the lightly doped drain region 16b are formed. However,
At this time, in the n-channel MOSFET 1, the low-concentration source region 15b and the low-concentration drain region 16b are formed separately from the channel stop region 13b, and the buffer region 24 doped with the VT control impurity is provided between them. However, such a buffer region does not exist in the p-channel MOSFET 2.

Next, as shown in FIG. 4C, the photoresist mask 32c is once removed, and then the sidewall 1 made of a silicon oxide film is formed on the side of the gate electrode 12.
9 is formed, and a photoresist mask 32e having the same shape as the photoresist mask 32c shown in FIG. 4B is formed again.
Is formed, and arsenic (As), which is an n-type impurity having a high effective concentration, is implanted from above. Thus, in the n-channel MOSFET 1, the low-concentration source region 15b and the low-concentration drain region 16b are formed adjacent to both ends of the gate region 17, and the high-concentration source region 15a and the high-concentration drain region 16a are formed outside thereof. Has been formed. That is, it has a so-called LDD structure. At this time, the acceleration energy for implanting arsenic (As) ions is set to 20 to 50 KeV, and the impurity concentration in the vicinity of the surfaces of the high concentration source region 15a and the high concentration drain region 16a is set to about 10 ²⁰ cm ^-3 . In this case, the high-concentration source region 15a and the high-concentration drain region 16a of the n-channel MOSFET 1 and the channel stop region 13a are also included.
Between the buffer region 2 in which the VT control impurity is implanted.
4 are provided.

Although the high-concentration source and drain regions of the p-channel MOSFET 2 are formed through the process of FIG. 4C, at that time, the high-concentration source region 15a, the high-concentration drain region 16a, and the channel stop region 1 are formed.
There is no buffer area between 3a and 3a and both are formed continuously.

Therefore, in the second embodiment, since the high-concentration source region 15a and the high-concentration drain region 16a are formed apart from the channel stop region 13a, the same effect as in the first embodiment can be obtained. In particular, L
Since it has a DD structure, it can exhibit a remarkable effect in that the hot carrier effect can be prevented even if the channel length is shortened and the channel length is shortened.

However, as in the first embodiment, it is sufficient if one of the high-concentration source region 15a and the high-concentration drain region 16a to which a high voltage is applied is separated from the channel stop region 13a. Also, p-channel MOS
The FET 2 may have the same structure as the n-channel MOSFET 1.

Although the source / drain structure is the LDD structure in the second embodiment, the structure of the second embodiment is also provided in the so-called DD structure if the thin region is separated from the channel stop region. Basically, the configuration is similar. In that case, in the manufacturing process, phosphorus (P) and arsenic (As) having different diffusion coefficients are implanted using the same photoresist mask 32c in the state shown in FIG. By heating and diffusing, a relatively high density portion and a relatively low density portion can be formed.

(Third Embodiment) Next, a third embodiment will be described with reference to FIGS.

FIG. 5 shows the structure of a CMOFET according to the third embodiment, which is basically the same as the structure shown in FIG. 3 of the second embodiment. However, in the third embodiment, the high concentration source region 15a and the high concentration drain region 16a are formed.
And the region between the channel stop region 13a and VT
Low-concentration source region 1 in which not only control impurities but also impurities of a conductivity type opposite to that of silicon substrate 10 are lightly doped
5b and the low concentration drain region 16b. That is, the low concentration source region 15b and the low concentration drain region 16b function as the first buffer region. The second buffer region 25 is a region directly below the gate electrode 12 and lateral to both ends of the gate region 17, that is, adjacent to the element isolation 11, as in the case of the first embodiment.

FIGS. 6A to 6C show C according to the third embodiment.
6A shows the manufacturing process of the MOSFET, and the process shown in FIG. 6A is the same as the process shown in FIG. 4A in the second embodiment.

Next, as shown in FIG. 6B, a photoresist mask 32f is formed, and an n-channel M is formed on the photoresist mask 32f.
Phosphorus (P) is formed in the source and drain forming regions of OSFET1.
Is implanted to form a low concentration source region 15b and a low concentration drain region 16b. At this time, unlike the step of FIG. 4B in the second embodiment, the photoresist mask 32f opened to the end of the element isolation 11 is used, and the low concentration source region 15b and the low concentration drain region 1 are used.
Both 6b are formed in a region continuous with the channel stop region 13a. After that, although not shown, the p channel M
Similar low concentration source and drain regions are formed in the OSFET2.

After removing the photoresist mask 32f, the sidewalls 1 are formed on the sides of each gate electrode 12.
9 is formed. Then, as shown in FIG. 6C, a photoresist mask 32e having the same pattern as that used in the step of FIG. 4C in the second embodiment is formed again, and an n-type impurity having a high effective concentration is formed thereon. Arsenic (As) is implanted to form the high concentration source region 15a and the high drain region 16a. At this time, since the photoresist mask 32e has a shape that covers a portion that has entered the inside of the element forming region Rnfet by a predetermined distance from the end of the element isolation 11, the high concentration source region 15a and the high concentration drain region 16a. Both of them have a structure separated from the channel stop region 13a.

In the third embodiment, the low concentration source region 15b is used.
The low concentration drain region 16b is continuous with the channel stop region 13a, but the high concentration source region 15a and the high concentration drain region 16a are connected to the channel stop region 13a.
Since the structure is separated from a, the breakdown voltage characteristic can be maintained well even if the impurity concentration of the channel stop region 13a is relatively high.

In this case, the high concentration source region 15 is not always necessary.
Neither a nor the high-concentration drain region 16a needs to be separated from the channel stop region 13a, and p
Also in the channel MOSFET 2, the n-channel MOS
Similar to the first embodiment, the FET 1 may have the same structure.

Although the source / drain structure is the LDD structure in the third embodiment, when the so-called DD structure is used, even if the drain region having a relatively low concentration overlaps with the channel stop region. If the high-concentration portion is separated from the channel stop region, the LDD
The same effect as in the case of the structure can be exhibited.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIG.

FIGS. 7A to 7D show steps when the present invention is applied to a method of forming a high concentration source / drain region using a diffusion source.

First, as shown in FIG. 7A, the P-well 10a, the N-well 10b, the element isolation 11, and the channel stop 13a are formed in the same manner as in the first to third embodiments, and the element formation region is formed. Impurities for controlling VT are implanted into Rnfet and Rpfet.

Next, as shown in FIG. 7B, the low concentration source region 15b and the low concentration drain region 16b are formed through the same process as the process of FIG. 6B in the third embodiment. The formation of the sidewall 19 is completed.
The oxide film other than directly under the gate electrode 12 is removed.

Next, as shown in FIG. 7C, after a polysilicon film 34 to be an electrode is formed on the entire surface of the substrate, a polysilicon film on a region to be doped with an n-type impurity is formed. Arsenic (As) and boron (B) are implanted into the polysilicon above the region where p-type impurities are to be doped.

Next, as shown in FIG. 7D, after the polysilicon film is patterned to form a polysilicon electrode, the polysilicon film is maintained at a predetermined high temperature and arsenic (arsenic) which is an impurity from each polysilicon electrode ( As) or boron (B) is diffused in the silicon substrate 10 to form the high-concentration source region 15a and the high-concentration drain region 16a of each MOSFET 1, 2. At this time, on the n-channel MOSFET 1 side, both ends of the source electrode 34a and the drain electrode 34b are patterned so as to be inside the element formation region Rnfet by a predetermined distance from the element isolation 11. That is, both the high-concentration source region 15a and the high-concentration drain region 16a to be formed are formed apart from the channel stop region 13a.

Therefore, also in the fourth embodiment, the same structure as that shown in FIG. 5 in the third embodiment can be obtained. In that case, in such a manufacturing process, there is an advantage that the doping depth of impurities can be made shallow and punch-through is suppressed.

(Fifth Embodiment) Next, a fifth embodiment in which a channel stop region and a punch through stop region are simultaneously formed will be described with reference to FIG.

First of all. As shown in FIG. 8A, a silicon nitride film 31 is deposited on the silicon substrate 10 and then patterned, and the silicon in the opening 31a is thermally oxidized,
A LOCOS element isolation 11 is formed.

Next, as shown in FIG. 8B, impurity ions are implanted into the channel stop region 13a and the punch through stop region 13b from above with a relatively high energy to a depth of several 100 nm from the silicon surface. Are formed at the same time. However, the implanted impurities are n-channel MOS.
FET1 is boron (B) and p-channel MOSF
It is phosphorus (P) in ET2.

Next, as shown in FIG. 8C, VT control impurities are implanted, and further, as shown in FIG.
After forming the gate electrode 12, a source region 15 and a drain region 16 are formed by implanting a high concentration impurity. The steps shown in FIGS. 8C and 8D are basically the same as the steps shown in FIGS. 2C and 2D in the first embodiment. At that time, both the source region 15 and the drain region 16 are separated from the element isolation 11 by a predetermined distance.
It is located inside the nfet and is separated from the channel stop region 13a. Further, the source region 15
In this embodiment, the drain region 16 and the drain region 16 are both formed separately from the punch through stop region 13b. (Caution for deletion) FIG. 9A shows the mask 32c in the step of FIG. 8D.
Width x of a region where the end of the element formation region overlaps
N-channel MOSFET prepared by changing (see (b))
The result of having measured the breakdown voltage when a voltage is applied to the drain of No. 1 is shown. In FIG. 9A, ◯, Δ, and □ are the dose amounts of the impurity ions doped in the channel stop region 13a and the punch through stop region 13b, which are 3.0 × 10 ¹² cm ⁻² and 2.5 × 10 ^{12, respectively.} cm ^-2 , 2.0 x
The data at 10 ¹² cm ^-2 is shown, and the acceleration energy of boron (B) is 170 KeV. As shown in FIG. 9A, the overlapping width x between the mask and the element formation region is set to 0.
By setting the thickness to 4 to 0.6 μm, the breakdown voltage characteristics can be improved by 1 to 2V. The impurity ion implantation conditions are sufficient to set the impurity concentration near the surface of the channel stop region 13a to about 1 × 10 ¹⁷ cm ⁻³ .

In the fifth embodiment, the punch-through stop region 13b is used as the source-source while maintaining good withstand voltage characteristics.
The punch-through between the drains can be effectively prevented, and the punch-through stop region 13b is formed simultaneously with the channel stop region 13a, so that the process can be simplified.

In each of the first to fifth embodiments, the transistor is a MOS type FET, but the present invention is not limited to this example, and a general MIS type FET such as a silicon nitride film is used. The present invention is also applied to a FET having a gate insulating film, and a semiconductor device in which a Schottky gate field effect transistor or the like is arranged without providing a gate insulating film.

(Embodiment 6) Next, the MOSFET of the present invention
Example 6 according to an example in which the voltage is arranged in a booster circuit is shown in FIG.
0 and FIG. 11 will be described.

FIG. 10 is a circuit diagram showing the configuration of the booster circuit, and FIGS. 11A to 11E are diagrams showing potential waveforms at terminals I1, I1 ', points A, A', and terminal Out shown in FIG. is there. However, in FIG. 10, Tr1, Tr2, Tr3, Tr
1 ', Tr2', and Tr3 'are transistors, C, and
C'is a capacitor respectively. Here, in each of the transistors Tr1 to Tr3 ′, the source and drain are marked with a circled side apart from the channel stop region.

First, as shown in FIG. 11 (a), when a pulsed voltage signal having a height VDD is applied to the terminal I1 ', the coupling in the capacitor C causes a change in the state shown in FIG. 11 (c). As shown, the potential at point A is raised above the pulse voltage height VDD. At this time, the terminal I
When the gate voltage is applied to 2, the transistor Tr3 is turned on, and this potential is transferred to the terminal Out. Further, since the potential at the point A starts to fall due to the fall of the pulse voltage from the terminal I1, the transistor Tr3 is turned off.

On the other hand, as shown in FIG.
A pulse voltage signal having a phase opposite to that of the terminal I1 is applied to 1 ', and the potential at the point A'is raised to a level higher than the pulse voltage VDD, as shown in FIG.
It is transferred to the terminal Out via r3 '.

That is, the transistor Tr is connected to the terminal Out.
Since a voltage signal equal to or higher than the pulse voltage VDD is alternately transferred from 3, Tr3 ', as shown in FIG.
The potential at is a high potential above VDD.

In the sixth embodiment, the transistor arranged at the portion to which a high voltage of about 10 to 11 V is applied is separated from the channel stop region and the source / drain regions as in the above-mentioned first to fifth embodiments. By using the transistor having the above high withstand voltage structure, the characteristics of the booster circuit can be favorably maintained. However, it suffices if at least the region to which the high voltage is applied among the source region and the drain region is separated from the channel stop region.

In the sixth embodiment, the booster circuit is provided with the transistor having the high breakdown voltage structure as in the first to fifth embodiments. However, the present invention is not limited to this embodiment. Instead, a circuit that generates a high bias can effectively exhibit its function.

[0111]

As described above, according to the invention of claim 1, as a semiconductor device in which a field effect transistor is mounted on a semiconductor substrate, a channel stop region is provided below element isolation, and a drain region of the transistor is provided. A first buffer region doped with an impurity for threshold control is provided between at least a region to which a high voltage is applied and the channel stop region, and further below the gate electrode in the semiconductor substrate, and Since the second buffer region doped with the impurity for controlling the threshold is provided in the region adjacent to the element isolation, in the field effect transistor having a fine dimension, the impurity concentration in the channel stop region is increased and the element isolation is performed. The first buffer region ensures good withstand voltage characteristics of the source and drain regions while ensuring the isolation characteristics in And, the drain by a second buffer region -
It is possible to prevent the generation of leak current between the sources.

According to the invention of claim 2, in the invention of claim 1, the first buffer region is provided between both the drain region and the source region and the channel stop region. Even in a semiconductor device in which a high voltage is applied to the region, it is possible to maintain good withstand voltage characteristics.

According to a third aspect of the invention, in the semiconductor device having the booster circuit according to the first aspect of the invention, it is formed in the high potential portion of the booster circuit, apart from the channel stop region of the field effect transistor. Since the source region or the drain region is connected, the operation of the booster circuit can be ensured without causing damage to the source region or the drain region.

According to the invention of claim 4, so-called LDD
In the field effect transistor having the structure, the low-concentration source region and the low-concentration drain region are present as the first buffer region at the boundary between the high-concentration source region, the high-concentration drain region and the channel stop region.
In addition to the effect of the invention of claim 1, good device characteristics such as relaxation of the short channel effect due to the LDD structure can be obtained, and a semiconductor device more suitable for miniaturization of elements can be provided.

According to the invention of claim 5, in the invention of claim 4, the first buffer region is formed between both the high concentration source region and the high concentration drain region and the channel stop region. Therefore, the effect of the invention of claim 4 can be exerted also in a semiconductor device including a field effect transistor in which a high voltage is applied to both the high concentration source region and the high concentration drain region.

According to the invention of claim 6, in the invention of claim 4, in the case of a semiconductor device having a booster circuit, a high concentration source region of a field effect transistor having an LDD structure connected to a high potential portion or Since the high-concentration drain region is separated from the channel stop region, the operation of the booster circuit can be ensured without damaging the source region or the drain region.

According to the invention of claim 7, the above-mentioned claim 1,
In the invention of 2, 4, or 5, since the punch through stop region is formed continuously with the channel stop region, the above-mentioned characteristic improving effect by the source region and the drain region separated from the channel stop region and the punch through stop are provided. The effect of preventing malfunction of the field effect transistor due to the region can be exhibited together.

According to the invention of claim 8, as a method of manufacturing a semiconductor device having a field effect transistor and element isolation, an element isolation insulating film and a channel stop region are formed, and then an element formation surrounded by element isolation is formed. After the region is doped with a threshold control impurity and a gate electrode is formed, at least a region of the drain region and the source region to which a high voltage is applied enters the element formation region side by a predetermined distance from the end of the element isolation. Since the source formation region and the drain formation region are doped with impurities away from the channel stop region, the same process as the manufacturing process of a general semiconductor device having a field-effect transistor can be performed without causing difficulty in alignment. A semiconductor device having a first buffer region and a second buffer region according to the invention such as claim 1 is formed by the number. Bets can be, therefore, it is possible to achieve a reduction in the ease and the manufacturing cost for manufacturing a semiconductor device having a structure such as a claim 1.

According to the invention of claim 9, in the manufacturing method of claim 8, in a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor mounted, a source / drain-channel stop region is formed. Since the source region or the drain region is formed separately from the channel stop region only in the n-channel field effect transistor in which the inversion layer is likely to occur at the boundary of, the semiconductor device can be manufactured relatively easily.

According to the invention of claim 10, the above-mentioned claim 8 is used.
In the method of manufacturing a semiconductor device having an n-channel field-effect transistor and a p-channel field-effect transistor mounted therein,
Since the source region or the drain region is formed separately from the channel stop region in both of the channel field effect transistors, the breakdown voltage characteristic of the p channel field effect transistor can be more reliably maintained.

According to the eleventh aspect of the invention, in the manufacturing method of the eighth, ninth or tenth aspect, the formation of the source and drain regions is performed from a position which is located a predetermined distance from the element isolation into the element formation region side. Since the method is performed by implanting impurity ions using the photoresist mask having the opening and the gate electrode as a mask and then diffusing the impurity ions, the pattern of the photoresist mask used for manufacturing a conventional semiconductor device. Claim 1 only by changing
It is possible to manufacture a semiconductor device having such a configuration, and thus it is possible to suppress an increase in manufacturing cost.

According to the twelfth aspect of the invention, in the manufacturing method of the eighth, ninth or tenth aspect, the source region or the drain region having a structure separated from the channel stop region is provided with impurity ions from the electrode on the silicon substrate. Since it is formed by diffusing, it is possible to reduce the doping depth of impurities and suppress the occurrence of punch through.

According to the thirteenth aspect of the present invention, a so-called LD
As a method of manufacturing a semiconductor device having a field effect transistor having a D structure, a channel stop region and element isolation are formed, a threshold control impurity is doped, a gate electrode is formed, and then a low concentration impurity is doped. After forming the low-concentration source and drain regions and the sidewalls on the sides of the gate electrode, at least the high-concentration drain region and the high-concentration source region to which a high voltage is applied are predetermined from the end of the element isolation. Since a high-concentration impurity is doped so as to enter the element formation region side by a distance and move away from the channel stop region, a semiconductor device including a field-effect transistor having a normal LDD structure can be formed without difficulty in alignment. The semiconductor device having the structure according to claim 4 can be manufactured in the same number of steps as the above, and thus the semiconductor It can be achieved and reduction of the ease and cost of location production.

According to the fourteenth aspect of the invention, in the case of a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor, the step of forming the high concentration source region and the high concentration drain region is performed with high concentration. The high-concentration source region or the high-concentration drain region is formed separately from the channel stop region only in the n-channel field effect transistor in which an inversion layer is likely to occur at the boundary between the source region or the high-concentration drain region and the channel stop region. Therefore, the semiconductor device can be manufactured relatively easily.

According to the fifteenth aspect of the invention, in the case of a semiconductor device having an n-channel field effect transistor and a p-channel field effect transistor of LDD structure, LDD
Since the high-concentration source region or the high-concentration drain region is formed separately from the channel stop region for both the n-channel field effect transistor and the p-channel field effect transistor having the structure, the breakdown voltage of the p-channel field effect transistor is increased. The characteristics can be maintained more reliably.

According to the invention of claim 16, the above-mentioned claim 1
In the manufacturing method of 3, 14 or 15, the high concentration source,
The drain region is formed by implanting impurity ions using a photoresist mask and a gate electrode, which are opened inward from a position that is located a predetermined distance from the element isolation region as a mask, and then diffuse the impurity ions. Since it was done by simply changing the pattern of the photoresist mask used in the manufacture of conventional semiconductor devices,
It is possible to manufacture the semiconductor device having the configuration according to the fourth aspect, and thus it is possible to suppress an increase in manufacturing cost.

According to the invention of claim 17, said claim 1
In the manufacturing method of 15, the high concentration source region or the high concentration drain region having a structure separated from the channel stop region is formed by diffusion of impurity ions from the electrode on the silicon substrate. It is possible to make the dope depth shallow and suppress punch-through.

According to the eighteenth aspect of the invention, in the manufacturing method of the eighth, ninth, tenth, eleventh, twelve, thirteenth, fourteenth, fifteenth, sixteenth or seventeenth aspect, the punch through stop region and the channel stop region are simultaneously formed. Since it is formed, the number of steps can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a plane and cross-sectional structure of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view showing a state of the substrate in the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a diagram showing a plane and cross-sectional structure of a semiconductor device according to a second embodiment.

FIG. 4 is a cross-sectional view showing a state of a substrate in a manufacturing process of a semiconductor device according to a second embodiment.

FIG. 5 is a diagram showing a plane and cross-sectional structure of a semiconductor device according to a third embodiment.

FIG. 6 is a cross-sectional view showing a state of a substrate in a manufacturing process of a semiconductor device according to a third embodiment.

FIG. 7 is a cross-sectional view showing a state of a substrate in a manufacturing process of a semiconductor device according to a fourth embodiment.

FIG. 8 is a cross-sectional view showing a state of a substrate in a manufacturing process of a semiconductor device according to a fifth embodiment.

FIG. 9 is a diagram showing experimental data regarding changes in withstand voltage characteristics with respect to changes in the overlap between the element formation region and the mask, and the installation state of the mask.

FIG. 10 is an electric circuit diagram of a booster circuit according to a sixth embodiment.

FIG. 11 is a diagram showing waveforms of voltage signals in various parts of the booster circuit according to the sixth embodiment.

FIG. 12 is a cross-sectional view showing a structure in the vicinity of an FET of a conventional general semiconductor device.

FIG. 13 is a cross-sectional view showing a state in the vicinity of an FET in a conventional general semiconductor device manufacturing process.

FIG. 14 is an FE of a conventional semiconductor device described in one publication.
It is a figure which shows the plane and sectional structure of T vicinity.

FIG. 15 is a diagram showing a plane and a cross-sectional structure near an FET of a semiconductor device described in another publication.

[Explanation of symbols]

 10 Silicon Substrate (Semiconductor Substrate) 11 Element Isolation 12 Gate Electrode 13a Channel Stop Region 13b Punch Through Stop Region 15 Source Region 15a High Concentration Source Region 15b Low Concentration Source Region 16 Drain Region 16a High Concentration Drain Region 16b High Concentration Drain Region 17 Gate Region 18 Gate insulating film 20 Offset region 21 Overlap region 24 First buffer region 25 Second buffer region 31 Silicon nitride film 32 Photoresist mask 33 Silicon oxide film Rfet Device formation region Rcont Contact formation region

Claims (18)

[Claims] 1. A semiconductor device in which a field effect transistor is mounted in an element forming region of a semiconductor substrate doped with a first conductivity type impurity, the field effect transistor being formed on the semiconductor substrate. A source region of a field effect transistor in which a gate electrode and regions on both sides below the gate electrode in the semiconductor substrate are doped with a second conductivity type impurity having a conductivity type opposite to that of the first conductivity type impurity, and A drain region, an element isolation formed on the semiconductor substrate around the element formation region and separating the element formation region from other regions, and a first conductivity type impurity formed below the element isolation in the semiconductor substrate. A channel stop region that is doped with at least one of the drain region and the source region in the semiconductor substrate to which a high voltage is applied, and the channel stop region. A first buffer region, which is formed between the semiconductor substrate and the first region, and is doped with a first conductivity type impurity or a second conductivity type impurity at a concentration for controlling a threshold; And a second buffer region formed in a region adjacent to the first buffer region and doped with a first conductivity type impurity or a second conductivity type impurity at a threshold controlling concentration. 2. The semiconductor device according to claim 1, wherein the first buffer region is provided between both the drain region and the source region in the semiconductor substrate and the channel stop region. Characteristic semiconductor device. 3. The semiconductor device according to claim 1, wherein the semiconductor device has a booster circuit, and the high potential portion of the booster circuit includes a channel stop region formed by the first buffer region of the field effect transistor. A semiconductor device, characterized in that the source region or the drain region formed apart from each other is connected. 4. A semiconductor device in which a field effect transistor is mounted in an element formation region of a semiconductor substrate doped with a first conductivity type impurity, wherein the field effect transistor is formed on the semiconductor substrate. A gate electrode, sidewalls provided on both side walls of the gate electrode, and a second conductivity type that is formed in a region below the sidewall in the semiconductor substrate and has a conductivity type opposite to that of the first conductivity type impurity. The low-concentration source region and the low-concentration drain region of the field-effect transistor in which impurities are effectively doped at a low concentration, and the region outside and adjacent to the low-concentration source region and the low-concentration drain region in the semiconductor substrate, respectively. A high-concentration source region and a high-concentration drain region of the field-effect transistor formed and doped with the second-conductivity-type impurity effectively in a high concentration; Element isolation formed on the semiconductor substrate around the element formation region and separating the element formation region from other regions, and formed on the semiconductor substrate below the element isolation and doped with a first conductivity type impurity. The channel stop region is formed between at least a region to which a high voltage is applied among the high-concentration drain region and the high-concentration source region in the semiconductor substrate and the channel stop region, and the second-conductivity-type impurity has the low concentration. A first buffer region doped with substantially the same concentration as that of the source region and the low-concentration drain region; and a region of the semiconductor substrate below the gate electrode and adjacent to the element isolation, the first conductivity type or the second conductivity type. A semiconductor device comprising: a second buffer region doped with a conductivity type impurity at a concentration for controlling a threshold value. 5. The semiconductor device according to claim 4, wherein the first buffer region is provided between the high concentration source region and the high concentration drain region in a semiconductor substrate and the channel stop region. A semiconductor device characterized in that. 6. The semiconductor device according to claim 4, wherein the semiconductor device has a booster circuit, and is formed in a high potential portion of the booster circuit away from a channel stop region of the field effect transistor. A high-concentration source region or a high-concentration drain region is connected to the semiconductor device. 7. The semiconductor device according to claim 1, 2, 4 or 5, which is below the element formation region of the semiconductor substrate and is continuous with the channel stop region and at least higher than the source region and the drain region. A semiconductor device having a punch-through stop region formed apart from a region to which a voltage is applied and doped with a first conductivity type impurity having a concentration substantially the same as that of a channel stop region. 8. A field effect transistor formed in a device forming region of a semiconductor substrate doped with a first conductivity type impurity, the field effect transistor including a gate electrode, a source region and a drain region, and the device forming region as another region. A method of manufacturing a semiconductor device having element isolation for isolation, comprising a step of doping an impurity for forming a channel stop into a region of the semiconductor substrate where the element isolation is to be formed, and the element isolation on the semiconductor substrate. A step of forming an insulating film for element isolation in a region to be formed, a step of doping the element formation area with a first conductivity type or second conductivity type impurity at a concentration for threshold control, and the element formation area A step of forming a gate electrode of the field effect transistor on the top surface of the element formation region, and a conductivity type opposite to the first conductivity type impurity in a region of the element formation region on the side of the gate electrode. And a step of forming a source region and a drain region of the field effect transistor by doping the second conductivity type impurity, and the step of forming the drain region and the source region includes at least the drain region and the source region. A method of manufacturing a semiconductor device, wherein a region to which a high voltage is applied is formed so as to enter a device forming region side from an end of device isolation by a predetermined distance and separate from a channel stop region. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor device is an n-channel field effect transistor and a p-type transistor.
A channel field effect transistor is included, and the step of forming the source region and the drain region includes n
In the element formation region of the channel field effect transistor,
At least a region to which a high voltage is applied is separated from the channel stop region in the drain region and the source region, while both of the drain region and the source region are channel stop in the element formation region of the p-channel field effect transistor. A method for manufacturing a semiconductor device, which is performed so as to overlap with a region. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor device is an n-channel field effect transistor and a p-type transistor.
A channel field effect transistor is included, and the step of forming the source region and the drain region includes n
In both element formation regions of the channel field effect transistor and the p channel field effect transistor, at least a region to which a high voltage is applied among the drain region and the source region is separated from the channel stop region. Manufacturing method of semiconductor device. 11. The method for manufacturing a semiconductor according to claim 8, 9 or 10, wherein in the step of forming the drain region and the source region, the source region or the drain region separated from the channel stop region is more predetermined than element isolation. A semiconductor device characterized in that after impurity ions are implanted using a photoresist mask having an opening inside and a gate electrode as a mask from a position that enters the element formation region side by a distance, the impurity ions are diffused. Production method. 12. The method of manufacturing a semiconductor according to claim 8, 9 or 10, wherein in the step of forming the drain region and the source region, impurities are doped in the source region or the drain region separated from the channel stop region. A method for manufacturing a semiconductor device, comprising: forming an electrode made of a conductive material doped with the impurity on the region, and then heating to diffuse the impurity ions from the electrode into the semiconductor substrate. . 13. An electric field formed in a device formation region of a semiconductor substrate doped with a first conductivity type impurity, the electric field including a gate electrode, a low concentration source region, a low concentration drain region, a high concentration source region and a high concentration drain region. A method of manufacturing a semiconductor device having an effect transistor and element isolation for isolating the element formation region from other regions, wherein a region for forming the element isolation of the semiconductor substrate is doped with an impurity for forming a channel stop. And a step of forming an insulating film for element isolation in a region for forming the element isolation on the semiconductor substrate, and a concentration of a first conductivity type or a second conductivity type impurity for threshold control in the element formation region. And a step of forming a gate electrode of the field effect transistor on the device forming region, and a step of forming a gate electrode of the device forming region on the side of the gate electrode of the device forming region. A step of effectively doping the region with a second conductivity type impurity having a conductivity type opposite to that of the first conductivity type at a low concentration; and a step of forming sidewalls on both sides of the gate electrode of the field effect transistor, After forming the side wall of the gate electrode, the region of the side of the side wall of the element forming region is effectively doped with a high concentration of the second conductivity type to form a high concentration source region and a high concentration drain region. And a step of forming the high-concentration source region and the high-concentration drain region, the high-concentration drain region and the high-concentration source region at least a region to which a high voltage is applied is at a predetermined distance from the end of the element isolation. A method of manufacturing a semiconductor device, characterized in that it is carried out so as to enter only the element formation region side and separate from the channel stop region. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the semiconductor device includes an n-channel field effect transistor and a p-channel transistor.
The step of forming the high-concentration source region and the high-concentration drain region includes the step of forming the high-concentration drain region and the high-concentration source region in the element forming region of the n-channel field-effect transistor. At least a region to which a high voltage is applied is separated from the channel stop region, while both the high-concentration drain region and the high-concentration source region overlap the channel stop region in the element formation region of the p-channel field effect transistor. A method of manufacturing a semiconductor device, comprising: 15. The method of manufacturing a semiconductor device according to claim 13, wherein the semiconductor device includes an n-channel field effect transistor and a p-channel field effect transistor.
The step of forming the high-concentration source region and the high-concentration drain region includes the step of forming a high-concentration source region and a high-concentration drain region in the element forming regions of both the n-channel field-effect transistor and the p-channel field-effect transistor. A method of manufacturing a semiconductor device, characterized in that at least a region to which a high voltage is applied among the concentration drain region and the high concentration source region is separated from the channel stop region. 16. The method of manufacturing a semiconductor according to claim 13, 14 or 15, wherein in the step of forming the high-concentration drain region and the high-concentration source region, the high-concentration source region or the high-concentration drain separated from the channel stop region is formed. In the region, it is performed by implanting impurity ions using a photoresist mask and a gate electrode, which are opened inward from a position that enters the element formation region side by a predetermined distance from the element isolation, and then diffuse the impurity ions. A method of manufacturing a semiconductor device, comprising: 17. The method for manufacturing a semiconductor according to claim 13, 14 or 15, wherein the step of forming the high-concentration drain region and the high-concentration source region comprises forming a high-concentration source region or a high-concentration drain away from a channel stop region. In the region, an electrode made of a conductive material doped with the impurity is formed on the region doped with the impurity, and then heated to diffuse impurity ions from the electrode into the semiconductor substrate. A method for manufacturing a characteristic semiconductor device. 18. The method according to claim 8, 9, 10, 11, 12, 1.
In the method of manufacturing a semiconductor device according to 3, 14, 15, 16 or 17, in the step of doping impurities for forming the channel stop region, impurity ions are added from the element formation region and the element isolation after the element isolation formation step. High-energy implantation, and at the same time, the impurity ions are also implanted below the element forming region of the semiconductor substrate as impurities for forming punch-through stop regions. Method.