JPS63305562A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a highly reliable MIS transistor integrated circuit (MIS-IC), by using a second MIS transistor for the MIS peripheral circuit handling relatively high voltage and high current, while using a first MIS transistor constructed in an ordinary manner for the circuit handling small signals. CONSTITUTION:A source region 16 and drain region 17 having a high dopant concentration of about 10<20>-10<21> atoms/cm<2> are formed on each of element forming regions 10 and 20 on the surface of a substrate 11. In the element forming region 19, a first MIS transistor having the source and drain regions 16, 17 directly connected to a channel stop region 18 provided under an element isolating region, namely an ordinary MIS transistor 22 is formed. In the other element forming region 20, a second MIS transistor having the source and drain regions 16 and 17 not connected directly to a channel stop region 18, namely MIS transistor 23 having high dielectric strength is formed. An MIS transistor integrated circuit having these transistors 22 and 23 can be provided with high reliability in this manner.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an integrated circuit (formerly 5-IC) of MIS transistors.

[Summary of the invention]

The present invention provides a MISI-transistor integrated circuit, in which:
A first MISI-transistor having a source region and a drain region that are continuous with the element isolation region in a plane, and a second MISI transistor in which at least a high concentration region of the source region and the drain region is formed spaced apart from the element isolation region in a plane. MIS transistors with different junction breakdown voltages can be used.
This makes it possible to manufacture transistors using the same manufacturing process, and to provide highly reliable old 5-ICs.

[Conventional technology]

Typically, a MISI-transistor integrated circuit is constructed as shown in FIG. That is, a gate electrode (3) is formed on the entire surface of a semiconductor substrate (II) of a first conductivity type, for example, a p-type, via a gate electrode 1 film (2), and insulation between this gate electrode (3) and a field portion is formed. An element isolation region (5) made of a thick oxidized FjI (4) layer, that is, a selective oxidation (LOGO5) method.
) is used as a mask to introduce a second conductivity type, for example, an n-type impurity, in a self-aligned manner to form a highly concentrated n-type source region (6) and drain region (7) on the surface of the substrate (1). Ru. In this case, a channel stop region (8) made of a p+ layer is formed in advance under the element isolation region (6), and a source region (6) and a drain region (7) are formed in the channel stop region (8) of the p+ layer. It is connected.

To increase the withstand voltage of such Mist-transistors, there are several methods: lowering the concentration of the substrate, increasing the junction depth of the source and drain regions, and forming the source and drain regions using a double diffusion method to reduce the concentration of the electric field. There are various ways to alleviate this and other methods.

[Problem that the invention seeks to solve]

By the way, the breakdown voltage (drain breakdown voltage) of the MIS transistor
In FIG. 9, the problem is the breakdown voltage of the junction part (al) in contact with the gate part (withstand voltage of al and the breakdown voltage of bl in contact with the channel stop region (8)) and the breakdown voltage of the junction part (bl) in contact with the channel stop region (8). ) and the drain region (7) are shallow, the breakdown voltage of the transistor is determined by the breakdown voltage of the junction (al), and when the junction is deep, the breakdown voltage of the transistor is determined by the breakdown voltage of the junction molecule b).

On the other hand, for example, in a dynamic RAM composed of MISI-transistors, a high-performance MISI transistor in a memory cell is used.
- The transistor has a conventional structure, has a relatively high voltage,
MIS transistors in peripheral circuits that handle high current have high withstand voltage M
An ISI-transistor is required. However, it has been difficult to manufacture conventional high-voltage MIS transistors using the same manufacturing process as ordinary MIS transistors.

In view of the above-mentioned points, the present invention provides a semiconductor device in which MIS transistors having different breakdown voltages can be constructed in the same manufacturing process.

Means for Solving Problem c] The present invention provides a semiconductor device having a source region and a drain region of a second conductivity type that are continuous in plan with an element isolation region formed on a semiconductor region of a first conductivity type. A second MIS transistor formed of the first MIS transistor and at least the high concentration regions of the source region and the drain region separated from the element isolation region in a plane.
It is configured with an ISI transistor.

A channel stop region is formed by a highly doped first conductivity type layer under the element isolation region. The source region and drain region of the first MIS transistor are
It is formed in self-alignment with the element isolation region and is in contact with the underlying channel stop region. Further, the source region and drain region of the second MISI transistor are formed so as not to contact the element isolation region and thus the channel stop region therebelow. Or a second MIS
The source region and drain region of the I-transistor are connected to the element isolation region and therefore to the channel stop region thereunder,
It is formed so as not to be in contact with the gate part. Or second MI
In the source and drain regions of the SI-transistor, the low concentration region is formed in self-alignment with the element isolation region, and the high concentration region does not touch the element isolation region, the channel stop region below it, or the channel stop region and the gate part. It is formed like this.

[Effect]

The first MrS transistor has a normal breakdown voltage.

On the other hand, the second MISI-transistor is configured so that the source region and the drain region, especially at least their high concentration region, do not touch the channel stop region under the element isolation region, so that the junction portion (withstand voltage of bl) rises,
The breakdown voltage is higher than that of the first MIS transistor. or,
When the source region and the drain region of the second MIS transistor, especially at least the high concentration region thereof, are configured so as not to contact the channel stop region and gate portion under the element isolation region, the junction portions (a) and [b] The breakdown voltage is increased, and the second MIS transistor has a higher breakdown voltage than the first MIS transistor. These first and second MIS transistors can be formed by changing the mask pattern when forming the source and drain regions, especially their high concentration regions, by ion implantation or diffusion. By forming a pattern in which a mask is formed on the inside, they can be formed simultaneously in the same manufacturing process without changing process conditions.

Therefore, by using this high-voltage second MrS transistor in the MIS peripheral circuit that handles relatively high voltage and high current, and by using the first M[31 transistor with a normal structure in the small signal part, it is possible to achieve high reliability. Mis-IC is obtained.

〔Example〕

Embodiments of the semiconductor device according to the present invention will be described below with reference to the drawings.

1 and 2 show one embodiment of the present invention.

In this example, the impurity concentration is 1015 to 1010, for example.
P-type silicon substrate (11) of about 16ato/ctA
For example, 3
After forming a channel stop region (18) using p+ layers of approximately 1016 to 3×10” atoms/cn!, an element isolation region (15) is formed using a thick oxide layer (■4) using selective oxidation (LOGO3) method. One element formation region (15) surrounded by this element isolation region (15)
19) and other element forming regions (20), for example, Si.
A gate electrode (13) made of, for example, polycrystalline silicon is formed via a gate insulating film (12) made of O2. Then, a photoresist JiFif (21) with a predetermined pattern is formed as a mask for impurity introduction, and the substrate (11) of each element formation region (19) and (20) is formed by ion implantation.
) On the surface, for example, an impurity concentration of 1020 to 10" atoms
A source region (16) and a drain region (17) having a high concentration of approximately s/cJ are formed. At this time, in the first element formation region 14 (19), a photoresist layer (21) is provided outside the edge of the element isolation region (15),
A source region (16) and a drain region (17) are formed in self-alignment with I5) and gate voltage ti (13). In addition, in the other element formation region 6 (20), the photoresist I'ti
f (21) is provided inside the edge of the element isolation region (15), and this photoresist layer (21) and gate electrode (13)
) as a mask, source region (16) and drain region (1
7). As a result, one element formation area (19
), the channel stop region (18
) a source region (16) and a drain region (1
7) First MIS transistor with normal MI
A source region (16) and a drain region (17) in which an S transistor (22) is formed and which are not in direct contact with the channel region (18) in other element formation regions (20).
A second MIS transistor having a high breakdown voltage MIS
A MIS transistor integrated circuit in which an I-transistor (23) is formed is obtained.

The source region (16) and drain region (17) in the first MIS transistor (23) and the element isolation region (1
5) The interval t1 between the
．． It was made of 2μ steel.

FIGS. 3 and 4 show other embodiments of the present invention.

In this example, parts corresponding to those in FIGS. 1 and 2 are given the same reference numerals and redundant explanations are omitted. 17) respectively in the channel stop area (12
) and the gate portion, that is, directly under the gate electrode (13) so as not to be in direct contact with each other to constitute a second MIS transistor, that is, a high voltage MIS transistor (24). Element isolation region (15), source region (16) and drain region (
17) Distance t1 between gate region and source region (16)
and the distance t2 between the drain region (17) is 1μ.
It is possible to use steel or higher, and in this example, 1.2μ steel is used for each.

As a result, the first Mi
s transistor or normal Mis transistor (22)
is formed, and a second MIS is formed in another element formation region (20).
Transistor, high voltage MIS transistor (24)
A MIS transistor integrated circuit is obtained.

6, 7, and 8 respectively show the first MIS transistor (22) having the above-described configuration, and the second MIS transistor (22) in FIG.
IS transistor (23) and the second Mis in FIG.
Transistor (24) (7) I o V.

Show characteristics. The first MIS transistor, i.e. the normal MI
As shown in FIG. 6, the S transistor (22) has a breakdown voltage Io of about 7 V, which is determined by the concentration of the channel stop region (18) in the element isolation region. On the other hand, in the second MIS transistor (23) of FIG. 1 in which the highly doped source region (16) and drain region (17) are separated from the channel stop region (18) of the element isolation region, the structure shown in FIG. As shown, the breakdown voltage is 13.2V, which is about 2.5V higher than the normal MIS transistor (22). Further, the source region (16) and the drain region (17) are separated by δ from the channel stop region (18) of the element isolation region and the gate region.
Second MISI transistor (24) in Fig. 3
In this case, the breakdown voltage is 14.0 as shown in Figure 8.
V, 3V from the normal MIS transistor (22)
or more. However, since the source and drain resistances of this M I S I-transistor (24) are high,
It deteriorates to 1 o-vo characteristic.

For example, MIS transistors (23) or (24) with the above configuration are used in dynamic RAM and MIS peripheral circuits that handle relatively high voltages and high currents.
Highly reliable dynamic RA is achieved by using a MIS transistor (22) with a normal structure as the SI transistor.
M can be configured.

FIG. 5 shows another embodiment of the invention. In this example,
A thick oxidation layer (14) is formed in the element formation region (19) of
) and the source region (
16) and the drain region (17), for example, form low concentration regions (16a) and (17a) with an impurity concentration of about 1017 to 101018ato/-, and then provide a side wall part on the gate electrode so that it does not contact the gate part. like 102
High concentration region of 0 to 102 iatos/al (16
b) and (17b') to form source regions (1
6) and drain region (17), forming the first M T
S transistor, that is, normal L D D fI structure M
An is transistor (25) is formed. In addition, in the other element formation region (20), using the thick oxide layer (14) and gate electrode (13) as masks, low concentration regions (16a) constituting the source region (16) and drain region (17) are formed.
and (17a), and then high concentration regions (16b) and (17b) are formed so as not to be in contact with the channel stop region (18) of the element isolation region and the gate region to form the source region (16) and the drain region. (17) and the second
A MISI transistor (26) with high breakdown voltage is formed.

The low concentration source regions (16a) and drain regions (17a) of the first and second MISI transistors are formed in the same process, and the high concentration source regions (17a) of the first and second MISI transistors are formed in the same process. 16b) and the drain region (17b) are also formed in the same process by selecting a mask pattern.

Even in such a configuration, the second MIS transistor (2
6), the source region (16) and the drain region (17)
Since the high concentration regions (16b) and (17b) do not touch the channel stop region (18), a high breakdown voltage is achieved.

In this case, the low concentration regions (16a) and (17a)
) because 1. -VD characteristics are stabilized.

Note that, although the above description deals with an n-channel MIS transistor, the same applies to a p-channel MIS transistor.

〔Effect of the invention〕

According to the present invention, by forming at least the highly doped source and drain regions of the MISI transistor apart from the element isolation region, it is possible to
The breakdown voltage can be improved compared to the S transistor. This high voltage MIS transistor can be formed at the same time as a normal MIS transistor in the same manufacturing process by simply changing the mask pattern when forming the source and drain regions. Therefore, by using a high-voltage M■S transistor with the above configuration in the Mis peripheral circuit that handles relatively high voltage and high current, and using a MISI-transistor with a normal structure in the small signal part, high reliability can be achieved using the old 5-IC. can be configured. Therefore, for example, dynamic RAM
It is suitable for application to MIS-ICs such as the following.

[Brief explanation of the drawing]

1 and 2 are a cross-sectional view and a plan view of one embodiment of the semiconductor device of the present invention, and FIGS. 3 and 4 are cross-sectional views and a plan view of another embodiment of the semiconductor device of the present invention. Plan view,
FIG. 5 is a sectional view showing still another embodiment of the semiconductor device of the present invention, FIGS. 6, 7, and 8 are TD vD characteristic diagrams, and FIG. 9 is a sectional view of a conventional Mis transistor integrated circuit. It is. (11) is a silicon substrate, (12) is a gate insulating film, (
13) is a gate electrode, (15) is an element isolation region, and (16) is a gate electrode.
) is the source region, (17) is the drain region, (18)
is the channel stop area.

Claims (1)

[Claims] A first M comprising a source region and a drain region that are continuous in plan with an element isolation region formed on a semiconductor region.
an IS transistor; and a second transistor in which at least high concentration regions of a source region and a drain region are formed spaced apart from the element isolation region in a plane.
A semiconductor device comprising a MIS transistor.