JP3301057B2 - Method of forming vertical gate field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to field effect transistors, and more particularly to vertical field effect transistors.

[0002]

BACKGROUND OF THE INVENTION Field effect transistors (FETs) are the basic building blocks in the field of integrated circuits. FETs can be classified into two basic structural types, horizontal and vertical. Horizontal or horizontal FE
T indicates a carrier flow from the source to the drain in a direction parallel (for example, horizontal) to the surface of the substrate on which the source and the drain are formed. A vertical FET exhibits carrier flow from source to drain in a direction perpendicular (eg, perpendicular) to the plane of the substrate on which the source and drain are formed.

[0003] Since horizontal FETs can be easily integrated,
Widely used and preferred by the semiconductor industry,
Vertical FETs have many advantages over horizontal FETs. Since the channel length of a vertical FET is not a function of the smallest feature size (eg, about 0.25 micrometers) that can be resolved by modern lithographic apparatus and methods, a vertical FET has a shorter channel length ( (E.g., about 0.1 micrometer), so vertical FETs have the ability to switch faster than horizontal FETs and greater power capacity. In addition, vertical FETs have the potential for greater packing density.

[0004] FET structures can have a single gate (eg, for forming a single channel) or a pair of gates (eg, for forming a pair of channels), and a double gate.
The gate version offers the advantage of increased current carrying capacity (eg, typically greater than twice the single gate version). Many horizontal double gate FET structures have been proposed, especially in the area of silicon-on-insulator (SOI). Such structures generally require a lower gate on the back of the substrate in addition to the usual upper gate. It is difficult to manufacture such a structure. The reason is that the upper and lower gates must be aligned within tolerances that exceed the accuracy of modern lithographic apparatus and methods, and the self-aligned method requires a layer between the upper and lower gates. This is because it is inhibited.

Further, the body of the transistor (for example,
It is necessary to have means for making electrical contact (where the channel is formed). Such contact is important to avoid unwanted parasitic effects caused by bodies with floating potential. The floating body effect can be a problem, especially for SOI transistors. However, proposed horizontal double-gate FET structures generally lack means for contacting the body of the transistor.

What is needed, therefore, is a double gate FET that solves the above-mentioned problems.

[0007]

It is an object of the present invention to provide a vertical double gate transistor structure having a large current carrying capacity.

It is another object of the present invention to provide a vertical double gate transistor structure having a conductive connection to a body in which a channel is formed.

It is yet another object of the present invention to provide a vertical double gate transistor structure that can be manufactured utilizing known state of the art manufacturing techniques.

[0010]

SUMMARY OF THE INVENTION The present invention provides a vertical double
The invention relates to a gate transistor and a method for manufacturing a vertical double gate transistor. In one embodiment of the present invention, a transistor has a substrate and a source layer, a channel layer, a drain layer, and a dielectric layer laminated on the substrate.
Above the first end of the transistor, a gate oxide and a conductive gate surround the top and sides of the stacked layers. Electrical contact is made at the second end of the transistor. In one embodiment, the first end has a plurality of fingers surrounded by a gate oxide and a conductive gate.

In another embodiment of the present invention, a method is provided for fabricating a vertical double gate transistor. The method includes providing a semiconductor substrate, forming a source layer on the semiconductor substrate, forming a channel layer on the source layer, and one end of the channel layer on a portion of the channel layer. Forming a drain layer on the channel layer and the etch stop layer; forming a first dielectric layer on the drain layer; forming a source layer and a channel on the drain layer; Forming a gate dielectric and a conductive gate over a portion of the layer, the drain layer, having a first end having an etch stop layer and a second end having a gate oxide and a conductive gate; Forming an insulating stack; forming a conformal dielectric layer over the conductive gate; and forming a second layer of the insulating stack to expose the etch stop layer. Removing a portion of the end drain layer and removing portions of the source and channel layers that are not protected by the etch stop layer to form contact traps in each of the source, channel and drain layers. Forming sidewall spacers along the sides of the contact pedestal, and forming vertical contacts connected to each of the contact pedestals of the source, channel, and drain layers.

[0012]

Referring now to the drawings, in the embodiment of the present invention illustrated herein, the device is a CMOS.
(Complementary MOS) devices, particularly enhancement-mode NMOS (n-channel MOS) FETs. As will be appreciated by those skilled in the art, according to the teachings of the present invention, n
A similar PMOS (p-channel MOS) FET by using p-type dopants instead of p-type dopants
Can be produced, and vice versa.

FIG. 1 is a sectional view of a semiconductor substrate 10. FIGS. 10 and 19 show the same device as FIG. 1, each with a cross-section A- at the first end 24.
A ′ corresponds to the cross section BB ′ at the second end 26, and similarly FIGS. 2 to 9 show the remaining drawings, FIGS.
8 and FIGS. 20 to 27 (for example, in FIG. 2, the AA ′ cross section and the BB ′ cross section correspond to FIG. 11 and FIG. 20, respectively). Substrate 10
Can be silicon, gallium arsenide, or other semiconductor material. For example, substrate 10 can be bulk or SOI. If the substrate 10 is a bulk substrate, a p-type well (not shown) can be formed in the substrate 10. Next, an n-type source layer 12, preferably an n ^{+ -type} source layer, is formed on the substrate 10, for reasons described below. The source layer 12 can be formed by a normal ion implantation method into the substrate 10 or by an epitaxial method known in the art.

2, 11 and 20, the p-type channel layer 1
4 are preferably formed by a low temperature epitaxial (LTE) method. For example, a suitable LTE method is described in S.
“Low-Temperatatu by Meyerson
re Silicon Epitaxy by Ult
rahigh Vacuum / Chemical Va
Appl. Phys of "por Deposition"
s. Lett. 48 (12), Mar. 24,198
6, pp. 797-799. The LTE method is preferred for forming the channel layer 14 to avoid excessive outdiffusion from the n-type source layer 12, thereby providing greater control over the channel length than provided by other methods. Becomes possible. The thickness of the channel layer 14 is preferably about 1000 °. In order to grow a high quality channel layer 14, it is preferable that the source layer 12 be made amorphous and then recrystallized at the beginning of the LTE process. The doping concentration applied to the channel layer 14 by the LTE process is preferably in a range of 1 × 10 ¹⁶ atoms / cm ^{3 to} 3 × 10 ¹⁸ atoms / cm ³ depending on a desired threshold voltage.

3, 12 and 21, an etch stop layer 16 is formed over a portion of the second end 26. FIG. The size and location of the etch stop layer 16 can be determined lithographically and should be dimensioned and have tolerances to ensure coverage for the area of the channel layer 14 needed to form body contacts. It is. The etch stop layer 16 is about 200 to 5
It can be finally removed by an etchant having a selectivity of at least 10: 1 with respect to the channel layer 14 and is preferably a dielectric, more preferably an oxide.

Next, in FIGS. 3, 12, and 21, an n-type drain layer 18, preferably an n ⁺ -type drain layer, is formed over the channel layer 14 and the etch stop layer 16.
The drain layer 18 is preferably formed by chemical vapor deposition (CVD) of polycrystalline silicon, followed by a diffusion anneal. The diffusion annealing is performed at about 800 ° C. to 10 ° C.
At a temperature of 50 ° C., for example 950 ° C. for rapid thermal annealing, a heating step in an inert ambient environment can be included. The combination of CVD with a subsequent diffusion anneal allows for limited outdiffusion from the drain layer 18 to the channel layer 14, and furthermore, the effective channel length L _eff
(E.g., approximately equal to the thickness of the channel layer 14 that is smaller than the out-diffusion shown by the drain layer 18 and the source layer 12)
4 enables a portion of the polysilicon drain layer 18 to be recrystallized.

In FIGS. 3, 12, and 21, a passivation cap 28 is formed over the drain layer 18. FIG.
The passivation cap 28 is preferably a CVD
Is a dielectric formed by tetraethylorthosilicate (TEOS) at about 700.degree. Next, substrate 10 is patterned to form transistor stack 32. This patterning is performed on the channel layer 1 on the first end 24 of the transistor stack 32.
4 (hereinafter referred to as a mesa width W, and the display of W is shown in FIG. 12). To operate in a fully depleted mode (eg, a merged depletion region), for a completed transistor having an effective channel length L _eff of about 1000 °, the mesa width W will preferably be about 300-300.
Should be 1000 °. As the mesa width increases, the threshold voltage V _th becomes lower than complete depletion, that is, the threshold voltage V _th is extremely sensitive to the doping concentration of the channel layer 14. FIG. 30 shows that W = 300 ° and W = 1
The simulation sensitivity of the threshold voltage to the channel layer doping concentration at 500 ° is shown. As is apparent from this graph, at a doping concentration of about 5 × 10 ¹⁷ / cm ³ or less, a transistor having a mesa width W of 1500 ° generates punch-through, and as a result,
This results in gate control losses and extremely low threshold voltages. In contrast, for relatively narrow mesa widths W, such as 300 °, the channel layer 14 can be lightly doped, providing high carrier mobility and therefore large current carrying capacity without sacrificing gate control. Give benefits like. Mesa widths in the range of 300-1000 ° can be achieved by utilizing known sidewall image transfer techniques.

In FIGS. 4, 13, and 22, a vertical gate oxide 30 is grown along the sides of the transistor stack 32, ie, along the sides of each of the source layer 12, the channel layer 14, and the drain layer 18. Gate oxide 30 overlapping source layer 12 and drain layer 18
Is manufactured thicker than the portion of the gate oxide 30 that overlaps the channel layer 14 to provide a smaller capacitance value than that provided by the oxide that overlaps the channel layer 14. Thus, the input capacitance created by the gate oxide overlapping source layer 12 and drain layer 18 can be minimized. The oxidizing conditions and the doping of the source layer 12 and the drain layer 18 can be selected so as to take advantage of the change in the oxidizing rate due to the doping concentration of the semiconductor. For example, the oxidation rate of the n ⁺ polysilicon layer (1.5 × 10 ²⁰ / cm ³ ) can be increased to about five times the oxidation rate of the p ⁻ layer (1 × 10 ¹⁶ / cm ³ ). Drain layer 18 and source layer 1
2 are each doped at the n ⁺ level and if the epitaxial channel layer 14 is p ⁻
And the thickness of the portion of the gate oxide 30 that overlaps the drain layer 18 can be about five times the thickness of the portion of the gate oxide that overlaps the channel layer 14.

In FIGS. 5, 14 and 23, the conformal
Gates 34 and gate caps 36 are formed on and surround the sides of the transistor stack 32 and may form adjacent structures. Gate 34 must be conductive, preferably polysilicon or tungsten, more preferably n ⁺ polysilicon, or p ⁺ polysilicon if a higher threshold voltage is required for lower off-current. Preferably, and the gate 34
Can be formed by a known CVD method. Gate cap 36 should be a dielectric material and can be grown and deposited by known methods. Next, the portion of the gate 34 and the gate cap 36 covering the second end 26 of the transistor stack 32 is removed, and the gate 34 and the gate cap 36 are removed from the first end 24 of the transistor stack 32. Only the exposed edges can be covered. This removal is accomplished by providing a photosensitizer and patterning the photosensitizer such that the second end 26 of the transistor stack 32 is exposed.
By etching the transistor stack 32 until the passivation cap 28 is exposed. Forming the gate 34 in this manner avoids the alignment problem described above.
Note that this problem is generally associated with a horizontal double gate transistor.

6, 15 and 24, another photosensitive layer 38 is provided and patterned. The patterning of the photosensitive layer 38 cooperates with the etch stop layer 16 to align the inner edge 40 as shown in FIG. Also, in particular, the line extending from the inner edge 40 is
6 intersects the etch stop layer 16 at a distance D from the outer edge 42, which distance D approximates the dimensions of the electrical contacts made to the channel layer 14. After patterning, the transistor stack 32 is etched to remove portions of the source layer 12, the channel layer 14, and the drain layer 18 at the second end 26. Reactive ionic etchants suitable for the oxide etch stop layer 16 should be selective for both oxide and photosensitizer (photoresist), for example, HBr or HCl.
+ Cl + O ₂ + N ₂ . As shown in FIGS. 6, 15, and 24, the portion of the drain layer 18 at the second end 26 that is not protected by the photosensitive layer 38 is completely removed. The etching is continued until the source layer 12 is exposed, but a part of the channel layer 14 protected by the etch stop layer 16 remains. After the etching, trapezoidal portions 41, 43, and 45 are formed to make contacts to the source layer 12, the channel layer 14, and the drain layer 18, respectively.

7, 16, 25, the photosensitive layer 38 is removed from the transistor stack 32 and insulating sidewall spacers 44, 46, 48, 50, 52 are formed over the exposed edges of the transistor stack 32. can do. In particular, sidewall spacers 44/52 are formed along the exposed edges of gate 34 / cap 36. Similarly, the side wall spacers 46, 48, and 50 form the drain layer 18, the channel layer 14, and the source layer 12, respectively.
Are formed along. Side wall spacers 44, 46, 4
8, 50, 52 can be composed of, for example, nitride formed by CVD followed by anisotropic etching. The use of nitride as the sidewall spacer material allows for a borderless contact structure, which provides the advantage of greater tolerances for placing contacts. However, if it is necessary to provide the active region with silicide to increase the conductivity of the diffusion region (eg, source layer 12 and drain layer 18) to the conductive contact to be formed (not shown), the sidewall spacer may be
It should be formed of a dielectric material rather than silicon nitride to prevent shorting between layers.

8, 17, and 26, the entire transistor stack 32 is encapsulated in a dielectric material 54, preferably silicon dioxide, and patterned. Openings 56, 58, 60, 62 for contact studs
Is etched into the encapsulating dielectric material 54. An opening 58 extends through both the encapsulation dielectric 54 and the passivation cap 28, exposing the drain layer 18 to allow contact. Opening 60
Extends through both the encapsulating dielectric material 54 and the etch stop layer 16, exposing the channel layer 14 to allow for direct contact (eg, body contact).

9, 18, and 27, the conductive contacts
Studs 57, 59, 61, 63 are formed by CVD of a conductive material, such as tungsten, as known in the art.

FIG. 28 shows a plan view of another preferred embodiment of the present invention, in which like reference numbers indicate like elements. The structure shown in FIG. 28 is formed by the steps described in the description of FIGS. 7, 16, 25 above (eg, immediately prior to encapsulation and formation of contact studs 57, 59, 61, 63). Can be. The transistor stack 132 shown in FIG.
5. Second end 26 of transistor stack 32 shown in FIG.
Contact end 126 similar to FIG.
And an active end 124 similar to the first end 24 shown in FIG. However, the active end 124 does not
6 and 25 feature a plurality of fingers 164, each similar to the first end of the transistor stack 32, which are connected at a contact end 126 for sharing contacts. The structure shown in FIG. 28 provides additional current carrying capacity in a high density layout. A typical vertical transistor made in accordance with the present invention can have a channel length of 1000 °, a mesa width W of 300 °, and a finger length of about 2000 ° for each of the four fingers.

Increasing the finger length F can further increase the current carrying capacity of the transistor stack 132, but with an undesirable increase in propagation delay. In another embodiment, providing an additional set of contacts by making structure 132 symmetric about line CC ′ shown in FIG.
Therefore, the finger length F can be effectively doubled without increasing the propagation delay. In addition, such technology
It can be applied to a single finger version of the invention, but is less space efficient.

The above description includes specific exemplary dimensions of the preferred embodiment. However, the present invention can be described more broadly by roughly estimating the relative relationships of critical dimensions. FIG. 29 shows a simplified representation of the multilayer finger transistor stack 232 to show critical dimensions. FIG.
_Has L _{eff, the} effective channel length, and the transistor
The overall height h of the stack 232 is shown. The effective channel length is determined by the thickness of the channel layer 214, and the height h is characterized by the total thickness of the source layer 212, the channel layer 214, and the drain layer 218.
Further, the mesa width W and the finger length F are displayed. Table 1 below shows the approximate preferred range of dimensions and / or the relationship between the indicated dimensions.

Table 1 500 ° ≦ L _eff ≦ 1000 ° 300 ° ≦ W ≦ 1500 ° 3W ≦ F ≦ 10W (Note: can be doubled as described above) h ≦ 10W

Various advantages over the prior art are provided by the invention described herein. Importantly, the present invention provides direct contact with the channel layer 14 (eg, body), ie, the floating contact of the SOI device.
There is provided a vertical transistor having an important feature for preventing a body effect. The present invention also provides a transistor capable of conducting more than twice the current of a single-gate planar transistor by increasing the current as the mesa width W decreases due to the channel depletion effect. L
_The short channel effect on _eff is suppressed as the mesa width W decreases and as the channel approaches full depletion. In addition, alignment problems commonly associated with double gate transistors are avoided by using wrap around gate 34.

Although the present invention has been particularly shown and described with reference to preferred embodiments, it will be appreciated by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention. it is obvious.

In summary, the following is disclosed regarding the configuration of the present invention. (1) a substrate, a source layer deposited on the substrate and having a first peripheral edge, and a second layer deposited on the source layer and having a thickness substantially defining a channel length of the transistor; A channel layer further having a peripheral edge; a drain layer deposited over the channel layer and having a third peripheral edge; and a first peripheral edge, the second peripheral portion deposited over the drain layer. An edge, an upper dielectric layer having a fourth peripheral edge substantially coinciding with the third peripheral edge, and surrounding the source layer, the channel layer, and a portion of the drain layer, the source layer, the channel layer, A vertical gate dielectric layer in contact with the first peripheral edge, the second peripheral edge, and the third peripheral edge of the drain layer, respectively; Vertical double gate field effect transistor, characterized in that it comprises a conductive gate that is in contact surrounds the body layer. (2) the source layer, the channel layer, and the drain layer substantially coincide with each other, and are characterized by a length and a width;
The double-gate field-effect transistor according to (1), wherein the length is much larger than the width. (3) The double-gate field-effect transistor according to (1), wherein the gate dielectric layer is made of an oxide. (4) The double-gate field effect of (1), wherein the gate dielectric layer has a significantly smaller capacitance adjacent to the source and drain layers than in the channel layer. Transistor. (5) The double-gate field effect transistor of (1), wherein the gate dielectric layer is much thicker adjacent to the source and drain layers than in the channel layer. (6) The double-gate field-effect transistor according to (1), wherein the conductive gate is selected from the group consisting of polysilicon and tungsten. (7) a gate contact connected to the conductive gate, a body contact connected to the channel layer,
The double contact according to (1), further comprising: a source contact connected to the source layer; and a drain contact connected to the drain layer.
Gate field effect transistor. (8) the body contact, the source contact,
The drain contact is formed at a first end of the transistor, and a second end of the transistor corresponding to a portion of the source layer, the channel layer, and the drain layer, which contacts the conductive gate, The double finger according to the above (7), which has a plurality of fingers.
Gate field effect transistor. (9) The double-gate field effect transistor according to (7), wherein the transistor operates in a fully depleted mode. (10) providing a semiconductor substrate, forming a source layer having a first peripheral edge on the semiconductor substrate, and forming a channel layer having a second peripheral edge on the source layer Etching one end of the channel layer over a portion of the channel layer.
Forming a stop layer; forming a drain layer having a third peripheral edge on the channel layer and the etch stop layer; forming a first dielectric layer on the drain layer Forming a gate dielectric and a conformal conductive gate along a portion of the first peripheral edge, the second peripheral edge, and a portion of the third peripheral edge to form the etch stop layer. Forming an insulated transistor stack having a first end having a first dielectric end and a second end having the gate dielectric and the conformal conductive gate; and forming a conformal dielectric over the conformal conductive gate. Forming a body layer; and exposing the etch stop layer at a second end of the isolated transistor stack. A part of the drain layer is removed, a part of the source layer and the channel layer not protected by the etch stop layer is removed, and a contact platform is provided on each of the source layer, the channel layer, and the drain layer. Forming a sidewall, forming sidewall spacers along side surfaces of the contact platform, each of the contact platforms of the source layer, the channel layer, and the drain layer; and the conductive gate. Forming a vertical conductive contact connected to the transistor and a vertical double gate field effect transistor. (11) The method according to (10), wherein the channel layer is formed by low-temperature epitaxy. (12) The gate dielectric layer is thermally grown, and the dopant concentration of the source layer, the channel layer, and the drain layer is adjusted so as to utilize a change in an oxidation rate due to a dopant concentration when the gate dielectric is grown. The method according to (10), wherein the method is selected. (13) The semiconductor device according to (1), wherein the semiconductor substrate comprises a silicon-on-insulator wafer.
The method according to 0). (14) The method according to (10), wherein the drain layer is formed by a chemical vapor deposition method. (15) The method according to (10), wherein the conductive gate is selected from the group consisting of polysilicon and tungsten. (16) The method according to the above (10), wherein the etch stop layer comprises an oxide, and the removing step comprises a reactive ion etching with HBr. (17) The method according to the above (10), wherein the etch stop layer is made of an oxide, and the step of removing is made of reactive ion etching with HCl + Cl + O ₂ + N ₂ . (18) The method according to the above (10), wherein the side wall spacer is made of a dielectric material. (19) The method according to the above (10), wherein the side wall spacer is made of nitride.

[Brief description of the drawings]

FIG. 1 illustrates the manufacturing steps in a preferred embodiment of the method of the present invention for forming a vertical double gate field effect transistor.

FIG. 2 illustrates the manufacturing steps in a preferred embodiment of the method of the present invention for forming a vertical double gate field effect transistor.

FIG. 3 illustrates the fabrication steps of a preferred embodiment of the method of the present invention for forming a vertical double gate field effect transistor.

FIG. 4 illustrates the manufacturing steps of a preferred embodiment of the method of the present invention for forming a vertical double gate field effect transistor.

FIG. 5 illustrates the manufacturing steps in a preferred embodiment of the method of the present invention for forming a vertical double gate field effect transistor.

FIG. 6 illustrates the fabrication steps in a preferred embodiment of the method of the present invention for forming a vertical double gate field effect transistor.

FIG. 7 illustrates the manufacturing steps in a preferred embodiment of the method of the present invention for forming a vertical double gate field effect transistor.

FIG. 8 illustrates the manufacturing steps in a preferred embodiment of the method of the present invention for forming a vertical double gate field effect transistor.

FIG. 9 illustrates the manufacturing steps in a preferred embodiment of the method of the present invention for forming a vertical double gate field effect transistor.

FIG. 10 is a diagram showing a manufacturing step in a preferred embodiment of the method of the present invention as a sectional view taken along the line AA ′ of FIG. 1;
This corresponds to FIG. 1 and FIG.

FIG. 11 is a view showing a manufacturing step in a preferred embodiment of the method of the present invention as an AA ′ cross-sectional view, and corresponds to FIGS. 2 and 20;

FIG. 12 is a sectional view showing a manufacturing step in a preferred embodiment of the method of the present invention taken along the line AA ′, and corresponds to FIGS. 3 and 21;

FIG. 13 is a view showing a manufacturing step in a preferred embodiment of the method of the present invention as an AA ′ cross-sectional view, corresponding to FIGS. 4 and 22;

FIG. 14 is a sectional view taken along line AA ′ of a manufacturing step in a preferred embodiment of the method of the present invention, and corresponds to FIGS. 5 and 23.

FIG. 15 is a sectional view taken along line AA ′ of a manufacturing step in a preferred embodiment of the method of the present invention, and corresponds to FIGS. 6 and 24.

FIG. 16 is a sectional view taken along line AA ′ of a manufacturing step in a preferred embodiment of the method of the present invention, and corresponds to FIGS. 7 and 25.

FIG. 17 is a sectional view showing a manufacturing step in the preferred embodiment of the method of the present invention, taken along the line AA ′, corresponding to FIGS. 8 and 26;

FIG. 18 is a cross-sectional view taken along line AA ′ of a manufacturing step in a preferred embodiment of the method of the present invention, and corresponds to FIGS. 9 and 27.

FIG. 19 is a view showing a manufacturing step in a preferred embodiment of the method of the present invention as a BB ′ cross-sectional view of FIG. 1;
This corresponds to FIG. 1 and FIG.

FIG. 20 is a view showing a manufacturing step in a preferred embodiment of the method of the present invention as a BB ′ sectional view, corresponding to FIGS. 2 and 11;

FIG. 21 is a view showing a manufacturing step in a preferred embodiment of the method of the present invention as a BB ′ cross-sectional view, corresponding to FIGS. 3 and 12;

FIG. 22 is a view showing a manufacturing step in a preferred embodiment of the method of the present invention as a BB ′ cross-sectional view, corresponding to FIGS. 4 and 13;

FIG. 23 is a view showing a manufacturing step in a preferred embodiment of the method of the present invention as a BB ′ cross-sectional view, corresponding to FIGS. 5 and 14;

FIG. 24 is a view showing a manufacturing step in a preferred embodiment of the method of the present invention as a BB ′ cross-sectional view, corresponding to FIGS. 6 and 15;

FIG. 25 is a view showing a manufacturing step in a preferred embodiment of the method of the present invention as a BB ′ cross-sectional view, corresponding to FIGS. 7 and 16;

FIG. 26 is a view showing a manufacturing step in a preferred embodiment of the method of the present invention as a BB ′ cross-sectional view, corresponding to FIGS. 8 and 17;

FIG. 27 is a view showing a manufacturing step in a preferred embodiment of the method of the present invention as a BB ′ cross-sectional view, corresponding to FIGS. 9 and 18;

FIG. 28 is a plan view of another preferred embodiment of the present invention.

FIG. 29 is a simplified partial perspective view of the structure shown in FIG. 28.

FIG. 30 is a graph showing threshold voltage as a function of channel layer doping and mesa width W.

[Explanation of symbols]

Reference Signs List 10 (semiconductor) substrate 12 (n-type) source layer 14 (p-type) channel layer 16 etch stop layer 18 drain layer 24 first end 26 second end 28 passivation cap 30 vertical gate oxide 32 transistor Stack 34 (conformal) gate 36 (gate) cap 38 photosensitive layer 40 inner edge 41, 43, 45 trapezoidal portion 42 outer edge 44, 46, 48, 50 side wall spacer 54 dielectric material 56, 58, 60, 62 opening 57, 59, 61, 63 Contact stud 124 Active end 126 Contact end 132 Transistor stack 164 Finger 212 Source layer 214 Channel layer 218 Drain layer 232 Multi-layer finger transistor stack h Overall height L _eff Effective channel length W Me Width D Distance

──────────────────────────────────────────────────の Continuing the front page (72) Inventor Lewis Lou-Cheng Sue United States 12524 Fishkill Cross-By Court 7 New York, USA (72) Inventor Jack Alan Mandelman United States 12582 Stormville Jammy Lane, New York 5 ( 72) Inventor Ewan-Cheng Sun United States 10536 Kutnaanne Chambers Lane 29, New York 29 (72) Inventor Euan Tauer United States 10506 Bedford Finch Lane, New York 11 (56) References JP-A-6-61493 ( JP, A) JP-A-7-202216 (JP, A) JP-A-62-33472 (JP, A) JP-A-50-19379 (JP, A) JP-A-2-188966 (JP, A A) JP-A-5-198817 (JP, A) JP-A-2-2833 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336 H01L 21 / 8238 H01L 27/092

Claims (10)

(57) [Claims] A step of providing a semiconductor substrate; a step of forming a source layer on the semiconductor substrate; a step of forming a channel layer on the source layer; and the channel near one end of the channel layer. Part of layer
Forming an etch stop layer on top of the channel layer and the etch stop layer;
Forming a drain layer; and forming an upper dielectric layer on the drain layer.
When,At least the source layer, the channel layer, and the drain
By patterning the etching layer,
Around the other end opposite to the one end where the top layer is formed.
Switches forming a transistor stack having side edges.
Tep, Formed at the other end of the transistor stack
The peripheral edge Along the part of the gate dielectricTo form
furtherThe gate dielectricUpandOn the other end side
Part on the dielectric layerConformal conductive gateFormation
Steps to  On top of said conformal conductive gate,
Forming a dielectric layer; and exposing the insulating stop layer to expose the etch stop layer.
Of the transistor stackSaid oneThe dray at the end
A part of the etching layer, and the etching stop layer
The unprotected channel layer and the source layer
A part is removed to remove the source layer, the channel layer,
Forming a contact trapezoid on each of the drain layers
Forming sidewall spacers along the sides of the contact pedestal.
Forming the source layer, the channel layer, and the drain layer.
Each of the contact trapezoids,ConformalConductive gate
To form a vertical conductive contact connected to the
And a vertical gate field effect transistor, comprising:
How to form a star. The method according to claim 2, wherein the channel layer, and forming by cold epitaxy method of claim 1. 3. The method of claim 2, wherein the gate dielectric is thermally grown, and the dopant concentration of the source layer, the channel layer, and the drain layer is adjusted to take advantage of a change in an oxidation rate depending on a dopant concentration when the gate dielectric is grown. 2. The method according to claim 1 , wherein is selected. 4. The semiconductor substrate according to claim 1, wherein said semiconductor substrate comprises a silicon-on-insulator wafer.
2. The method according to 1 . The method according to claim 5, wherein said drain layer, and forming by chemical vapor deposition method according to claim 1. Wherein said conformal conductive gate, and selecting from the group consisting of polysilicon and tungsten, The method of claim 1. 7. made from said etch stop layer is an oxide, said step of removing is characterized by comprising the reactive ion etching with HBr, The method of claim 1. 8. The method according to claim 1, wherein said etch stop layer comprises an oxide and said removing step comprises HCl + Cl + O ₂ + N _2.
The method of claim 1 , comprising reactive ion etching. Wherein said sidewall spacers, characterized in that it consists of a dielectric material, The method of claim 1. Wherein said sidewall spacers, characterized in that a nitride The method of claim 1.