Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
  • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/01—Manufacture or treatment
  • H10D10/051—Manufacture or treatment of vertical BJTs
  • H10D10/054—Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/40—Vertical BJTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/63—Vertical IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0195—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including vertical IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

• a present invention described herein relates generally to a process for fabricating an integrated circuit structure, and more specifically to electronic devices having semiconductor junctions and to a process for their manufacture.
• limit-of- resolution, level-to-level alignment, and depth-of-focus are physically constrained parameters.
• Typical photolithographic techniques are limited by physical constraints of the photolithographic system involving actinic radiation wavelength, ⁇ , and geometrical configurations of the projection system optics. According to Rayleigh's criterion,
• DUV deep ultraviolet illumination
• NA NA 0.7
• the lower limit of resolution is 168 nanometers (1680 A) .
• Techniques such as phase-shifted masks can extend this limit downward, but photomasks required in this technique are extremely expensive. This expense becomes greatly compounded with a realization that an advanced semiconductor process may employ more than 25 photomasks.
• U.S. Patent No. 6,413,802 to Hu et al . describes a device fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin.
• U.S. Patent No. 6,525,403, to Inaba et al . describes a process with a gate, source, and drain in a modified horizontal configuration.
• a potential overetch produces a damaged region in the silicon and may result in excessive consumption of silicon underlying a contact. Further, formation of an oxide spacer without an etch stop presents manufacturing difficulties as timing and other recipe tolerances become overly stringent . For at least the aforementioned reasons, integrated circuit manufacturers have been unable to sufficiently reduce a size of electronic devices while still maintaining high performance.
• the aforementioned art has limitations on either device performance or anufacturability due to structures use (e.g., SOI or SIMOX) , limitations due to required lithography steps, or requirements for gate oxides to be performed late in a process, thereby limiting flexibility in design.
• CMOS transistor Formation of elements of a vertical transistor is described, particularly, a gate-source-drain arrangement of a CMOS transistor. Improved methods for vertical transistor formation, which are not limited by constraints of photolithography due to a novel use of spacers and self-aligning techniques, have great utility and importance. Those of skill in the art will appreciate that the techniques described herein may be used to fabricate other types of devices as well . For example, junctions of a bipolar transistor (as well as other device junction types) may be fabricated using the methods described herein.
• a method of fabricating an electronic device includes implanting a dopant into an area of a semiconducting substrate where the area is located within a region isolated by a dielectric isolator.
• a film stack is then deposited over the implanted and dielectric separator areas .
• the film stack includes, inter alia, a first dielectric layer and a first polysilicon layer.
• a dielectric window is then etched through the first dielectric layer and a second dielectric layer is deposited into the dielectric window and over the film stack.
• the second dielectric layer is etched anisotropically to form a first spacer. The spacer is used to reduce the size of transistor features well below the limits of photolithography.
• Portions of the film stack lying between the implanted area and the first dielectric layer are then anisotropically etched to form an epitaxial via.
• the via is filled with epitaxial silicon, thereby forming an epitaxial channel.
• a second polysilicon layer is formed over the epitaxial channel and a third dielectric layer is deposited over the second polysilicon layer and surrounding areas.
• the third dielectric layer is consequently etched anisotropically to form a second spacer and the first polysilicon layer is anisotropically etched.
• a fourth dielectric layer is deposited over the second polysilicon layer and the first polysilicon layer and the fourth dielectric layer is etched to form a third spacer.
• a semiconductor substrate having thereon at least one dopant-implanted region laterally enclosed by a dielectric isolation region. A topmost surface of the dielectric isolation region and the implanted region are substantially coplanar with a principal surface of the substrate.
• An epitaxial channel is disposed on the topmost surface of the implanted region and is electrically coupled to the implanted region. A periphery of the epitaxial channel is defined by a first dielectric spacer.
• a polysilicon region is peripherally disposed to and surrounds the epitaxial channel . The polysilicon region at least partially overlays the implanted region and is isolated from direct electrical coupling with the implanted region by a dielectric layer.
• FIG. 1 shows an exemplary embodiment of an isolated implant area used to create an electronic device structure of the present invention.
• FIG. 2 is a schematic cross-sectional view of the isolated implant area of FIG. 1 with a film stack.
• FIG. 3 shows the deposited films of FIG. 1 with an etched dielectric mask window.
• FIG. 4 shows a conformal blanket deposition of a dielectric layer filling the mask window of FIG. 3.
• FIG. 5 shows the conformal blanket deposition of FIG. 4 anisotropically etched, forming a dielectric spacer.
• FIG. 6 shows an anisotropic etch of film layers down to the implant area through the window formed by the dielectric spacer of FIG. 5.
• FIG. 7 shows the removal of overlying dielectric layers of FIG. 6 with a vertical sidewall gate oxidation.
• FIG. 8 shows an epitaxial channel fill of a gate area formed on FIGS. 6 and 7.
• FIG. 9 shows the epitaxial fill area of FIG. 8 after chemical-mechanical planarization of the epitaxial silicon and deposition of polysilicon and photoresist.
• FIG. 10 shows the photoresist layer of FIG. 9 after development and etch.
• FIG. 11 shows an etched polysilicon layer of FIG. 10, which will become a gate area of the electronic device .
• FIG. 12 shows the etched polysilicon layer of FIG. 11 with an etched underlying nitride layer, further defining the gate area.
• FIG. 13 shows a conformal dielectric blanket layer deposited over the gate area of FIG. 12.
• FIG. 14 shows the dielectric blanket layer of FIG. 13 after an anisotropic etch, leaving an oxide spacer.
• FIG. 15 shows a developed and etched photoresist layer over the gate area of FIG. 14.
• FIG. 16 shows an etched drain area formation remaining after polysilicon etch and removal of the photoresist layer of FIG. 15.
• FIG. 17 shows a conformal dielectric blanket layer over the gate and drain areas of FIG. 16.
• FIG. 18 shows the dielectric blanket layer of FIG. 17 after an anisotropic etch and leaving an oxide spacer surrounding the drain area .
• FIG. 19 shows the electronic device structure of FIG. 18 after significant back-end-of-line processing steps associated with the present invention are completed.
• FIG. 1 shows an exemplary embodiment of an isolated implant area 105 used to create an electronic device structure of the present invention.
• FIG. 1 includes a base substrate 101, an isolation dielectric area 103, and the implanted substrate area 105.
• An extent 107 of the implanted area 105 is shown in a plan view at the top of FIG. 1. All areas are formed by processes well-known to one of skill in the art.
• the base substrate 101 is frequently a silicon wafer. In this embodiment, the specific silicon wafer is doped within the confines of the isolation dielectric area to form the implant area 105.
• FIG. 2 is a schematic cross-sectional view of the isolated implant area 105 of FIG. 1 with an overlying film stack.
• the film stack includes a pad oxide 201, a first polysilicon layer 203, a nitride layer 205, a dielectric hard mask 207, and a photoresist layer 209.
• the dielectric hard mask 207 may be, for example, a CVD-deposited oxide.
• nominal film thicknesses and methods of deposit are provided as follows: the pad oxide 201 is a deposited 500 A - 1000 A oxide, the first polysilicon layer 203 is 1000 A thick, the nitride layer 205 is 300 A thick, the dielectric (e.g., oxide) layer 207 is 2000 A - 3000 A thick, and the photoresist layer 209 is 0.5 ⁇ m - 1.5 ⁇ m thick.
• FIG. 3 shows the deposited films of FIG. 1, after exposing the photoresist layer 209, developing, and etching through the photoresist layer 209 and underlying hard mask 207, and producing a mask window 301.
• Etching through the hard mask 207 may be accomplished through various wet etch (e.g., in hydrofluoric acid, such as contained in a standard buffered oxide etch, or orthophosphoric acid) or dry etch (e.g., reactive-ion etch (RIE) ) techniques.
• RIE reactive-ion etch
• the photoresist layer 209 is stripped.
• a plan view at the top of FIG. 3 shows a limit 303 to conventional lithography.
• the limit 303 with contemporary lithography is 0.18 ⁇ m.
• a conformal blanket deposition of an oxide spacer layer 401 fills the mask window 301 and overlies the surrounding hard mask 207.
• the oxide spacer layer 401 is then anisotropically etched, for example, by RIE.
• An etchant is chosen with a high selectivity ratio between oxide and nitride allowing the nitride layer 205 to act as an etch stop.
• the remaining oxide spacer 501 (FIG. 5) , substantially extends the limit 303 of conventional lithography as shown by a reduced-dimension mask opening 503. For example, a typical 0.18 ⁇ m design rule with an oxide spacer 501 thickness of 0. ; 05 ⁇ m at the base produces a 0.08 ⁇ m mask opening 503.
• the oxide spacer 501 along with the hard mask 207, provide an mask for anisotropic etching through the underlying layers (i.e., the nitride layer 205, the first polysilicon layer 203, and the pad oxide 201) , and down to the implanted area 105, thereby producing an epitaxial ("epi") via 601.
• the overlying hard mask 207 and oxide spacer 501 are stripped by, for example, a buffered-oxide wet-etch technique.
• a thermal oxidation step produces a gate oxide 701 on vertical walls of the first polysilicon layer 203.
• any oxide regrowth on the bottom of the bottom of the epi via 601 may be remove by techniques such as RIE. Precautions are taken to minimize or eliminate any native oxide growth on the bottom of the epi via 601 after etch. Techniques to minimize native oxide growth from silicon are well known in the art and will not be discussed herein.
• Thermal oxide growth techniques combine oxygen with underlying silicon (i.e., the first polycrystalline silicon layer 103) . Mechanisms for thermal oxide growth are well understood with approximately 44% of the underlying polysilicon 103 being consumed to form the gate oxide 701.
• the epi via 601 is then filled (FIG. 8) with an epitaxial silicon 801 channel deposition.
• the epitaxial silicon forms a channel of the transistor, channel 901 (FIG. 9) .
• a second polysilicon layer 903 and a second photoresist layer 905 are then deposited.
• the second polysilicon layer 903 and the second photoresist layer are nominally 1000 A and 5000 A thick, respectively.
• the second photoresist layer 905 is then exposed, developed, and etched leaving a second photoresist etch mask 1005 (FIG. 10) . Areas of the first polysilicon not under the second photoresist etch mask 1005 layer 203 are then etched, for example, by RIE, leaving a gate polysilicon 1103 (FIG. 11) .
• a conformal oxide layer 1301 is deposited (e.g., by an LPCVD process) over the gate polysilicon and surrounding area, and is then anisotropically etched, leaving an oxide spacer 1401 (FIG. 14) .
• the oxide spacer provides for a self-aligning area that allows for overlay of features beyond what typical lithography and alignment techniques would ordinarily permit. Therefore, level -to-level alignment issues with multiple masks are eliminated as the levels are self-aligned.
• photoresist is deposited and etched leaving a photoresist mask 1501.
• the photoresist mask 1501 serves as an etch mask for a polysilicon etch producing a polysilicon gate area 1601 (FIG. 16) .
• a final CVD oxide is conformally deposited 1701 (FIG. 17) , and anisotropically etched, leaving a gate area oxide spacer 1801 (FIG. 18) .
• the gate area oxide spacer has the same self-aligning qualities as the oxide spacer
• a final anisotropic etch reveals the implanted substrate area 105 and forms a source region 1901, a drain region 1903, and a gate region 1905.
• techniques well known to a skilled artisan are completed to form, for example, additional implants diffused into the drain polysilicon, metallization, electronic-test, and packaging steps to complete the semiconductor device.
• a process and arrangement for forming a vertical gate CMOS device has been discussed herein. However, the invented process and arrangements of layers and regions described herein are also useful for forming a wide range of other device types and structures having utility as individual devices or in combinations.
• CMOS complementary metal-oxide-semiconductor
• CMOS complementary metal-oxide-semiconductor
• the techniques described herein are also readily amenable to constructing features such as double gates by expanding the gate-masking step with a separation of gate areas by dielectric deposition or growth.
• a thin-film head (TFH) process in the data storage industry or an active matrix liquid crystal display (AMLCD) in the flat panel display industry could readily make use of the processes and techniques described herein.
• THF thin-film head
• AMLCD active matrix liquid crystal display
• semiconductor should be recognized as including the aforementioned and related industries.

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• 2005
  • 2005-01-18 EP EP05705754A patent/EP1709680A4/en not_active Withdrawn
  • 2005-01-18 WO PCT/US2005/001313 patent/WO2005072154A2/en not_active Ceased
  • 2005-01-18 CN CNB2005800029189A patent/CN100442477C/en not_active Expired - Fee Related
  • 2005-01-21 TW TW094101806A patent/TW200531215A/en unknown

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