TW200531215A - Vertical gate cmos with lithography-independent gate length - Google Patents

Abstract

Formation of elements of a vertical transistor is described, particularly, a gate-source-drain arrangement of a CMOS transistor. Vertical transistors are used frequently in the integrated circuit art. Accordingly, improved methods for their formation, which are not limited by constraints of photolithography, have great utility and importance. Those of skill in the art will appreciate that the techniques described may be used to fabricate other types of devices as well. For example, junctions of a bipolar transistor (as well as other device junction types) may be fabricated using the methods described herein.

Description

200531215 IX. Description of the invention: [Technical field to which the invention belongs] The invention described herein generally relates to a method for manufacturing an integrated circuit structure, and more particularly, to an electronic device having a semiconductor interface and its electronic device Production method. [Prior art]

In integrated circuit technology, smaller devices can be gradually obtained without sacrificing the performance of the devices. This small device size requires small device areas, precise alignment between areas, and minimization of parasitic resistance and capacitance. Device size can be reduced by relying more on fine-line lithography. However, as shown below, it has become impractical or impossible to continue to reduce feature size and achieve significant improvements in alignment accuracy. Because lithography has reached its physical limit, yields and throughput will decrease. The four control performance parameters of the lithography technology are the limitation of resolution, the accuracy of layer-to-layer alignment, the depth of focus and the throughput. For discussion purposes, the limitations of resolution, layer-to-layer alignment accuracy, and depth of focus are practically limited parameters. Typical lithography technology is limited by the physical limitations of the lithography system (including: the wavelength of actinic radiation λ and the geometry of the optics of the projection system. According to the Rayleigh ’s criterion:

r 0.6UL · =; ΝΑ where yiM is the numerical aperture of the optical system and is defined as yiM = 77 si η α, where the refractive index of the medium through which 77 is a radiation (312XP / Invention Specification (Supplementary Pieces) / 94-05 / 94101806 200531215 usually refers to air, so / 7: 3 1), and 0: the divergent half-angle of actinic radiation. For example: use deep ultraviolet lighting (D U V) with; I = 193 nm and water / = 0.7, the lower limit of the resolution is 168 nanometers (168 A). Although techniques such as phase shift masks (p h a s e-s h i f t e d m a s k) can extend this limitation downwards, the masks required in this technique are quite expensive. This cost is greatly increased by the fact that advanced semiconductor systems may use more than 25 masks. As the feature size of the photomask decreases and the total number of photomasks increases, the second parameter (layer-to-layer alignment accuracy) plus the limitation of resolution becomes more important. Example # For example, if the mask alignment itself causes the device yield to be reduced to 95% per layer, the 25-layer mask becomes a total device yield of 0.9525 (0.28 or 28% yield) (assuming nothing about error). Therefore, this phase-shift mask is not only more expensive than the more complex mask, but it also obviously causes bad yield.

Furthermore, although the numerical aperture of the lithography system can be increased to reduce the limitation of resolution, the result is not conducive to the third parameter (the depth of focus). The depth of focus is inversely proportional. Therefore, when less / increased, the resolution limit will decrease, but the depth of focus will decrease more quickly. The reduction in focal depth makes precise focusing more difficult, especially on non-planar structures, such as the Manhattan Geometries, which are becoming increasingly popular in advanced semiconductor devices. Recently, technology has been developed to make smaller size transistors and related devices. One of the methods for manufacturing the transistor is described in the 1999 International Electronic Device Conference sponsored by IEEE named "Vertical Replacement Gate (VRG) M0SFET: It has nothing to do with lithography technology. "The 50nm vertical MOSFET with a gate length" is in the paper. Here, 6 312XP / Invention Specification (Supplement) / 94-05 / 94101806 200531215 JM Hergenrother et al. Describe a method using vertical transistor technology in which gates and gate oxides need to be applied in the final steps of the process O.H. et al. U.S. Patent No. 6,4 1,3,802 describes a device fabricated in a silicon layer on an insulating layer (eg, SI M 0 X) from which the device is made. Extend into wings. Furthermore, U.S. Patent No. 6,5 2,5,403, to Inaba et al. Describes a method for manufacturing gates, sources, and drains in a modified horizontal structure.

Zhibo Zhang's U.S. Patent_Applicant Publication No. 2 0 2/0 0 6 0 3 3 8 describes a vertical FET device by which source and drain regions are formed at individual ends of a vertical channel, and at the vertical channel An insulated gate is formed nearby. Other techniques have focused on vertical devices like the ones described above formed on a silicon-on-insulator (SOI). SOI and SI M 0 X have several disadvantages. These disadvantages include the poor performance of the memory device (because of the floating system of the device), the need for extreme lithography technology for one or more process steps, and the dramatic increase in price caused by the SO I material. Therefore, in the conventional method for manufacturing a bipolar device, a source window is directly formed without providing some means for stopping the layer for a while. A potential over-etch will create a damaged area in the silicon, causing excessive loss of silicon at a contact. Furthermore, when the tolerance of time and other conditions becomes excessively strict, the formation of an oxide spacer without the need for an etching stop layer may present manufacturing difficulties. 7 312XP / Invention Manual (Supplement) / 94-05 / 94101806

200531215 For at least the reasons mentioned above, integrated circuit manufacturers have not been able to reduce the size of electronic devices sufficiently while still maintaining high performance. In terms of device performance or manufacturing capabilities, there are restrictions on the use of structures due to structural use (for example, SI MOX), and restrictions on the required lithography steps or the requirement to form gate oxides in a short time, thus limiting the design. In view of the expectation that integrated circuits can have a higher number of devices, a smaller size, and a larger circuit performance, there is still a continuing need for a manufacturing facility without the need to help with impractical and expensive lithography techniques. Therefore, what is needed The invention provides a method and a structure for manufacturing an integrated circuit device. This structure for manufacturing an integrated circuit device has a device with a reduced size that is acceptable. [Summary of the Invention] The formation of a vertical transistor element is described, especially the gate-source-drain configuration of the transistor. The method of forming a vertical transistor is not controlled by the new use of spacers and self-alignment technology. This improvement method has great applicability and importance. Those skilled in the art will recognize that other devices can also be manufactured using the techniques described herein. For example, the methods described herein can be used to fabricate a bipolar interface (and other device interface types). In a specific example, a method for manufacturing an electronic device includes: implanting an area in a semiconductor substrate, the area being located in an area isolated by a dielectric layer. A film stack is then deposited in the implanted area and the dielectric area. The film stack particularly includes a first intermediary first polycrystalline layer. Then, the first dielectric layer is etched to form 312XP / Invention Specification (Supplement) / 94-05 / 94101806, while maintaining the above-mentioned technical SOI or post-step meter device required for the device. Improve the lithography-CMOS improvement The lithography technology of this type of transistor-a doped electrical isolation isolation layer and a dielectric layer 8 200531215

A window, and a second dielectric layer is deposited in the dielectric window and over the film stack. The second dielectric layer is anisotropically etched to form a first spacer. The spacer is used to properly reduce the size of the transistor features to less than the limit of lithography technology. Then, an anisotropic etching is performed on a portion of the film stack between the layout region and the first dielectric layer to form an epitaxial via hole (e p i 1: a X i a 1 v i a). The interstitial pores are filled with epitaxial stones to form an epitaxial channel. A second polycrystalline silicon layer is formed over the epitaxial channel, and a third dielectric layer is deposited over the second polycrystalline silicon layer and the surrounding area. Subsequently, the third dielectric layer is anisotropically etched to form a second spacer, and the first polycrystalline silicon layer is anisotropically etched. A fourth dielectric layer is deposited over the second polycrystalline silicon layer and the first polycrystalline silicon layer, and the fourth dielectric layer is etched to form a third spacer. Finally, any remaining layer surrounded by the third spacer is etched to a height substantially coplanar with the implanted area. The invention also defines an electronic device. In a specific example, a half of the conductive substrate is disclosed, which has at least one doped implanted region surrounded by a dielectric isolation region. The uppermost surfaces of the dielectric isolation region and the implanted region are substantially coplanar with the main surface of the substrate. An epitaxial channel is arranged on the uppermost surface of the implanted area and electrically connected to the implanted area. The periphery of the epitaxial channel is defined by a first dielectric spacer. A polycrystalline silicon region is arranged on the periphery to surround the epitaxial channel. The polycrystalline silicon region at least partially covers the implanted region and is isolated from the implanted region by a dielectric layer without direct electrical coupling. [Embodiment] 9 312XP / Invention Specification (Supplement) / 94-05 / 94101806 200531215 With reference to FIGS. 1 to 19, an exemplary embodiment of the present invention will be described in detail according to the following process steps. FIG. 1 shows an exemplary specific example of an isolation implantation area 105 for generating an electronic device structure of the present invention. FIG. 1 includes a base substrate 101, an isolation dielectric region 103, and the implant substrate region 105. The range 1 0 7 of the planting area 1 0 5 is shown in a plan view above FIG. 1. All zones are formed in a way well known to the artist. The base substrate 101 is often a silicon wafer. In this specific example, a specific silicon wafer is doped within the boundary of the isolation dielectric region to form the layout region 105. In another case, other Group IV element semiconductors or compound semiconductors (for example, Groups I I-V or I I_V I) may be selected as the base substrate 1 0 1. For example, the isolated dielectric region 103 is a deposited or thermally grown oxide or a deposited nitride.

Fig. 2 is a schematic cross-sectional view of the isolation implanted area 105 of Fig. 1 having a top film stack. In this example, the film stack includes a pad oxide 201, a first polycrystalline silicon layer 203, a nitride layer 205, a dielectric hard mask 207 and a photoresist. Layer 2 0 9. For example, the dielectric hard mask 207 can be a CVD deposited oxide. In a specific exemplary embodiment, the micro film thickness and deposition method are provided as follows: the pad oxide 2 1 is an oxide deposited with a thickness of 5 0 A-1 0 0 0 A, and the first polycrystalline The silicon layer is 2 0 3 series 1 0 0 0 A thick, the nitride layer 2 5 5 series 3 0 0 A thick, the dielectric (eg, oxide) layer 2 0 7 series 2 0 0 0 A-3 0 0 0 A is thick, and the photoresist layer 209 is 0.5 // m-1.5 # m thick. Figure 3 shows the hard mask 207 and the photoresist layer 209 under development, and after the photoresist layer 209 is exposed and developed, and after a mask window 301 is generated, Figure 10 312XP / Invention Specification (Supplement) ) / 94-05 / 94101806 200531215 Deposited film. Different wet etching (for example: hydrofluoric acid (hydr 0f 1 u ricacid) or orthophosphoric acid) contained in a standard buffer oxide etch or dry worm etch ( For example, reactive ionization (reactive-ion netch, RIE) technology is used to etch the hard mask 2 0 I. After the hard mask 2 7 is etched, the photoresist layer 2 0 9 is peeled off. The plan view above Fig. 3 shows the limitations of traditional lithography technology 3 0 3. For example: At that time, the limitation of lithography technology 3 3 was 0. 1 8 // m. Referring to Fig. 4, an oxide spacer layer 4 0 Conformal blanket overlying deposition filling of 1 # The mask window 3 0 1 and the surrounding hard mask 2 0 7. Then, the oxide spacer layer 4 0 1 is anisotropically etched by, for example, RIE. An etchant having a high selectivity between oxide and nitride to allow the nitride layer 205 to serve as an etch stop layer. As shown in a size reduction mask opening 5 0 3, the residual oxide spacer 5 0 1 ( Figure 5) The limitation of the traditional lithography technique is extended 3 0 3. For example: at this oxidation interval In the case where the bottom of the object 501 has a thickness of 0. 05 // m, a typical design rule of 0. 18 μm produces a 0. 8 # m curtain opening 5 0 3.

Referring to FIG. 6, the oxidized spacer 5 01 and the hard mask 2 0 7 provide an anisotropic etching of the underlying layers (ie, the nitrided layer 2 05, the first polycrystalline silicon layer). 2 0 3 and the pad oxide 2 0 1) to the implanted area 1 0 5 to generate a mask of an epitaxial (“epi”) via hole 601. In FIG. 7, the upper hard mask 207 and the oxidized spacers 501 are peeled off by, for example, a buffer oxide wet etching technique. A thermal oxidation step generates a gate oxide 7 01 on the vertical wall of the first polycrystalline silicon layer 2 0 3. Any oxide that grows on the bottom of the epitaxial interstitial hole 6 0 1 can be removed by RIE technology like 312XP / Invention Specification (Supplement) / 94-05 / 94101806 200531215 times (ie, in the Oxide on the planting area 105). After etching, precautions are taken to minimize or remove any native oxide (n a t i v e oxide) grown on the bottom of the epitaxial via hole 601. Techniques for minimizing native oxides grown from silicon are well known in the art and will not be discussed here. Thermal oxide growth technology combines oxygen with the underlying silicon (ie, the first polycrystalline silicon layer 2 0 3). It can be clearly understood that the thermal oxide growth mechanism consumes about 4 4% of the underlying polycrystalline silicon 2 0 3 to form the gate oxide 7 0 1.

Then, an epitaxial silicon 801 channel is deposited to fill the epitaxial via hole 601 (FIG. 8). The epitaxial silicon 8 0 1 forms a channel 9 0 1 of the transistor (FIG. 9). After that, a second polycrystalline silicon layer 903 and a second photoresist layer 905 are deposited. In a specific exemplary embodiment, the second polycrystalline silicon layer 903 and the second photoresist layer 905 have extremely small thicknesses of 100 A and 5000 A, respectively. The second photoresist layer 905 is exposed, developed, and etched to leave a second photoresist etch mask 1005 (FIG. 10). Then, the area of the first polycrystalline silicon 203 which is not under the second photoresist mask 105 is etched by, for example, R I E to leave a gate polycrystalline silicon 1 1 0 3 (FIG. 1 1). Subsequently, the gate region is completed by additional etching of the nitride layer 205 to leave a nitride pad 1250 (FIG. 12). Referring to FIG. 13 (eg, by an LPCVD process) a conformal oxide layer 1 3 0 1 is deposited over the gate polycrystalline silicon and the surrounding area, and then the conformal oxide layer is anisotropically etched 1 3 0 1 In order to leave the oxidative spacer 14 0 1 (Figure 1 4). The oxidized spacer provides a self-aligned area that allows coverage beyond the features typically permitted by typical lithography and alignment techniques. Therefore, when aligning these layers by yourself, the layer-to-layer alignment problem with multiple photomasks can be deleted. 12 312XP / Invention Specification (Supplement) / 94-05 / 94101806

200531215 questions. In addition, feature sizes are determined by deposition and etching techniques and by features defined only by lithography and alignment techniques. In FIG. 15, a photoresist is deposited and etched to leave a photoresist mask 1 E. The photoresist mask 1 50 is used as an etching mask for polysilicon etching for generating a polysilicon gate region (FIG. 1). 6). A CVD oxide 1701 (FIG. 17) is deposited in the actual shape and the CVD oxide is anisotropically etched to leave a gate region oxidation spacer 1 801 (FIG. 18). The gated spacer has the same self # quality as the previous oxidized spacer 1 4 0 1. In FIG. 19, a final anisotropic etching exposes the implanted base region 105 and forms a source region 1910, a drain region 1903 and a pole region 1905. After the last anisotropic etch, the technology of the artist is used to perform additional implantation, chemical, electronic test, and packaging steps such as diffusion to the drain polycrystalline silicon to complete the semiconductor device. To help understand the present invention, a process and configuration for forming a vertical CMOS device are discussed here. However, the layers and areas of the invention process and configuration described herein can also be used to form a variety of other types and structures with practicality to form individual devices or combinations. For example, although one example describes the formation of a CMOS device, those skilled in the art will understand that the present invention can be easily applied to a bipolar transistor or other types of semiconductor devices. Furthermore, the techniques described herein can also easily construct features such as double gates by dielectric deposition. In addition, many industries related to the semiconductor industry can use this technology such as: thin film magnetic heads in the data storage industry (thi η _ fi 1 mhead, 312XP / Invention Specification (Supplement) / 94-05 / 94101806 Far Small »01 ° 160 1 The last 1701 domain oxygen alignment plate is a gate known metal for the device in the gate domain can be physically installed or TFH) 13

200531215 or active matrix liquid crystal display in the panel display industry; the processes and technologies described herein can be easily used. The term "half_" is considered to include the above and related industries. In addition, although the manufacturing steps and techniques have been described and described, those skilled in the art will be able to use their methods that fall within the scope of the attached patent application. For example: Several techniques (such as chemical vapor deposition, vapor deposition, epitaxy, atomic layer deposition, etc.) are often used for layering. Although not all techniques are applicable to all membranes described here®, the technique is well known One can recognize that multiple methods for depositing layers and / or film types can also be used. Therefore, the scope of the present invention is limited to the scope of patents attached. [Simplified Description of the Drawings] Figure 1 shows a method for generating One of the inventions is an exemplary embodiment of the planting area of the electronic device structure. Fig. 2 is a diagram of the isolation planting area of Fig. 1 with a film stack. A dielectric layer overlying deposition to fill the mask window of FIG. 3 is shown. FIG. 5 shows a conformal blanket overlying deposition by anisotropic etching to form a dielectric spacer. Electricity The window etching film formed by the spacers is stacked to the implanted area. Fig. 7 shows the removal of the 312XP / Invention Specification (Supplement) / 94-05 / 94101806 I (AMLCD) conductor by a vertical sidewall gate oxidation. " The type of a film that can be recognized by its technology and plasma enhanced deposition should be specified in detail, and a given area should only be used to indicate the cross-sectional area of the film. The conformal blanket of Figure 4 is anisotropic, with the upper dielectric layer 14 200531215. FIG. 8 shows an epitaxial channel filling in the gate region formed in FIGS. 6 and 7. FIG. 9 shows the worm-crystal filled area of FIG. 8 after chemical mechanical planarization of the epitaxial silicon and deposition of polycrystalline silicon and photoresist. FIG. 10 shows the photoresist layer of FIG. 9 after development and etching. FIG. 11 shows the etched polycrystalline layer of FIG. 10, which will become a gate region of the electronic device.

Figure 12 shows the etched polysilicon layer of Figure 11 with an etched underlying nitride layer to further define the gate region. Figure 13 shows a conformal blanket overlying dielectric layer deposited over the gate region of Figure 12. FIG. 14 shows the blanket dielectric layer of FIG. 13 after anisotropic etching to leave an oxide spacer. Figure 15 shows a developed and etched photoresist over the gate region of Figure 14. FIG. 16 shows the formation of an etched drain region remaining after the polycrystalline stone lithography and the removal of the photoresist layer of FIG. 15. Figure 17 shows a conformal blanket overlying dielectric layer over the gate and drain regions of Figure 16. FIG. 18 shows the blanket dielectric layer of FIG. 17 after anisotropic etching and an oxide spacer surrounding the drain region is left. FIG. 19 shows the structure of the electronic device of FIG. 18 after completing the important subsequent process steps related to the present invention. 15 312XP / Invention Manual (Supplement) / 94-05 / 94101806 200531215 [Main components 1 01 Bottom 1 03 Isolation 1 05 Isolation 1 07 Range 201 Oxygen 203 First 205 Nitriding 207 Dielectric 209 Photoresistor 301 Cover 303 Limit 401 Oxidation 501 Residual 503 Size 601 Crystal 70 1 Gate 801 Crystal 901 Channel 903 Second 905 Second 1005 Second 1103 Gate 1205 Nitriding

No. Description] Substrate dielectric region, implantation of regionalized polycrystalline silicon layer, hard mask layer, window spacer, oxide spacer, reduction of mask opening, interlayer hole oxide, silicon polycrystalline silicon layer, photoresist layer, photoresist etching mask, polycrystalline cutting pad 312XP / Invention Specification (Supplement) / 94-05 / 94101806 16 200531215 130 1 Conformal oxide layer 140 1 Oxidation spacer 150 1 Photoresist mask 160 1 Polycrystalline silicon gate region 170 1 CVD oxide 180 1 Gate region oxidation interval Object 190 1 Source region 1903 Drain region • 1905 Gate region • 17 312XP / Invention Specification (Supplement) / 94-05 / 94101806

Claims (1)

200531215 10. Scope of patent application: 1. A method for manufacturing an electronic device, comprising: implanting a dopant into a region of a semiconductor substrate, the implanted region is located in a region isolated by a dielectric isolation layer; Depositing a film stack over the implanted and dielectric isolation layer region, the film stack including a first dielectric layer and a first polycrystalline silicon layer; etching a dielectric passing through the first dielectric layer A window; depositing a second dielectric layer into the dielectric window and above the film stack; Anisotropically etch the second dielectric layer to form a first spacer; anisotropically etch a portion of the film stack between the implanted region and the first dielectric layer to form an epitaxial dielectric hole; Filling the epitaxial via hole with epitaxial silicon to form an epitaxial channel; forming a second polycrystalline silicon layer over the epitaxial channel; depositing a third dielectric layer on the second polycrystalline silicon layer and Above the surrounding area; anisotropically etch the third dielectric layer to form a second spacer; etch the first polycrystalline silicon layer; deposit a fourth dielectric layer on the second polycrystalline silicon layer and the first Over a polycrystalline silicon layer; etching the fourth dielectric layer to form a third spacer; and etching any remaining layer surrounding the third spacer to approximately the height of the implanted region. 2. The manufacturing method according to item 1 of the patent application range, wherein the film stack includes a hafnium oxide, a first polycrystalline layer, a nitride layer, and an oxide mask. 18 312XP / Invention Specification (Supplement) /94-05/94101806.200531215-3. The manufacturing method according to item 1 of the patent application scope, wherein the spacer includes an oxide. 4. The manufacturing method of claim 1, wherein the first, second, third, and fourth dielectric layers include an oxide. 5. An electronic device comprising: a semiconductor substrate having at least one region surrounded by a dielectric isolation region laterally, the region is implanted with a dopant, the dielectric isolation region and the top of the implanted region are topmost The surface is substantially coplanar with an epitaxial channel of the main surface of the substrate, is disposed on the uppermost surface of the implanted region, and is electrically coupled to the implanted region. The periphery of the epitaxial channel is surrounded by a first dielectric spacer. Defined; and a polycrystalline silicon region disposed at the periphery to surround the epitaxial channel, the polycrystalline silicon region at least partially covers the implanted region and is isolated from the implanted region by a dielectric layer without direct electrical coupling . 6. For the electronic device under the scope of patent application No. 5, in which, when When a voltage exceeding a critical voltage is applied to the stupid channel, the stupid channel is electrically coupled to the surrounding polycrystalline silicon region. 7. The electronic device of claim 5 in which the epitaxial channel is electrically isolated from the surrounding polycrystalline silicon region when a voltage lower than a critical voltage is applied to the epitaxial channel. 8. The electronic device according to item 5 of the patent application, wherein the polycrystalline silicon region is surrounded by a second dielectric spacer. 9. The electronic device according to item 5 of the scope of patent application, further comprising 19 312XP / Invention Specification (Supplement) / 94-05 / 94101806 200531215 containing a polycrystalline silicon capping layer on the uppermost surface of the epitaxial channel. The capping layer is surrounded by a third dielectric spacer. 10. The electronic device according to item 9 of the scope of patent application, wherein the polycrystalline silicon capping layer is a gate contact of a transistor. 1 1. The electronic device according to item 5 of the patent application, wherein the polycrystalline silicon region is a drain contact of a transistor. 1 2. The electronic device according to item 5 of the scope of patent application, wherein the implanted area is a source contact of a transistor. 13. A method of manufacturing an electronic device, comprising: implanting a dopant into an area of a semiconductor substrate; depositing a film stack over the implanted area, the film stack including a first dielectric layer and a first A polycrystalline stone layer; etching a dielectric window through the first dielectric layer; forming a first spacer in the dielectric window; anisotropic etching in the implanted area and the first Part of the film stack between the dielectric layers to form a stupid interstitial hole; fill the stupid interstitial hole with stupid stone to form a wormhole channel and form a second polycrystalline silicon layer above the epitaxial channel Forming a second spacer surrounding the second polycrystalline silicon layer; engraving the first polycrystalline silicon layer; and forming a third spacer surrounding the first polycrystalline silicon layer. 14. The manufacturing method according to item 13 of the patent application scope, further comprising isolating the implanted area by a dielectric isolation layer. 15. The manufacturing method according to item 13 of the scope of patent application, wherein the first 20 312XP / Invention Specification (Supplement) / 9105/94101806 200531215 spacer is deposited on the dielectric by depositing a second dielectric layer Formed in the window and above the film stack, and then anisotropically etching the second dielectric layer. 16. The manufacturing method according to item 13 of the scope of patent application, wherein the second spacer is formed by depositing a third dielectric layer over the second polycrystalline silicon layer and the surrounding area, and anisotropic The third dielectric layer is formed by etching. 1 7. The manufacturing method according to item 13 of the scope of patent application, wherein the third spacer is formed by depositing a fourth dielectric layer on the second polycrystalline silicon layer and the first polycrystalline silicon layer, And anisotropically etching the fourth dielectric layer. 18. The manufacturing method according to item 17 of the scope of patent application, further comprising etching any remaining layer surrounding the third spacer to a height substantially equal to the implanted area. 21 312X? / Invention Specification (Supplement) / 94-05 / 94101806