EP1709680A4 - Cmos a grille verticale presentant une longueur de grille independante de la lithographie - Google Patents
Cmos a grille verticale presentant une longueur de grille independante de la lithographieInfo
- Publication number
- EP1709680A4 EP1709680A4 EP05705754A EP05705754A EP1709680A4 EP 1709680 A4 EP1709680 A4 EP 1709680A4 EP 05705754 A EP05705754 A EP 05705754A EP 05705754 A EP05705754 A EP 05705754A EP 1709680 A4 EP1709680 A4 EP 1709680A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- dielectric
- polysilicon
- spacer
- layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000001459 lithography Methods 0.000 title description 9
- 238000000034 method Methods 0.000 claims abstract description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 50
- 229920005591 polysilicon Polymers 0.000 claims description 49
- 125000006850 spacer group Chemical group 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 239000007943 implant Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 238000000206 photolithography Methods 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 17
- 239000010408 film Substances 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 230000008021 deposition Effects 0.000 description 7
- 230000007423 decrease Effects 0.000 description 4
- 230000005855 radiation Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 235000011007 phosphoric acid Nutrition 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
- H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Definitions
- a present invention described herein relates generally to a process for fabricating an integrated circuit structure, and more specifically to electronic devices having semiconductor junctions and to a process for their manufacture.
- limit-of- resolution, level-to-level alignment, and depth-of-focus are physically constrained parameters.
- Typical photolithographic techniques are limited by physical constraints of the photolithographic system involving actinic radiation wavelength, ⁇ , and geometrical configurations of the projection system optics. According to Rayleigh's criterion,
- DUV deep ultraviolet illumination
- NA NA 0.7
- the lower limit of resolution is 168 nanometers (1680 A) .
- Techniques such as phase-shifted masks can extend this limit downward, but photomasks required in this technique are extremely expensive. This expense becomes greatly compounded with a realization that an advanced semiconductor process may employ more than 25 photomasks.
- U.S. Patent No. 6,413,802 to Hu et al . describes a device fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin.
- U.S. Patent No. 6,525,403, to Inaba et al . describes a process with a gate, source, and drain in a modified horizontal configuration.
- a potential overetch produces a damaged region in the silicon and may result in excessive consumption of silicon underlying a contact. Further, formation of an oxide spacer without an etch stop presents manufacturing difficulties as timing and other recipe tolerances become overly stringent . For at least the aforementioned reasons, integrated circuit manufacturers have been unable to sufficiently reduce a size of electronic devices while still maintaining high performance.
- the aforementioned art has limitations on either device performance or anufacturability due to structures use (e.g., SOI or SIMOX) , limitations due to required lithography steps, or requirements for gate oxides to be performed late in a process, thereby limiting flexibility in design.
- CMOS transistor Formation of elements of a vertical transistor is described, particularly, a gate-source-drain arrangement of a CMOS transistor. Improved methods for vertical transistor formation, which are not limited by constraints of photolithography due to a novel use of spacers and self-aligning techniques, have great utility and importance. Those of skill in the art will appreciate that the techniques described herein may be used to fabricate other types of devices as well . For example, junctions of a bipolar transistor (as well as other device junction types) may be fabricated using the methods described herein.
- a method of fabricating an electronic device includes implanting a dopant into an area of a semiconducting substrate where the area is located within a region isolated by a dielectric isolator.
- a film stack is then deposited over the implanted and dielectric separator areas .
- the film stack includes, inter alia, a first dielectric layer and a first polysilicon layer.
- a dielectric window is then etched through the first dielectric layer and a second dielectric layer is deposited into the dielectric window and over the film stack.
- the second dielectric layer is etched anisotropically to form a first spacer. The spacer is used to reduce the size of transistor features well below the limits of photolithography.
- Portions of the film stack lying between the implanted area and the first dielectric layer are then anisotropically etched to form an epitaxial via.
- the via is filled with epitaxial silicon, thereby forming an epitaxial channel.
- a second polysilicon layer is formed over the epitaxial channel and a third dielectric layer is deposited over the second polysilicon layer and surrounding areas.
- the third dielectric layer is consequently etched anisotropically to form a second spacer and the first polysilicon layer is anisotropically etched.
- a fourth dielectric layer is deposited over the second polysilicon layer and the first polysilicon layer and the fourth dielectric layer is etched to form a third spacer.
- a semiconductor substrate having thereon at least one dopant-implanted region laterally enclosed by a dielectric isolation region. A topmost surface of the dielectric isolation region and the implanted region are substantially coplanar with a principal surface of the substrate.
- An epitaxial channel is disposed on the topmost surface of the implanted region and is electrically coupled to the implanted region. A periphery of the epitaxial channel is defined by a first dielectric spacer.
- a polysilicon region is peripherally disposed to and surrounds the epitaxial channel . The polysilicon region at least partially overlays the implanted region and is isolated from direct electrical coupling with the implanted region by a dielectric layer.
- FIG. 1 shows an exemplary embodiment of an isolated implant area used to create an electronic device structure of the present invention.
- FIG. 2 is a schematic cross-sectional view of the isolated implant area of FIG. 1 with a film stack.
- FIG. 3 shows the deposited films of FIG. 1 with an etched dielectric mask window.
- FIG. 4 shows a conformal blanket deposition of a dielectric layer filling the mask window of FIG. 3.
- FIG. 5 shows the conformal blanket deposition of FIG. 4 anisotropically etched, forming a dielectric spacer.
- FIG. 6 shows an anisotropic etch of film layers down to the implant area through the window formed by the dielectric spacer of FIG. 5.
- FIG. 7 shows the removal of overlying dielectric layers of FIG. 6 with a vertical sidewall gate oxidation.
- FIG. 8 shows an epitaxial channel fill of a gate area formed on FIGS. 6 and 7.
- FIG. 9 shows the epitaxial fill area of FIG. 8 after chemical-mechanical planarization of the epitaxial silicon and deposition of polysilicon and photoresist.
- FIG. 10 shows the photoresist layer of FIG. 9 after development and etch.
- FIG. 11 shows an etched polysilicon layer of FIG. 10, which will become a gate area of the electronic device .
- FIG. 12 shows the etched polysilicon layer of FIG. 11 with an etched underlying nitride layer, further defining the gate area.
- FIG. 13 shows a conformal dielectric blanket layer deposited over the gate area of FIG. 12.
- FIG. 14 shows the dielectric blanket layer of FIG. 13 after an anisotropic etch, leaving an oxide spacer.
- FIG. 15 shows a developed and etched photoresist layer over the gate area of FIG. 14.
- FIG. 16 shows an etched drain area formation remaining after polysilicon etch and removal of the photoresist layer of FIG. 15.
- FIG. 17 shows a conformal dielectric blanket layer over the gate and drain areas of FIG. 16.
- FIG. 18 shows the dielectric blanket layer of FIG. 17 after an anisotropic etch and leaving an oxide spacer surrounding the drain area .
- FIG. 19 shows the electronic device structure of FIG. 18 after significant back-end-of-line processing steps associated with the present invention are completed.
- FIG. 1 shows an exemplary embodiment of an isolated implant area 105 used to create an electronic device structure of the present invention.
- FIG. 1 includes a base substrate 101, an isolation dielectric area 103, and the implanted substrate area 105.
- An extent 107 of the implanted area 105 is shown in a plan view at the top of FIG. 1. All areas are formed by processes well-known to one of skill in the art.
- the base substrate 101 is frequently a silicon wafer. In this embodiment, the specific silicon wafer is doped within the confines of the isolation dielectric area to form the implant area 105.
- FIG. 2 is a schematic cross-sectional view of the isolated implant area 105 of FIG. 1 with an overlying film stack.
- the film stack includes a pad oxide 201, a first polysilicon layer 203, a nitride layer 205, a dielectric hard mask 207, and a photoresist layer 209.
- the dielectric hard mask 207 may be, for example, a CVD-deposited oxide.
- nominal film thicknesses and methods of deposit are provided as follows: the pad oxide 201 is a deposited 500 A - 1000 A oxide, the first polysilicon layer 203 is 1000 A thick, the nitride layer 205 is 300 A thick, the dielectric (e.g., oxide) layer 207 is 2000 A - 3000 A thick, and the photoresist layer 209 is 0.5 ⁇ m - 1.5 ⁇ m thick.
- FIG. 3 shows the deposited films of FIG. 1, after exposing the photoresist layer 209, developing, and etching through the photoresist layer 209 and underlying hard mask 207, and producing a mask window 301.
- Etching through the hard mask 207 may be accomplished through various wet etch (e.g., in hydrofluoric acid, such as contained in a standard buffered oxide etch, or orthophosphoric acid) or dry etch (e.g., reactive-ion etch (RIE) ) techniques.
- RIE reactive-ion etch
- the photoresist layer 209 is stripped.
- a plan view at the top of FIG. 3 shows a limit 303 to conventional lithography.
- the limit 303 with contemporary lithography is 0.18 ⁇ m.
- a conformal blanket deposition of an oxide spacer layer 401 fills the mask window 301 and overlies the surrounding hard mask 207.
- the oxide spacer layer 401 is then anisotropically etched, for example, by RIE.
- An etchant is chosen with a high selectivity ratio between oxide and nitride allowing the nitride layer 205 to act as an etch stop.
- the remaining oxide spacer 501 (FIG. 5) , substantially extends the limit 303 of conventional lithography as shown by a reduced-dimension mask opening 503. For example, a typical 0.18 ⁇ m design rule with an oxide spacer 501 thickness of 0. ; 05 ⁇ m at the base produces a 0.08 ⁇ m mask opening 503.
- the oxide spacer 501 along with the hard mask 207, provide an mask for anisotropic etching through the underlying layers (i.e., the nitride layer 205, the first polysilicon layer 203, and the pad oxide 201) , and down to the implanted area 105, thereby producing an epitaxial ("epi") via 601.
- the overlying hard mask 207 and oxide spacer 501 are stripped by, for example, a buffered-oxide wet-etch technique.
- a thermal oxidation step produces a gate oxide 701 on vertical walls of the first polysilicon layer 203.
- any oxide regrowth on the bottom of the bottom of the epi via 601 may be remove by techniques such as RIE. Precautions are taken to minimize or eliminate any native oxide growth on the bottom of the epi via 601 after etch. Techniques to minimize native oxide growth from silicon are well known in the art and will not be discussed herein.
- Thermal oxide growth techniques combine oxygen with underlying silicon (i.e., the first polycrystalline silicon layer 103) . Mechanisms for thermal oxide growth are well understood with approximately 44% of the underlying polysilicon 103 being consumed to form the gate oxide 701.
- the epi via 601 is then filled (FIG. 8) with an epitaxial silicon 801 channel deposition.
- the epitaxial silicon forms a channel of the transistor, channel 901 (FIG. 9) .
- a second polysilicon layer 903 and a second photoresist layer 905 are then deposited.
- the second polysilicon layer 903 and the second photoresist layer are nominally 1000 A and 5000 A thick, respectively.
- the second photoresist layer 905 is then exposed, developed, and etched leaving a second photoresist etch mask 1005 (FIG. 10) . Areas of the first polysilicon not under the second photoresist etch mask 1005 layer 203 are then etched, for example, by RIE, leaving a gate polysilicon 1103 (FIG. 11) .
- a conformal oxide layer 1301 is deposited (e.g., by an LPCVD process) over the gate polysilicon and surrounding area, and is then anisotropically etched, leaving an oxide spacer 1401 (FIG. 14) .
- the oxide spacer provides for a self-aligning area that allows for overlay of features beyond what typical lithography and alignment techniques would ordinarily permit. Therefore, level -to-level alignment issues with multiple masks are eliminated as the levels are self-aligned.
- photoresist is deposited and etched leaving a photoresist mask 1501.
- the photoresist mask 1501 serves as an etch mask for a polysilicon etch producing a polysilicon gate area 1601 (FIG. 16) .
- a final CVD oxide is conformally deposited 1701 (FIG. 17) , and anisotropically etched, leaving a gate area oxide spacer 1801 (FIG. 18) .
- the gate area oxide spacer has the same self-aligning qualities as the oxide spacer
- a final anisotropic etch reveals the implanted substrate area 105 and forms a source region 1901, a drain region 1903, and a gate region 1905.
- techniques well known to a skilled artisan are completed to form, for example, additional implants diffused into the drain polysilicon, metallization, electronic-test, and packaging steps to complete the semiconductor device.
- a process and arrangement for forming a vertical gate CMOS device has been discussed herein. However, the invented process and arrangements of layers and regions described herein are also useful for forming a wide range of other device types and structures having utility as individual devices or in combinations.
- CMOS complementary metal-oxide-semiconductor
- CMOS complementary metal-oxide-semiconductor
- the techniques described herein are also readily amenable to constructing features such as double gates by expanding the gate-masking step with a separation of gate areas by dielectric deposition or growth.
- a thin-film head (TFH) process in the data storage industry or an active matrix liquid crystal display (AMLCD) in the flat panel display industry could readily make use of the processes and techniques described herein.
- THF thin-film head
- AMLCD active matrix liquid crystal display
- semiconductor should be recognized as including the aforementioned and related industries.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
La présente invention concerne la formation d'éléments d'un transistor vertical, notamment d'une structure grille (1905) - source (1901) - drain (1903) d'un transistor CMOS. Les transistors verticaux sont couramment utilisés dans la technologie des circuits intégrés. Les procédés améliorés pour leur formation, qui ne sont pas limités par des contraintes de photolithographie, présentent par conséquent une grande utilité et une grande importance. Les techniques selon cette invention présentent l'avantage de pouvoir également être utilisées pour fabriquer d'autres types de dispositifs. Les procédés selon cette invention peuvent par exemple être mis en oeuvre pour fabriquer des jonctions d'un transistor bipolaire (ainsi que d'autres types de jonctions de dispositif).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/761,876 US6846709B1 (en) | 2003-10-06 | 2004-01-21 | Vertical gate CMOS with lithography-independent gate length |
PCT/US2005/001313 WO2005072154A2 (fr) | 2004-01-21 | 2005-01-18 | Cmos a grille verticale presentant une longueur de grille independante de la lithographie |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1709680A2 EP1709680A2 (fr) | 2006-10-11 |
EP1709680A4 true EP1709680A4 (fr) | 2008-07-02 |
Family
ID=34826456
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP05705754A Withdrawn EP1709680A4 (fr) | 2004-01-21 | 2005-01-18 | Cmos a grille verticale presentant une longueur de grille independante de la lithographie |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1709680A4 (fr) |
CN (1) | CN100442477C (fr) |
TW (1) | TW200531215A (fr) |
WO (1) | WO2005072154A2 (fr) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US5402002A (en) * | 1989-09-22 | 1995-03-28 | Siemens Aktiengesellschaft | Bipolar transistor with reduced base/collector capacitance |
US5599724A (en) * | 1992-05-21 | 1997-02-04 | Kabushiki Kaisha Toshiba | FET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same |
US20010017392A1 (en) * | 1997-05-19 | 2001-08-30 | International Business Machines Corporation. | Vertical transport MOSFETs and method for making the same |
US20020098657A1 (en) * | 1999-06-28 | 2002-07-25 | Mohsen Alavi | Structure and process flow for fabrication of dual gate floating body integrated MOS transistors |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5689127A (en) * | 1996-03-05 | 1997-11-18 | International Business Machines Corporation | Vertical double-gate field effect transistor |
US5786256A (en) * | 1996-07-19 | 1998-07-28 | Advanced Micro Devices, Inc. | Method of reducing MOS transistor gate beyond photolithographically patterned dimension |
US6040214A (en) * | 1998-02-19 | 2000-03-21 | International Business Machines Corporation | Method for making field effect transistors having sub-lithographic gates with vertical side walls |
US6518616B2 (en) * | 2001-04-18 | 2003-02-11 | International Business Machines Corporation | Vertical gate top engineering for improved GC and CB process windows |
US20030008515A1 (en) * | 2001-07-03 | 2003-01-09 | Tai-Ju Chen | Method of fabricating a vertical MOS transistor |
-
2005
- 2005-01-18 CN CNB2005800029189A patent/CN100442477C/zh not_active Expired - Fee Related
- 2005-01-18 EP EP05705754A patent/EP1709680A4/fr not_active Withdrawn
- 2005-01-18 WO PCT/US2005/001313 patent/WO2005072154A2/fr not_active Application Discontinuation
- 2005-01-21 TW TW94101806A patent/TW200531215A/zh unknown
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US5402002A (en) * | 1989-09-22 | 1995-03-28 | Siemens Aktiengesellschaft | Bipolar transistor with reduced base/collector capacitance |
US5599724A (en) * | 1992-05-21 | 1997-02-04 | Kabushiki Kaisha Toshiba | FET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same |
US20010017392A1 (en) * | 1997-05-19 | 2001-08-30 | International Business Machines Corporation. | Vertical transport MOSFETs and method for making the same |
US20020098657A1 (en) * | 1999-06-28 | 2002-07-25 | Mohsen Alavi | Structure and process flow for fabrication of dual gate floating body integrated MOS transistors |
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TW200531215A (en) | 2005-09-16 |
CN1910748A (zh) | 2007-02-07 |
WO2005072154A2 (fr) | 2005-08-11 |
WO2005072154A3 (fr) | 2005-12-08 |
CN100442477C (zh) | 2008-12-10 |
EP1709680A2 (fr) | 2006-10-11 |
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