US20050156224A1 - Method to make minimal spacing between floating gates in split gate flash - Google Patents
Method to make minimal spacing between floating gates in split gate flash Download PDFInfo
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- US20050156224A1 US20050156224A1 US11/059,987 US5998705A US2005156224A1 US 20050156224 A1 US20050156224 A1 US 20050156224A1 US 5998705 A US5998705 A US 5998705A US 2005156224 A1 US2005156224 A1 US 2005156224A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the invention relates to semiconductor memory devices, and, more particularly, to a method of forming a split gate flash memory with minimal floating gate-to-floating gate spacing.
- a split gate flash memory device is essentially a MOS transistor with a variable threshold voltage.
- the threshold voltage varies with the amount of charge that is stored on a floating gate structure.
- the floating gate structure overlies a first part of the device channel region.
- a control gate structure overlies a second part of the device channel region. Voltage on the control gate controls the second part of the device channel region directly and controls the first part of the device channel indirectly, as modulated by charge on the floating gate.
- the control gate is formed in close proximity to the floating gate so that a capacitive coupling between the control gate and the floating gate is achieved.
- Flash memories have undergone significant improvements over the years. In particular, device size has been dramatically reduced. Further reductions in the device size require technological innovations. In particular, the spacing between the floating gates of adjacent split gate flash cells is a significant problem.
- the floating gates are patterned, or defined, using a lithographic system. For example, after the deposition of a floating gate layer, the semiconductor wafer is then coated with a photoresist layer. The photoresist layer is exposed to actinic light through a mask. After development, a pattern of photoresist is left on the wafer overlying the floating gate layer. The floating gate layer is then etched where exposed by the patterned photoresist layer.
- a primary goal of the present invention is to provide a method to reduce cell-to-cell spacing without reducing reliability or yield and without significant complexity.
- U.S. Pat. No. 6,228,695 B1 to Hsieh et al teaches a method to form split gate flash cells with self-aligned sources and self-aligned floating gates. Spacer floating gates are formed on the sidewalls of the control gates.
- U.S. Pat. No. 5,915,178 to Chiang et al describes a split gate flash and a method of formation. An oxide layer is grown on the surface of the floating gate layer prior to etching the floating gate.
- U.S. Pat. No. 6,312,989 B1 to Hsieh et al shows a split gate flash device and a method of manufacture.
- U.S. Pat. No. 6,380,583 B1 to Hsieh et al teaches a split gate flash device and a method of formation. An oxide layer is grown over a floating gate layer to form a hard mask.
- a principal object of the present invention is to provide an effective and very manufacturable method to form a split gate flash memory.
- a further object of the present invention is to provide a method to form closely-spaced MOS gates.
- a yet further object of the present invention is to provide a method to form closely-spaced floating gates.
- a yet further object of the present invention is to provide a method to form closely-spaced floating gates with minimal process complexity.
- a yet further object of the present invention is to provide a method to form closely-spaced split gate flash cells.
- Another further object of the present invention is to provide a unique MOS gate structure.
- a method to form MOS gates in an integrated circuit device comprises providing a substrate.
- a dielectric layer is formed overlying the substrate.
- a conductor layer is formed overlying the dielectric layer.
- a first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer.
- a second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer.
- the conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.
- an integrated circuit device comprises a dielectric layer overlying a substrate.
- a patterned conductor layer overlies the dielectric layer.
- a patterned first masking layer overlies the conductor layer. Spacers are on the sidewalls of the patterned first masking layer and overlie the patterned conductor layer. The external edges of the patterned conductor layer and the spacers are aligned.
- FIG. 1 illustrates a top layout view of a partially completed split gate flash device array showing a preferred embodiment of the present invention.
- FIGS. 2-8 illustrate a first cross sectional view of the split gate flash device array showing a preferred embodiment of the present invention.
- FIGS. 9-17 illustrate a second cross sectional view of the split gate flash device array showing a preferred embodiment of the present invention.
- the preferred embodiments of the present invention disclose a method to form split gate flash memory. A method to form closely-spaced floating gates is described. A unique MOS gate device is illustrated. It should be clear to those experienced in the art that the present invention can be applied and extended without deviating from the scope of the present invention.
- FIG. 1 A top view of a partially completed split gate flash memory of the present invention is shown.
- a typical flash memory comprises a very large number, perhaps millions, of identical memory cells. The cells are arranged in a two-dimensional array to facilitate addressing, reading, and writing to specific cells in the array.
- a wafer substrate 10 is provided.
- the substrate may comprise any suitable semiconductor material or combination of materials.
- the substrate 10 comprises monocrystalline silicon.
- the substrate 10 is divided into two types of areas: active 10 and isolation 20 .
- the active areas (OD) 10 are simply areas of semiconductor.
- the isolation areas (STI) 20 are areas where a dielectric material has been formed.
- the isolation areas 20 may comprise any type of dielectric material and structure suitable for isolating adjacent active devices.
- the isolation areas 20 comprise shallow trench isolation (STI) that may be formed by well-known methods.
- STI regions 20 comprise trenches in the substrate 10 that are filled with a dielectric material such as silicon oxide.
- the memory array is laid out such that the STI regions 20 and active (OD) regions 10 are in parallel.
- Two cross sections “2” and “9” are analyzed in the description below.
- the “2” cross section bisects the parallel STI 20 and OD 10 regions and will illustrate the floating gate-to-floating gate spacing.
- the “2” cross section corresponds to FIGS. 2-8 below.
- the “9” cross section is parallel to the STI 20 and OD 10 regions and will illustrate adjacent split gate flash cells within an active region 10 .
- the “9” cross section corresponds to FIGS. 9-17 below.
- the substrate 10 is divided by a series of isolation regions 20 . Each isolation regions separates an active cell area in the substrate.
- FIG. 3 several layers are formed overlying the substrate 10 and isolation regions 20 .
- a first dielectric layer 24 is formed overlying the substrate 10 and isolation regions 20 .
- This first dielectric layer 24 is the floating gate dielectric.
- the first dielectric layer 24 may comprise any dielectric layer having suitable dielectric constant and breakdown capability.
- the first dielectric layer 24 comprises an oxide material. More preferably, the first dielectric layer 24 comprises silicon oxide that is thermally grown on the substrate 10 to a thickness of between about 80 Angstroms and about 110 Angstroms. For simplicity of illustration, the first dielectric layer 24 is only shown overlying the substrate 10 .
- a first conductor layer 28 is then grown overlying the first dielectric layer 24 .
- the first conductor layer 28 may comprise any conductive material, such as a metal, a semiconductor, or a combination of both, that can be used in the formation of a MOS gate.
- the first conductor layer 28 comprises a polysilicon layer that is deposited overlying the first dielectric layer 24 .
- the polysilicon layer 28 may be doped or undoped. More preferably, the polysilicon layer 28 is formed by chemical vapor deposition of polysilicon to a thickness of between about 500 Angstroms and about 1,200 Angstroms.
- a first masking layer 32 is then deposited overlying the first conductor layer 28 .
- the first masking layer 32 is a key feature of the present invention.
- the first masking layer 32 preferably comprises a material that can be selectively etched with respect to the first conductor layer 28 . More preferably, the first masking layer 32 comprises silicon nitride that is deposited by a chemical vapor deposition process. Most preferably, the first masking layer 32 is deposited to a thickness of between about 500 Angstroms and about 1,000 Angstroms.
- the first masking layer 32 is patterned.
- the first masking layer 32 is patterned using a lithographic process as shown.
- a first photoresist layer 36 is deposited overlying the first masking layer 32 .
- the first photoresist layer 36 is exposed to actinic light through a mask and then is developed.
- the patterned first photoresist layer 36 covers the first masking layer 32 as shown. It is important to note that the resulting patterned first photoresist layer 36 may exhibit misalignment 40 as is well-known in the art. Referring now to FIG.
- the first photoresist layer 36 pattern is transferred to the first masking layer 32 by etching through the first masking layer 32 where exposed by the first photoresist layer 36 .
- the resulting, patterned first masking layer 32 is shown. Note that spacings 42 between first masking layer 32 features be made relatively large compared to the final floating gate-to-floating gate spacings that are formed using the unique method as will be demonstrated below.
- a second masking layer 44 is deposited overlying the first masking layer 32 and the first conductor layer 28 .
- the second masking layer 44 preferably comprises another material that can be selectively etched with respect to the first conductor layer 28 . More preferably, the second masking layer 44 comprises silicon nitride that is deposited by chemical vapor deposition. Most preferably, the second masking layer 44 is deposited to a thickness of between about 600 Angstroms and about 1,200 Angstroms.
- the second masking layer 44 is etched back to form spacers 44 on the sidewalls of the first masking layer 32 .
- This etch back step preferably comprises a dry etch having an anisotropic etching characteristic.
- the spacers 44 create a combined first and second masking layer pattern 32 and 44 having substantially wider features and, therefore, substantially narrower spaces 47 .
- a combined masking pattern 32 and 44 is created that has a substantially narrower space 47 than could be reliably achieved by a lithography-only process.
- the spaces 47 are controlled by the thickness of the deposited second masking layer 44 and by the etching back process. It is also important to note that the external edges 48 of the spacers 44 are designed to overlap the edges of the isolation regions 20 such that the resulting gates do not exhibit leakage.
- the first conductor layer 28 is etched through where exposed by the first masking layer 32 and the spacers 44 .
- the floating gates 28 of the split gate flash device are thereby formed in the direction perpendicular to the active regions 10 as shown in FIG. 1 .
- the edges 48 of the floating gates 28 overlie the isolation regions 20 . Very narrow floating gate-to-floating gate spaces 49 are possible with a minimally complex process and without creating shorting or leakage problems.
- the method of the present invention is optimally suited for the formation of split gate flash transistors, it can be used to pattern any MOS transistor gate 28 .
- the resulting MOS gates 28 each comprise the first conductor layer 28 overlying the substrate 10 with the first dielectric layer 24 therebetween.
- the masking layer 32 and 44 is formed by a combination of a first masking layer 32 overlying the first conductor layer 28 and spacers 44 overlying the first conductor layer 28 . The external edges of the spacers 44 and the first conductor layer 28 are aligned.
- FIG. 9 further processing in the formation of a split gate flash memory is illustrated using the “9” cross section.
- the first masking layer 32 and the spacers 44 are completely removed from the wafer surface. Note that the first conductor layer 28 has not been defined in this direction of the array.
- FIGS. 9-17 Several steps are herein illustrated in FIGS. 9-17 to define the floating gates 28 in the active area direction, to define control gates, and to complete the memory device.
- a third masking layer 52 is deposited overlying the first conductor layer 28 .
- the third masking layer 52 again preferably comprises a material, such as silicon nitride, that can be selectively etched with respect to the first conductor layer 28 and, in addition, to silicon oxide layers used as dielectrics in the exemplary device. More preferably, the third masking layer 52 is deposited to a thickness of between about 3,000 Angstroms and about 4,500 Angstroms. The thickness of the third masking layer 52 largely determines the height of the final device as will be seen below.
- the third masking layer 52 is then patterned, preferably using lithography. A second photoresist layer 56 is deposited and patterned as shown.
- the third masking layer 52 is etched through to create openings 59 . Note that an additional etch may be performed to create an optimal topography on the first conductor layer 28 as shown. In particular, by over-etching into the first conductor layer 28 , sharp corners 60 can be created at the edges of the third masking layer 52 . These corners 60 or slopes improve the performance of the resulting floating gates.
- the openings 59 are filled with a dielectric material 64 .
- an oxide layer 64 such as silicon oxide 64 , is deposited overlying the third masking layer 52 and filling the openings 59 .
- This oxide layer 64 is then planarized using, for example, a chemical mechanical polish operation. Other planarization processes could be used.
- the floating gates are defined in the active region direction.
- another lithographic mask 68 is defined overlying the third masking layer 52 and the oxide layer 64 .
- the third masking layer 52 is selectively etched where exposed by the lithographic mask 68 .
- the first conductor layer 28 is etched through where exposed by a lithographic mask 68 and by the oxide layer 64 . Note that this step defines the floating gates 28 in the active area direction.
- the edges of the floating gates 28 so defined are self-aligned to the previously formed oxide layer 64 .
- the opening 68 that is formed serves as the source opening 68 for the completed device. Ions may be implanted through this opening to forms source regions, not shown.
- the source openings 68 are now lined with a lining oxide layer 76 .
- the lining oxide layer 76 is formed by first depositing silicon oxide to a thickness of between about 300 Angstroms and about 500 Angstroms and then etching back this silicon oxide to form spacers 76 lining the opening 68 .
- a conductive plug layer 84 is deposited to fill the openings 68 .
- the conductive plug layer 84 comprises polysilicon.
- the conductive plug layer 84 is then planarized using, for example, a chemical mechanical polish, to complete the source plug 84 .
- a capping oxide layer 80 is formed overlying the conductive plug layer 84 by, for example, a thermal oxidation step.
- the remaining third masking layer 52 is now removed by etching.
- the first dielectric layer 24 is removed from the surface of the substrate 10 .
- pairs 89 of floating gates 28 are formed with source plugs 84 therebetween.
- a second dielectric layer 90 is formed overlying the floating gate pair 891 and the substrate 10 .
- the second dielectric layer 90 preferably comprises a silicon oxide layer that is formed by thermal oxidation to a thickness of between about 120 Angstroms and about 180 Angstroms.
- a second conductor layer 94 is then deposited overlying the second dielectric layer 90 .
- the second conductor layer 94 will be used to form the control gates for the split gate flash devices.
- the second conductor layer 94 preferably comprises polysilicon that is doped or undoped. More preferably, the second conductor layer 94 is deposited to a thickness of between about 1,500 Angstroms and about 3,000 Angstroms.
- the second conductor layer 94 is etched back to form spacers 94 on the sidewalls of the floating gates 28 , with the second dielectric layer 90 therebetween.
- the etching back step is preferably performed using a dry etch with an anisotropic characteristic.
- the resulting spacers 94 form the control gates and word lines for each side of the floating gate pairs 89 .
- Drain regions may be formed by ion implantation between the control gates 94 .
- An isolation layer 100 is deposited overlying the wafer. Contact openings are made in the isolation layer 100 .
- a metal layer 106 is deposited and patterned to form connective lines in the array.
- An effective and very manufacturable method to form a split gate flash memory is achieved.
- the method is used to form closely-spaced MOS gates and, more particularly, closely-spaced floating gates.
- the method to form closely-spaced floating gates adds minimal process complexity to the base process.
- the floating gates so formed are incorporated into split gate flash devices.
- a unique MOS gate structure is achieved.
- the novel method and device of the present invention provides an effective and manufacturable alternative to the prior art.
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Abstract
A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.
Description
- (1) Field of the Invention
- The invention relates to semiconductor memory devices, and, more particularly, to a method of forming a split gate flash memory with minimal floating gate-to-floating gate spacing.
- (2) Description of the Prior Art
- A split gate flash memory device is essentially a MOS transistor with a variable threshold voltage. The threshold voltage varies with the amount of charge that is stored on a floating gate structure. The floating gate structure overlies a first part of the device channel region. A control gate structure overlies a second part of the device channel region. Voltage on the control gate controls the second part of the device channel region directly and controls the first part of the device channel indirectly, as modulated by charge on the floating gate. The control gate is formed in close proximity to the floating gate so that a capacitive coupling between the control gate and the floating gate is achieved.
- Flash memories have undergone significant improvements over the years. In particular, device size has been dramatically reduced. Further reductions in the device size require technological innovations. In particular, the spacing between the floating gates of adjacent split gate flash cells is a significant problem. Currently, the floating gates are patterned, or defined, using a lithographic system. For example, after the deposition of a floating gate layer, the semiconductor wafer is then coated with a photoresist layer. The photoresist layer is exposed to actinic light through a mask. After development, a pattern of photoresist is left on the wafer overlying the floating gate layer. The floating gate layer is then etched where exposed by the patterned photoresist layer.
- There are several difficulties in minimizing the cell-to-cell spacing of the split gate flash cells. The floating gate spacing is often the limiting factor in the cell-to-cell spacing. If the floating gate spacing is made too small, then misalignment in the lithography process or variation in the etching process may lead to bridging or shorting of the floating gates. Alternatively, increasing the floating gate spacing will cause the floating gate overlap of active area (OD) to decrease. Misalignment or overetching could then cause the active area to be uncovered by the floating gate edge. This would result in leaky devices. Finally, methods to self-align the floating gate to the active area result in overly complicated processes or in residue issues. A primary goal of the present invention is to provide a method to reduce cell-to-cell spacing without reducing reliability or yield and without significant complexity.
- Several prior art inventions relate to flash memory cells. U.S. Pat. No. 6,228,695 B1 to Hsieh et al teaches a method to form split gate flash cells with self-aligned sources and self-aligned floating gates. Spacer floating gates are formed on the sidewalls of the control gates. U.S. Pat. No. 5,915,178 to Chiang et al describes a split gate flash and a method of formation. An oxide layer is grown on the surface of the floating gate layer prior to etching the floating gate. U.S. Pat. No. 6,312,989 B1 to Hsieh et al shows a split gate flash device and a method of manufacture. U.S. Pat. No. 6,380,583 B1 to Hsieh et al teaches a split gate flash device and a method of formation. An oxide layer is grown over a floating gate layer to form a hard mask.
- A principal object of the present invention is to provide an effective and very manufacturable method to form a split gate flash memory.
- A further object of the present invention is to provide a method to form closely-spaced MOS gates.
- A yet further object of the present invention is to provide a method to form closely-spaced floating gates.
- A yet further object of the present invention is to provide a method to form closely-spaced floating gates with minimal process complexity.
- A yet further object of the present invention is to provide a method to form closely-spaced split gate flash cells.
- Another further object of the present invention is to provide a unique MOS gate structure.
- In accordance with the objects of this invention, a method to form MOS gates in an integrated circuit device is achieved. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.
- Also in accordance with the objects of this invention, an integrated circuit device is achieved. The device comprises a dielectric layer overlying a substrate. A patterned conductor layer overlies the dielectric layer. A patterned first masking layer overlies the conductor layer. Spacers are on the sidewalls of the patterned first masking layer and overlie the patterned conductor layer. The external edges of the patterned conductor layer and the spacers are aligned.
- In the accompanying drawings forming a material part of this description, there is shown:
-
FIG. 1 illustrates a top layout view of a partially completed split gate flash device array showing a preferred embodiment of the present invention. -
FIGS. 2-8 illustrate a first cross sectional view of the split gate flash device array showing a preferred embodiment of the present invention. -
FIGS. 9-17 illustrate a second cross sectional view of the split gate flash device array showing a preferred embodiment of the present invention. - The preferred embodiments of the present invention disclose a method to form split gate flash memory. A method to form closely-spaced floating gates is described. A unique MOS gate device is illustrated. It should be clear to those experienced in the art that the present invention can be applied and extended without deviating from the scope of the present invention.
- Referring now to
FIG. 1 , the preferred embodiment of the present invention is illustrated. Several important features of the present invention are shown and discussed below. A top view of a partially completed split gate flash memory of the present invention is shown. A typical flash memory comprises a very large number, perhaps millions, of identical memory cells. The cells are arranged in a two-dimensional array to facilitate addressing, reading, and writing to specific cells in the array. - In this exemplary layout, a
wafer substrate 10 is provided. The substrate may comprise any suitable semiconductor material or combination of materials. Preferably, thesubstrate 10 comprises monocrystalline silicon. Other substrates, such as silicon on isolation (SOI), could be used. Thesubstrate 10 is divided into two types of areas: active 10 andisolation 20. The active areas (OD) 10 are simply areas of semiconductor. The isolation areas (STI) 20 are areas where a dielectric material has been formed. Theisolation areas 20 may comprise any type of dielectric material and structure suitable for isolating adjacent active devices. Preferably, theisolation areas 20 comprise shallow trench isolation (STI) that may be formed by well-known methods. Typically,STI regions 20 comprise trenches in thesubstrate 10 that are filled with a dielectric material such as silicon oxide. The memory array is laid out such that theSTI regions 20 and active (OD)regions 10 are in parallel. Two cross sections “2” and “9” are analyzed in the description below. The “2” cross section bisects theparallel STI 20 andOD 10 regions and will illustrate the floating gate-to-floating gate spacing. The “2” cross section corresponds toFIGS. 2-8 below. The “9” cross section is parallel to theSTI 20 andOD 10 regions and will illustrate adjacent split gate flash cells within anactive region 10. The “9” cross section corresponds toFIGS. 9-17 below. - Referring now to
FIG. 2 , the “2” cross section is illustrated. Thesubstrate 10 is divided by a series ofisolation regions 20. Each isolation regions separates an active cell area in the substrate. Referring now toFIG. 3 , several layers are formed overlying thesubstrate 10 andisolation regions 20. Afirst dielectric layer 24 is formed overlying thesubstrate 10 andisolation regions 20. This firstdielectric layer 24 is the floating gate dielectric. Thefirst dielectric layer 24 may comprise any dielectric layer having suitable dielectric constant and breakdown capability. Preferably, thefirst dielectric layer 24 comprises an oxide material. More preferably, thefirst dielectric layer 24 comprises silicon oxide that is thermally grown on thesubstrate 10 to a thickness of between about 80 Angstroms and about 110 Angstroms. For simplicity of illustration, thefirst dielectric layer 24 is only shown overlying thesubstrate 10. - A
first conductor layer 28 is then grown overlying thefirst dielectric layer 24. Thefirst conductor layer 28 may comprise any conductive material, such as a metal, a semiconductor, or a combination of both, that can be used in the formation of a MOS gate. Preferably, thefirst conductor layer 28 comprises a polysilicon layer that is deposited overlying thefirst dielectric layer 24. Thepolysilicon layer 28 may be doped or undoped. More preferably, thepolysilicon layer 28 is formed by chemical vapor deposition of polysilicon to a thickness of between about 500 Angstroms and about 1,200 Angstroms. - A
first masking layer 32 is then deposited overlying thefirst conductor layer 28. Thefirst masking layer 32 is a key feature of the present invention. Thefirst masking layer 32 preferably comprises a material that can be selectively etched with respect to thefirst conductor layer 28. More preferably, thefirst masking layer 32 comprises silicon nitride that is deposited by a chemical vapor deposition process. Most preferably, thefirst masking layer 32 is deposited to a thickness of between about 500 Angstroms and about 1,000 Angstroms. - Referring now to
FIG. 4 , thefirst masking layer 32 is patterned. Preferably, thefirst masking layer 32 is patterned using a lithographic process as shown. Afirst photoresist layer 36 is deposited overlying thefirst masking layer 32. Thefirst photoresist layer 36 is exposed to actinic light through a mask and then is developed. The patternedfirst photoresist layer 36 covers thefirst masking layer 32 as shown. It is important to note that the resulting patternedfirst photoresist layer 36 may exhibitmisalignment 40 as is well-known in the art. Referring now toFIG. 5 , thefirst photoresist layer 36 pattern is transferred to thefirst masking layer 32 by etching through thefirst masking layer 32 where exposed by thefirst photoresist layer 36. The resulting, patterned first maskinglayer 32 is shown. Note thatspacings 42 between first maskinglayer 32 features be made relatively large compared to the final floating gate-to-floating gate spacings that are formed using the unique method as will be demonstrated below. - Referring now to
FIG. 6 , as an important feature of the present invention, asecond masking layer 44 is deposited overlying thefirst masking layer 32 and thefirst conductor layer 28. Thesecond masking layer 44 preferably comprises another material that can be selectively etched with respect to thefirst conductor layer 28. More preferably, thesecond masking layer 44 comprises silicon nitride that is deposited by chemical vapor deposition. Most preferably, thesecond masking layer 44 is deposited to a thickness of between about 600 Angstroms and about 1,200 Angstroms. - Referring now to
FIG. 7 , another important feature of the present invention is illustrated. Thesecond masking layer 44 is etched back toform spacers 44 on the sidewalls of thefirst masking layer 32. This etch back step preferably comprises a dry etch having an anisotropic etching characteristic. Thespacers 44 create a combined first and secondmasking layer pattern narrower spaces 47. As a result, a combinedmasking pattern narrower space 47 than could be reliably achieved by a lithography-only process. Thespaces 47 are controlled by the thickness of the depositedsecond masking layer 44 and by the etching back process. It is also important to note that theexternal edges 48 of thespacers 44 are designed to overlap the edges of theisolation regions 20 such that the resulting gates do not exhibit leakage. - Referring now to
FIG. 8 , another important feature in the present invention is illustrated. Thefirst conductor layer 28 is etched through where exposed by thefirst masking layer 32 and thespacers 44. The floatinggates 28 of the split gate flash device are thereby formed in the direction perpendicular to theactive regions 10 as shown inFIG. 1 . Referring again toFIG. 8 , theedges 48 of the floatinggates 28 overlie theisolation regions 20. Very narrow floating gate-to-floatinggate spaces 49 are possible with a minimally complex process and without creating shorting or leakage problems. - While the method of the present invention is optimally suited for the formation of split gate flash transistors, it can be used to pattern any
MOS transistor gate 28. The resultingMOS gates 28 each comprise thefirst conductor layer 28 overlying thesubstrate 10 with thefirst dielectric layer 24 therebetween. Themasking layer first masking layer 32 overlying thefirst conductor layer 28 andspacers 44 overlying thefirst conductor layer 28. The external edges of thespacers 44 and thefirst conductor layer 28 are aligned. - Referring now to
FIG. 9 , further processing in the formation of a split gate flash memory is illustrated using the “9” cross section. Thefirst masking layer 32 and thespacers 44 are completely removed from the wafer surface. Note that thefirst conductor layer 28 has not been defined in this direction of the array. Several steps are herein illustrated inFIGS. 9-17 to define the floatinggates 28 in the active area direction, to define control gates, and to complete the memory device. Referring again toFIG. 9 , athird masking layer 52 is deposited overlying thefirst conductor layer 28. Thethird masking layer 52 again preferably comprises a material, such as silicon nitride, that can be selectively etched with respect to thefirst conductor layer 28 and, in addition, to silicon oxide layers used as dielectrics in the exemplary device. More preferably, thethird masking layer 52 is deposited to a thickness of between about 3,000 Angstroms and about 4,500 Angstroms. The thickness of thethird masking layer 52 largely determines the height of the final device as will be seen below. Thethird masking layer 52 is then patterned, preferably using lithography. Asecond photoresist layer 56 is deposited and patterned as shown. - Referring now to
FIG. 10 , thethird masking layer 52 is etched through to createopenings 59. Note that an additional etch may be performed to create an optimal topography on thefirst conductor layer 28 as shown. In particular, by over-etching into thefirst conductor layer 28,sharp corners 60 can be created at the edges of thethird masking layer 52. Thesecorners 60 or slopes improve the performance of the resulting floating gates. - Referring now to
FIG. 11 , theopenings 59 are filled with adielectric material 64. Preferably, anoxide layer 64, such assilicon oxide 64, is deposited overlying thethird masking layer 52 and filling theopenings 59. Thisoxide layer 64 is then planarized using, for example, a chemical mechanical polish operation. Other planarization processes could be used. - Referring now to
FIG. 12 , as an important feature, the floating gates are defined in the active region direction. First, anotherlithographic mask 68 is defined overlying thethird masking layer 52 and theoxide layer 64. Next, thethird masking layer 52 is selectively etched where exposed by thelithographic mask 68. Finally, thefirst conductor layer 28 is etched through where exposed by alithographic mask 68 and by theoxide layer 64. Note that this step defines the floatinggates 28 in the active area direction. In addition, the edges of the floatinggates 28 so defined are self-aligned to the previously formedoxide layer 64. Finally, theopening 68 that is formed serves as the source opening 68 for the completed device. Ions may be implanted through this opening to forms source regions, not shown. - Referring now to
FIG. 13 , thesource openings 68 are now lined with alining oxide layer 76. Preferably, thelining oxide layer 76 is formed by first depositing silicon oxide to a thickness of between about 300 Angstroms and about 500 Angstroms and then etching back this silicon oxide to form spacers 76 lining theopening 68. Next, aconductive plug layer 84 is deposited to fill theopenings 68. Preferably, theconductive plug layer 84 comprises polysilicon. Theconductive plug layer 84 is then planarized using, for example, a chemical mechanical polish, to complete thesource plug 84. Finally, acapping oxide layer 80 is formed overlying theconductive plug layer 84 by, for example, a thermal oxidation step. - Referring now to
FIG. 14 , the remainingthird masking layer 52 is now removed by etching. In addition, thefirst dielectric layer 24 is removed from the surface of thesubstrate 10. As a result of the processing to this point, pairs 89 of floatinggates 28 are formed with source plugs 84 therebetween. - Referring now to
FIG. 15 , asecond dielectric layer 90 is formed overlying the floating gate pair 891 and thesubstrate 10. Thesecond dielectric layer 90 preferably comprises a silicon oxide layer that is formed by thermal oxidation to a thickness of between about 120 Angstroms and about 180 Angstroms. Asecond conductor layer 94 is then deposited overlying thesecond dielectric layer 90. Thesecond conductor layer 94 will be used to form the control gates for the split gate flash devices. Thesecond conductor layer 94 preferably comprises polysilicon that is doped or undoped. More preferably, thesecond conductor layer 94 is deposited to a thickness of between about 1,500 Angstroms and about 3,000 Angstroms. - Referring now to
FIG. 16 , as a key feature, thesecond conductor layer 94 is etched back toform spacers 94 on the sidewalls of the floatinggates 28, with thesecond dielectric layer 90 therebetween. The etching back step is preferably performed using a dry etch with an anisotropic characteristic. The resultingspacers 94 form the control gates and word lines for each side of the floating gate pairs 89. - Finally, referring now to
FIG. 17 , the split gate flash memory device is completed. Drain regions, not shown, may be formed by ion implantation between thecontrol gates 94. Anisolation layer 100 is deposited overlying the wafer. Contact openings are made in theisolation layer 100. Ametal layer 106 is deposited and patterned to form connective lines in the array. - The advantages of the present invention may now be summarized. An effective and very manufacturable method to form a split gate flash memory is achieved. The method is used to form closely-spaced MOS gates and, more particularly, closely-spaced floating gates. The method to form closely-spaced floating gates adds minimal process complexity to the base process. The floating gates so formed are incorporated into split gate flash devices. A unique MOS gate structure is achieved.
- As shown in the preferred embodiments, the novel method and device of the present invention provides an effective and manufacturable alternative to the prior art.
- While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
Claims (7)
1.-14. (canceled)
15. An integrated circuit device comprising:
a dielectric layer overlying a substrate;
a patterned conductor layer overlying said dielectric layer;
a patterned first masking layer overlying said conductor layer;
spacers on sidewalls of said patterned first masking layer and overlying said patterned conductor layer wherein external edges of said patterned conductor layer and said spacers are aligned.
16. The device according to claim 15 wherein said patterned conductor layer comprises a floating gate for a non-volatile memory cell.
17. The device according to claim 15 wherein said patterned conductor layer comprises polysilicon.
18. The device according to claim 15 wherein said patterned first masking layer comprises silicon nitride.
19. The device according to claim 15 wherein said spacers comprise silicon nitride.
20. The device according to claim 15 wherein said external edges of said patterned conductor layer overlie isolation structures in said substrate.
Priority Applications (1)
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US11/059,987 US20050156224A1 (en) | 2003-09-05 | 2005-02-17 | Method to make minimal spacing between floating gates in split gate flash |
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US10/655,662 US6881629B2 (en) | 2003-09-05 | 2003-09-05 | Method to make minimal spacing between floating gates in split gate flash |
US11/059,987 US20050156224A1 (en) | 2003-09-05 | 2005-02-17 | Method to make minimal spacing between floating gates in split gate flash |
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US10/655,662 Division US6881629B2 (en) | 2003-09-05 | 2003-09-05 | Method to make minimal spacing between floating gates in split gate flash |
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US10/655,662 Expired - Fee Related US6881629B2 (en) | 2003-09-05 | 2003-09-05 | Method to make minimal spacing between floating gates in split gate flash |
US11/059,987 Abandoned US20050156224A1 (en) | 2003-09-05 | 2005-02-17 | Method to make minimal spacing between floating gates in split gate flash |
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Families Citing this family (4)
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US7176083B2 (en) * | 2004-06-17 | 2007-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | High write and erase efficiency embedded flash cell |
KR100731115B1 (en) * | 2005-11-04 | 2007-06-22 | 동부일렉트로닉스 주식회사 | Flash memory device and method for fabricating the same |
US7951670B2 (en) * | 2006-03-06 | 2011-05-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flash memory cell with split gate structure and method for forming the same |
US8809179B2 (en) * | 2006-04-13 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for reducing topography of non-volatile memory and resulting memory cells |
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US5915178A (en) * | 1997-12-08 | 1999-06-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for improving the endurance of split gate flash EEPROM devices via the addition of a shallow source side implanted region |
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US6312989B1 (en) * | 2000-01-21 | 2001-11-06 | Taiwan Semiconductor Manufacturing Company | Structure with protruding source in split-gate flash |
US6380583B1 (en) * | 1999-04-26 | 2002-04-30 | Taiwan Semiconductor Manufacturing Company | Method to increase coupling ratio of source to floating gate in split-gate flash |
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US6627524B2 (en) * | 2001-06-06 | 2003-09-30 | Micron Technology, Inc. | Methods of forming transistor gates; and methods of forming programmable read-only memory constructions |
US6653188B1 (en) * | 2002-05-08 | 2003-11-25 | Nanya Technology Corp. | Method of forming poly tip of floating gate in split-gate memory |
US20040084713A1 (en) * | 2002-10-30 | 2004-05-06 | Taiwan Semiconductor Manufacturing Company | Structure with composite floating gate by poly spacer in flash |
US20040094795A1 (en) * | 2002-11-18 | 2004-05-20 | Ching-Yuan Wu | Self-aligned floating-gate structure for flash memory device |
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2003
- 2003-09-05 US US10/655,662 patent/US6881629B2/en not_active Expired - Fee Related
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2005
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US5915178A (en) * | 1997-12-08 | 1999-06-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for improving the endurance of split gate flash EEPROM devices via the addition of a shallow source side implanted region |
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US6380583B1 (en) * | 1999-04-26 | 2002-04-30 | Taiwan Semiconductor Manufacturing Company | Method to increase coupling ratio of source to floating gate in split-gate flash |
US6228695B1 (en) * | 1999-05-27 | 2001-05-08 | Taiwan Semiconductor Manufacturing Company | Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate |
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US6653188B1 (en) * | 2002-05-08 | 2003-11-25 | Nanya Technology Corp. | Method of forming poly tip of floating gate in split-gate memory |
US20040084713A1 (en) * | 2002-10-30 | 2004-05-06 | Taiwan Semiconductor Manufacturing Company | Structure with composite floating gate by poly spacer in flash |
US20040094795A1 (en) * | 2002-11-18 | 2004-05-20 | Ching-Yuan Wu | Self-aligned floating-gate structure for flash memory device |
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US6881629B2 (en) | 2005-04-19 |
US20050054162A1 (en) | 2005-03-10 |
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