JPH05243274A - Vertical mosfet - Google Patents

Abstract

PURPOSE:To reduce the dispersion in threshold voltage of a vertical MOSFFT by forming one conductive tape source layer on the surface of a reverse conductive type region in the proximity directly under a polysilicon electrode. CONSTITUTION:An N<-> type epitaxial layer 2 and a P<-> type epitaxial layer 3 are grown on an N<-> type semiconductor substrate 1. Next, using an oxide film 4 as a mask, an ion implantation is performed and an N-type layer 5 is formed. After informing a gate oxide film 4a and a gate polysilicon 6, an N<+> type source 7 is formed. Then, an interlayer insulating film 8 is formed, and a source electrode 9 and a drain electrode 10 are formed. Thus, since the P<-> type epitaxial layer 3 separated by the N<-> type layer 5 is employed as a base, the surface concentration becomes constant. As a result, the dispersion in threshold voltage is reduced. Further, the compact gate polysilicon 6 can be obtained and the parasitic capacitance is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical MOSFET in which variations in threshold voltage and parasitic capacitance are reduced.

[0002]

2. Description of the Related Art A conventional vertical MOSFET is shown in FIG.
This will be described with reference to (a) to (d).

First, as shown in FIG. 5A, an N ⁻ type epitaxial layer 2 is grown on an N ⁺ type semiconductor substrate 1.

Next, as shown in FIG.
˜100 nm gate oxide film 4a and thickness 600 nm
After the gate polysilicon 6 is formed, the gate polysilicon 6 is used as a mask for ion implantation to perform the P-type base 3a.
To form.

Next, as shown in FIG. 5C, ion implantation is performed using a resist (not shown) and the gate polysilicon 6 as a mask to form an N ⁺ -type source 7 having a DSA structure, and then the resist is removed. .

Next, as shown in FIG.
After depositing the interlayer insulating film 8 of 0 to 1000 nm, the contact is opened, and the source electrode 9 and the drain electrode 10 are formed to complete the element portion.

The surface concentration distribution that determines the threshold voltage of the conventional vertical MOSFET is not uniform in the P-type base as shown in FIG. 4 (b). Further, there is a drawback that the peak concentration Q _{B of the} surface of the P-type base that determines the threshold voltage changes depending on the depth of the N ⁺ -type source.

Therefore, the threshold voltage is apt to change and the variation is large.

[0009]

[Problems to be Solved by the Invention] Conventional vertical MOSFE
T uses a DSA structure that forms a P-type base and an N ⁺ -type source using the gate polysilicon as a mask.

Therefore, the peak concentration Q _B of the P-type base surface
Has a problem that the threshold value obtained by the following equation varies.

V _T = φ _MS −Q _SS / C ₀ + 2φ _f −Q _B / C ₀ Here, V _T is the threshold voltage, Q _SS is the surface charge density, and φ
_f is the Fermi level, φ _MS is the work function difference, C ₀ is the capacity per unit area, and Q _B is the peak concentration on the surface of the P-type base.

[0012]

A vertical type MOSFE of the present invention
The T is a reverse conductivity type surrounded by a single conductivity type region formed by sequentially stacking a single conductivity type epitaxial layer and a reverse conductivity type epitaxial layer on one main surface of a single conductivity type semiconductor substrate. With a region as a base, a gate oxide film and a polysilicon gate electrode are formed on the opposite conductivity type epitaxial layer, and a one conductivity type source layer is formed on the surface of the opposite conductivity type region immediately below the polysilicon electrode. It is a thing.

[0013]

EXAMPLE FIG. 1A shows a first example of the present invention.
This will be described with reference to (d).

First, as shown in FIG. 1A, an N ⁻ type epitaxial layer 2 and a P ⁻ type epitaxial layer 3 are grown on an N ⁺ type semiconductor substrate 1.

Next, as shown in FIG. 1B, the oxide film 4
By ion implantation or thermal diffusion after forming the N ^- -type layer 5 ^- N connecting -type epitaxial layer 2. The P ⁻ type epitaxial layer 3 divided by the N ⁻ type layer 5 serves as a base.

Next, as shown in FIG. 1 (c), a thickness of 20
After forming a gate oxide film 4a having a thickness of ˜100 nm, a gate polysilicon 6 having a thickness of 600 nm is deposited. Next, the gate polysilicon 6 is etched using a resist (not shown) as a mask, and then the resist is removed. The resist (not shown) and the gate polysilicon 6 are again used as a mask to perform ion implantation to form an N ⁺ type source 7, and then the resist is removed.

Next, as shown in FIG. 1D, the thickness 50
An interlayer insulating film 8 having a thickness of 0 to 1000 nm is deposited, a contact is opened, a source electrode 9 is formed, and then a drain electrode 10 is formed to complete an element portion.

The current path of this vertical MOSFET is shown by an arrow (→).

In this embodiment, since the base is made of the P ^-- type epitaxial layer 3, the surface concentration becomes flat as shown in FIG. 4 (a) and the variation of the threshold voltage becomes small.

Next, a second embodiment of the present invention will be described with reference to FIG.

First, an N ⁻ type epitaxial layer 2 and a P ⁻ type epitaxial layer 3 are grown on an N ⁺ type semiconductor substrate 1, and then a gate oxide film 4a and a gate polysilicon 6 are formed. Next, ion implantation is performed using a resist (not shown) and the gate polysilicon 6 as a mask to form N ^−.
After forming the mold layer 5, the resist is removed. Furthermore N ⁺
After forming the mold source 5 and depositing the interlayer insulating film 8, the contact is opened, and the source electrode 9 and the drain electrode 10 are formed.
Are formed to complete the element portion.

Next, a third embodiment of the present invention will be described with reference to FIG.

First, an N ⁻ type epitaxial layer 2 and a P ⁻ type epitaxial layer 3 are grown on an N ⁺ type semiconductor substrate 1, a gate oxide film 4a is formed, and then an N ⁻ type layer 5 is formed. Next, V _T control can be performed by ion-implanting the entire surface.

Although the N-channel vertical MOSFET has been described above, the present invention is similarly applied to the P-channel vertical MO.
It can be applied to SFET.

[0025]

By forming the base region with the P type epitaxial layer, the surface concentration of the base can be flattened. As a result, the variation in threshold voltage was reduced. Further, the gate polysilicon region can be reduced in size, and the parasitic capacitance can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view showing a third embodiment of the present invention.

FIG. 4A is a graph showing the surface concentration distribution of the vertical MOSFET of the present invention. (B) is a conventional vertical MOSF
It is a graph which shows the surface concentration distribution of ET.

FIG. 5 is a cross-sectional view showing a conventional vertical MOSFET in process order.

[Explanation of symbols]

1 N ⁺ type semiconductor substrate 2 N ⁻ type epitaxial layer 3 P ⁻ type epitaxial layer 3a P type base 4 oxide film 4a gate oxide film 5 N ⁻ type layer 6 gate polysilicon 7 N ⁺ type source 8 interlayer insulating film 9 source electrode 10 Drain electrode Q _B Base surface peak concentration → Current path

Claims (1)

[Claims] 1. A one-conductivity-type epitaxial layer and a reverse-conductivity-type epitaxial layer are sequentially stacked on one main surface of a one-conductivity-type semiconductor substrate, and a reverse-type surrounded by one-conductivity-type region formed in the reverse-conductivity-type epitaxial layer. Based on the conductivity type area,
A vertical MOSFET in which a gate oxide film and a polysilicon gate electrode are formed on the opposite conductivity type epitaxial layer, and a one conductivity type source layer is formed on the surface of the opposite conductivity type region immediately below the polysilicon electrode.