JPS60226185A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a novel element structure leading to the high-reproducibility manufacture of vertical-type transistors equipped with excellent performance characteristics by a method wherein punch-through at the middle portion of a device is prevented and the structural sensitivity of the device is regulated by controlling the dopant concentration in the active region of a transistor. CONSTITUTION:An N<+> type diffused layer 41 is formed on the surface of a P type (100) Si substrate, and a P type layer 42 is added thereto. Injection of B<+> ions is effected for the formation of a high-concentration P type region 43 (40) in the middle of the P type layer 42. Further, in the surface, a high-concentration N type layer 44 (47) is provided by As diffusion. The multilayer structureis subjected to plasma-etching for the creation of a groove as deep as to reach the N<+> diffusion layer 41. This is followed by the formation by plasma-deposition of an SiO2 film to cover the bottom and surface of the groove. Oxidation is then accomplished of the groove side walls for the formation of a gate insulating film 46. Lithography is applied for the provision of a contact hole in the SiO2 film formed on the high-concentration N type region 47 to be a drain. A metal layer is formed by the directional evaporation method, and lithography is again used for the creation of gates 48 and drain electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to the structure of a semiconductor device, and particularly to the structure of a transistor that controls a current flowing in the vertical direction and is suitable for forming a highly integrated circuit.

[Background of the invention]

(Known example closest to the invention, equity 56-26143)L
As SIs become more highly integrated, the dimensions of elements such as transistors that make up the SIs become smaller and smaller, and the active regions of the elements are now formed with a size of less than 1 μm. but,
For example, as in conventional LSI, there is a source on the Si crystal surface.
In a planar element in which a high concentration diffusion region such as a drain is formed and a control electrode provided on the channel controls the current flowing through a channel region formed on the same crystal surface, each of the source, drain, gate regions and A large area is occupied by electrode connections to these regions, which is one of the obstacles to higher integration. In addition, as devices become smaller, the source and drain become closer together, which causes a depletion layer to expand inside the Si crystal in the channel region, creating a so-called short channel effect that tends to cause a punch-through phenomenon. This has become an obstacle to the development of

As a structure capable of solving the problems caused by such planar devices, a method has been proposed in which the operation of the element is performed based on the idea of controlling the current flowing in a direction perpendicular to the substrate. The so-called static induction type transistor (SIT, Japanese Patent Publication No. 56-26143) shown in FIGS. 1 and 2 is also one such example. Understanding the operation of a conventionally structured SIT is useful for understanding the present invention, and will be briefly explained using FIGS. 1 and 2.

FIG. 1 is a cross-sectional view of a Schottky barrier type element, and the transistor part includes, for example, an n-type low resistance substrate 11 which is to become a source S, an n-type low resistance region 12 which is to be a drain D, and a channel interposed therebetween. Desired n-type high resistance region 13
and an electrode 14 of the gate G forming a Schottky junction therewith.

The current between the source and the drain indicated by the arrow 15 is controlled by modulating the channel width by the depletion layer 16 whose size changes depending on the source and gate voltages. here 17
is an insulating film for gate-source insulation.

As is clear from this structure, in this type of device, a depletion type device is obtained in which the source and drain are normally in a conductive state and the device is operated in a pinch-off direction by a gate bias. With no bias, the sidewall depletion layer causes a pinch-off state, and it is possible to form an enhancement type that expands the current path by biasing the depletion layer in the direction of shrinking it, but depending on the drain voltage and the doping in the high resistance layer. It is extremely difficult to obtain products with uniform characteristics with good reproducibility because the device operation is highly dependent on precision and device processing dimensional precision and is sensitive to structure.

On the other hand, FIG. 2 is a cross-sectional view of an insulated gate type device.
3 is provided. A gate insulating film 24 is formed on the sidewall of the cross section, and a gate electrode 25 is formed therebetween. The source-drain current flows through the inversion layer formed on the side wall of the high-resistance P shadow region 23 as shown by the arrow 26, and the formation of the inversion layer is controlled by the voltage at the gate 25.

Here, 27 is an insulating film between the gate and the source.

The problem with this device is the size dependence of the drain breakdown voltage. If the height of the side wall is sufficiently larger than the width of the P shadow region 23, it can be safely assumed that the conventional planar element is simply formed vertically.

However, in normal processing, as shown in FIG. The layer contacts the depletion layer extending from the source 31 side at a point 38 near the center, resulting in a punch-through situation.

For this reason, in such a structure, a normal insulated gate FET
It doesn't work. In order to operate the FET, it is necessary to accurately form a very thin operating region of 1 μm or less as shown in FIG. 2, and here again, the structural sensitivity of the transistor characteristics is an important issue.

However, despite their small size, vertically operated transistors have a large current capacity compared to planar structures, have large mutual conductance, and are capable of high-speed operation due to their integrated circuit structure. It has attractive properties.

In addition, from a circuit design perspective, a degree of freedom is required in element dimensions, and multiple gates can be installed in the same device and operated independently to enable efficient usage, such as configuring an OR circuit. It is hoped that

[Purpose of the invention]

The object of the present invention is to eliminate the problems of such vertical structural elements,
The object of the present invention is to provide a novel element structure capable of realizing a vertical transistor with good reproducibility and excellent characteristics.

[Summary of the invention]

The present invention provides a way to prevent punch-through in the center of the device as briefly described in FIG. 6 The method also provides a way to control, specifically by controlling the dopant concentration in the active region of the transistor.

[Embodiments of the invention]

The present invention will be explained below based on examples. FIG. 4 is a schematic cross-sectional view of an element when the present invention is applied to the structure illustrated in FIG. 3.

The device structure is the same as that illustrated in FIG. 3, except that a p-type region 40 with a higher concentration is provided within the p-type region. The steps to arrive at this structure are briefly described below.

An n+ diffusion layer 41 is formed on the surface of a p-type (100) silicon substrate by selective diffusion, and a 1 μm thick p-type layer 41 is formed on the surface of a p-type (100) silicon substrate.
After forming the shape layer 42, B+ ions are irradiated with l at 200 keV.
Xl013an-" implantation, forming a high concentration p shadow region 43 (40) in the middle of the p-type layer 42, and at the same time
A high concentration n-type layer 44 (47) formed by s-diffusion was provided. This multilayer structure is etched by plasma etching to form a groove deep enough to reach the n+ diffusion layer 41, and then a Si○2 film of about 300 nm is deposited on the bottom and surface of the groove by plasma deposition.
Formed. At this time, the height of the Si○2 film 45 at the bottom of the groove approximately coincided with the upper surface of the n1 diffusion layer. Next, the trench sidewalls were oxidized and a gate insulation film 46 was provided. 5in2 film (not shown) on the high concentration n shadow area 47 that will become a drain
After forming contact holes by lithography, a metal layer was formed by directional vapor deposition, and a gate 48 and a drain electrode (not shown) were formed by lithography again. Although the description of the process is omitted, the contact to the source region 41 is formed separately.

The peak concentration of the P-type high concentration region 40 formed within the P shadow region 42 is approximately 40×10” am−’, and the thickness is approximately 0.2
It is μm. Because of this barrier layer, the depletion layer extending from the drain 47 cannot reach the source 41, and a drain breakdown voltage of 8V or more can be obtained without causing punch-through in a normal device operation region. P type high concentration region 40
Although the threshold voltage of the FET formed on the sidewall increases by forming B on the sidewall due to gate oxidation,
Because of the redistribution and because the effective channel length is close to the barrier layer thickness, the threshold voltage is not as high as estimated from the spatial concentration.

In the device structure shown in FIG. 4 to which the present invention is applied, the effective channel length is short and the channel width is the entire circumference of the P shadow region 40, so the mutual conductance is extremely large compared to a planar device obtained with the same surface area. can be obtained.

Although this embodiment has been described for an n-channel MO5FET, it can also be applied to a P-channel MO3FET by changing the polarity of the conductivity type. In addition, in this example, P
The shaped high-concentration region was formed at a position approximately half the height of the P shadow region 42 by high-energy ion implantation, but this was done in consideration of positional matching with the gate electrode. However, the high-concentration p shadow region 40 can be formed not only by high-energy ion implantation, but also by, for example, low-energy ion implantation followed by diffusion near the surface of the device, or simply by diffusion. Alternatively, it can be formed at the same time as the P-type layer 42 is formed, but since the device characteristics are structurally sensitive, the dopant concentration and distribution must be precisely reproduced.

An example in which the p-type high concentration layer is formed using another method will be shown below.

FIG. 5 shows a cross section of an element when B is introduced using a focused ion beam in the process explained in FIG. 4. The n+ region 41 and the p-type layer 42 of the substrate are formed in the same manner as in the process shown in FIG.
．． A B ion beam focused to a diameter of about 1 μm is irradiated while scanning the inside of the island-like P shadow region 52, leaving 0.5 μm around the periphery, to obtain the shape of the high concentration region 50 as shown in FIG. The formation of the surface layer 44 is performed concurrently with the annealing of the implantation layer, and the subsequent formation of the gate, source insulating film 45, gate oxide film 46, and gate metal 48 is performed in the same manner as in the previous example.

The advantages in terms of device operation obtained by the structure of this device are the same as those explained in FIG. When gate electrodes are provided independently at different locations within the p-shaped shadow region 52, it is possible to obtain a composite element having a structure in which, for example, several FETs with different threshold voltages are connected in parallel, and multivalue processing, etc. It can be applied to the following circuits.

The process of doping at a certain distance from the sidewall can be applied to the Schottky barrier FET or junction FET described in FIG. 1, and can form an SIT with uniform characteristics with good reproducibility. It is possible to obtain such a composite element. An example of the structure is shown in FIG.

The structure of the device is the same as that shown in FIG. 1 except that a P-type high concentration region 60 is formed inside the n-type high resistance layer 13.

An n-type high-resistance region 12 is provided on the substrate via an n-type low-resistance region 61 and an n-type high-resistance layer 13.
A metal gate 14 forming a Schottky junction therewith is provided on the side wall of the source 61, and is connected to the source 61 via an insulating film 17. Note that the metal gate 14 may be a low-resistance p-type St, and in this case, it is a junction-type FET separated by a pn junction formed by slightly diffusing a dopant from the p-type ASi into an n-type high-resistance region. It becomes a structure.

In this structure, the source-drain current flows between a depletion layer 66 formed on the sidewall and extending from the gate 14 side, and a depletion layer 62 formed between the n-type high resistance region 13 and the p-type high concentration region 6o. It flows through the gap as shown by the arrow 63. The size of this depletion layer gap depends on the dopant concentration of the n-type high-resistance region 13, as well as the concentration of the p-type high-concentration region 60 and the distance from the sidewall, but these can be precisely determined using a focused ion beam. It is possible to control the Therefore, the level of control is higher than simply relying only on the machining accuracy of the island-like region 13 as shown in FIG. 1, and it is possible to provide an element that can operate on an island-like region of any size.

The structure of the present invention can also be applied to miniaturized devices.

The impurity concentration of the semiconductor used in the active region of the device is 10
Around "c+n-", this is a state in which 103 impurities are contained in 1 μm3, but when the - edge becomes about 0.4 μm, the number of impurities contained in this decreases to less than 100, and due to statistical fluctuations, the element It becomes difficult to achieve uniform characteristics.In other words, control is required to ensure that quantized impurities are included in the device.According to the spirit of the present invention, as shown in FIG. The purity of the region 73 is increased to, for example, a dopant concentration of 10110l3' or lower, and the high-resistance region 73 contains an amount of impurity that determines the characteristics of the active region at a higher concentration.
This problem can be solved by forming 8 using, for example, a focused ion beam.

FIG. 7 shows a structure similar to that in FIG. 2, in which the high resistance region 73 is arranged in the form of an island between an n-type low resistance region 71 provided on the silicon substrate and an n-type low resistance region 72 provided on the surface. The device is controlled by controlling the voltage applied to a gate electrode 75 provided through a gate insulating film 74 provided on the side wall of the island-like high resistance region 73. In this device, the gate electrode 75 is separated from the source 71 by an insulating film 77.

Since the formation of the high concentration p regions 78 is performed individually using a focused ion beam, impurities can be introduced at any dose into any device when an integrated circuit is constructed. For example, the threshold voltage of a MOSFET can be It can also be controlled and set. Furthermore, when the width of the high resistance region in the direction parallel to the main surface of the substrate is about 1 μm or less, the threshold voltage changes in proportion to the ion dose, and the amount changes as shown by the line perpendicular to the paper in Figure 7. A density of around 3 x 10-''c/μm is sufficient.

Therefore, even if a focused beam with an output of 1 nA class is used, 3
The writing time is X10-7 sec/μm, and a 4-inch wafer can be processed in a writing time of several minutes.

FIG. 8 shows the concentration range of the p-type high concentration layer that is effective for the above purpose. Figure 8 shows the impurity concentration distribution measured in the depth direction at the center of the element illustrated in Figure 4.
1 is the P concentration of the high concentration n shadow area provided on the substrate, 82 is the As concentration of the n type paper resistance area formed on the substrate surface, and the shaded area 83 is the surface containing the highest p concentration area formed by implantation. This is the B concentration of the region.

In order to achieve the punch-through between the source and the drain described in FIG. 3, it is practically sufficient if the peak concentration is 101101B' or more, and even if it greatly exceeds this, it will only require a longer process time and there will be no advantage. Furthermore, in the device shown in FIG. 5, the threshold voltage becomes too high, making it impossible to obtain device operation, and other problems arise, such as an increase in crystal defects due to the introduction. Further, if the thickness is less than 1016 am-'', the effect of impurity introduction will not be sufficiently manifested.

Of course, FIG. 8 is only an example of the concentration distribution, and in reality, the range changes depending on the shape of the distribution, and as illustrated in FIG. 7, the total amount of impurities introduced may contribute to the device characteristics. Therefore, in the present invention, it can be understood that it is important to provide the intermediate layer with a region having a higher impurity concentration than the impurity concentration in the semiconductor constituting the intermediate layer.

It can also be understood that, in view of the operating characteristics of the device, it is necessary to form the high concentration region of the present invention by introducing an impurity having a polarity different from the conductivity type of the regions constituting the source and drain.

〔Effect of the invention〕

As described above, by applying the present invention, it becomes possible to stably and reliably manufacture a vertically moving element that can be miniaturized and obtain various advantages in terms of element characteristics, and also enables By controlling the amount of impurities introduced that constitute the low resistance region, it is possible to control device characteristics and add a new degree of freedom in the integrated circuit configuration.

Although the embodiments have mainly been described with respect to n-channel devices, the present invention can also be applied to p-channel devices by reversing the polarity of the conductivity type.

Further, although silicon has been cited as an example of a semiconductor, it goes without saying that the invention can be similarly applied to compound semiconductors such as GaAs.

[Brief explanation of the drawing]

Figures 1 and 2 are cross-sectional views of a vertical element with a conventional structure, Figure 3 is a cross-sectional view of the element for explaining problems in the conventional structure, and Figures 4 to 7 show embodiments of the present invention. The cross-sectional view, FIG. 8, is a diagram showing the dopant concentration distribution in the depth direction according to the present invention. 41.44.47...Low resistance n-type semiconductor region, 42.
...High resistance P type semiconductor region, 40.43...Low resistance p
type semiconductor region, 14, 25, 35, 75. 48... gate conductor, 16, 66... depletion layer, 17, 27° 37
．． 45.77... Insulating film, 24.34, 46°74.
...Gate insulating film. Y 1 Figure 2 Figure M3 口J゛/ Cup 4- Figure 5 Figure'dat Figure 7 Mouth AI? fD Kauqun rubbish (Sakan γυ

Claims (1)

[Claims] 1. In a semiconductor device in which a pair of low-resistance semiconductor layers are laminated with a high-resistance semiconductor layer in between, and a control electrode provided on the cross-sectional side wall of the layer controls the current flowing between the low-resistance semiconductor layers using an electric field, the intervening height is A semiconductor device characterized in that a region containing an impurity of a conductivity type different from that of the low-resistance semiconductor layer at a higher concentration than the dopant of the high-resistance semiconductor layer is provided in the resistive semiconductor layer.