JPS6346760A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To be able to preferably form transistors which use the sides of grooves without implanting a high concentration n-type impurity to the sides of the grooves by ion implanting the bottoms of the grooves after forming the grooves to form an n-type high concentration impurity layer. CONSTITUTION:An n-type impurity layer 12 is buried in advance in a region for forming an impurity layer on the bottom of the groove, and then epitaxially grown to form a p-type epitaxial layer 13. Further, a trench 16 is opened at a predetermined place, and a gate electrode is formed through a gate oxide film 17 as a word line 18. Thereafter, a capacitor lower electrode is formed by electrically contacting with the layer 12. The electrodes in the bottom of the trench of the transistor can be formed even if ion implanting is not performed after the trench is formed. Thus, a source diffused layer can be formed without deteriorating transistor characteristics using the side faces of the groove.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device, and in particular, a semiconductor memory device in which a gate portion of a switching transistor is formed perpendicular to a substrate, and a capacitor portion is formed above the switching transistor. The present invention also relates to a method of manufacturing a semiconductor memory device that enables high integration.

(Prior Art) Dynamic memory cells are widely used as memory elements because they are composed of a memory capacitor and a switching transistor and are suitable for high integration. However, as integration becomes higher and the area per cell decreases, not only the area occupied by the memory capacitor but also the area occupied by the switching transistor must be reduced.

One of the attempts to reduce the area occupied by the switching transistor is to form the switching transistor section perpendicularly to the substrate. FIGS. 3(a) to 3(d) are process cross-sectional views of a dynamic MOS memory cell in which a conventional switching transistor is formed perpendicularly to a substrate.

Hereinafter, the conventional example will be explained according to the process sectional view shown in FIG.

First, an N-type impurity layer 32 that will become a bit line is formed in a stripe shape on a P-type silicon substrate 31 by ion implantation or the like. Then, for example, relatively thick SiO.

Forming a film 33 and patterning it into a predetermined shape,
The entire SiOt film 33 is formed, patterned into a predetermined shape, and SiO! Using the entire film 33 as an etching mask, the substrate 31 is etched by reactive ion etching (IE) to form one trench for one memory cell. Next, an impurity layer 34 of a conductivity type opposite to that of the substrate is formed at the bottom of the groove using an ion implantation method (third
Figure (a)).

Next, a first insulating film 35 is formed on the side walls and bottom of the trench, for example, with Si.
A conductive film 36, for example, a polycrystalline silicon film containing phosphorus, is formed in a stripe shape in a direction perpendicular to the bit line.

When processing into stripes, at least a portion of the polycrystalline silicon film at the bottom of the trench is removed by etching to provide an opening. (Figure 3(b)).

Here, the insulating film 35 is used as a gate insulating film of a switching transistor, and the conductive film 36 is a second insulating film 37, for example, a Sin, etc. After forming the film, the insulating film 37 at the bottom of the trench is selectively removed and the conductor 1! membrane 3
8. For example, a polycrystalline silicon film containing phosphorus is formed at the intersection of the bit line and the word line to serve as the lower electrode of the capacitor (FIG. 3(C)). At this time, the conductive film 38
4 to be electrically connected.

(Problems to be Solved by the Invention) The present invention provides that when an impurity layer is formed on the bottom of the groove, for example, when ion implantation is used, the impurity is also injected into the sidewall of the groove. This solves the problem that the threshold voltage control of the switching transistor to be formed deteriorates.

[Structure of the invention]

(Means for Solving the Problems) In the present invention, an N-type impurity layer is buried in advance in a region at the bottom of a trench where an impurity layer is to be formed, and then epitaxial growth is performed to form a P-type epitaxial layer.

Furthermore, a trench is opened at a predetermined location, and a gate electrode is formed via a gate oxide film to form a word line. After that, contact is made to the N-type impurity layer,
Form a capacitor lower electrode. By doing so, the electrode at the bottom of the trench of the transistor can be formed without performing ion implantation after forming the trench.

(Function) In the present invention, a transistor using the side surfaces of a trench as a channel region is configured, for example, by using the Si surface as a drain diffusion layer and the bottom of the trench as a source diffusion layer. In order to form the N-type impurity layer (source diffusion layer) at the bottom of the trench, the conventional method is to form a heavily doped N-type layer by performing ion implantation after forming the trench, or to form a heavily doped N-type layer at the bottom of the trench. Two methods have been proposed in which the silicon oxide layer is formed by diffusion from doped poly-Si, but both methods have their own drawbacks.

For this purpose, an n-type buried impurity layer is formed in advance, a P-type epitaxial layer is formed on it, a trench is formed to reach the N-type buried impurity layer, and this N-type impurity layer is used as the source of the transistor. The present invention proposes a method of using it as a diffusion layer. By doing so, the source diffusion layer can be formed without deteriorating the characteristics of the transistor using the side surfaces of the trench.

(Example) An example of the present invention will be described with reference to process cross-sectional views shown in FIGS. 2(a) to (e).

First, antimony (sb), for example, is added as an impurity onto a P-type (100) silicon substrate 11.

A first N-type cavity concentration layer 12 is formed, and then a P-type silicon layer 13 having a concentration of about 1 to 10 Ωcm is formed on the entire surface by epitaxial growth to a thickness of, for example, about 2 μm.

It is assumed that this N-type impurity layer 12 has a shape that includes at least a region where 1 will be formed in a later step. Further, on the surface of this epitaxial layer 13, a second N-type impurity layer 14, which will become a bit line, is formed in a stripe shape by ion implantation (FIG. 2(a)).

Next, for example, a relatively thick 5 in 2 film 15 of about 4000 A is formed by thermal oxidation, patterned into a predetermined shape, and etched by reactive ion etching (RIE) using this SiO film 15 as an etching-resistant mask. The second NffJ layer 14 and the epitaxial layer 13 are etched successively to form the first N-type cavity 12.
A groove 16 is formed so as to reach (FIG. 2(b)). Next, a first insulating film 17, for example S
An iO1 film of about 200 Å is formed, and a polycrystalline silicon film containing a conductor, for example, phosphorus, is deposited over the entire surface via the first insulating film 17. At this time, it is preferable to select conditions for depositing the polycrystalline silicon film such that the polycrystalline silicon film is deposited thickly on the flat part and thinly on the side walls and bottom of the trench.

Next, reactive ion etching (RIE) is used to etch the polycrystalline silicon over the entire surface, and the etching is terminated when only the polycrystalline silicon film at the bottom of the groove is etched away. The polycrystalline silicon film is etched so that enough polycrystalline silicon film to function as an electrode is left on the flat portion where the film is thicker than the bottom of the trench and on the sidewalls of the trench. Next, conductive film 1 from which only the bottom of the groove is etched away is removed by a patterning process using a normal resist.
8 are formed in a stripe shape in a direction perpendicular to the bit line (FIG. 2(C)). Here, the insulating film 17 is used as a gate insulating film of a switching transistor, and the conductive film 17 is used as a gate electrode, that is, a word line of a memory cell.

Next, a second insulating film 19 is formed on the conductive film 18, e.g.
After forming the film, the insulating film 19 at the bottom 20 of the groove is selectively removed to expose the first N-type impurity layer 12, and the conductive film 2 is removed.
1. For example, put a polycrystalline silicon film containing phosphorus on the bit line 1.
4 and the word line 18, and serve as the capacitor lower electrode (FIG. 2(d)). At this time, the conductive film 21 and the first N-type impurity layer 12 are electrically connected, and the first
The N-type impurity layer serves as a source electrode of the switching transistor. For example, if the second insulating film 19 is formed of a thermal oxide film, the oxidation rate of a polycrystalline silicon film is faster than that of a silicon substrate, so the entire surface is then subjected to RIE or the like.
By performing in-film etching, it is possible to remove only the oxide film at the trench bottom 20 by etching.

After this, a third insulating film 22, for example, a film of about 100A of Si, is further formed on the conductive film 21, and then a conductive film 23, for example, a polycrystalline silicon film containing phosphorus, is deposited on the entire surface as a capacitor counter electrode. Form the capacitor part (
Figure 2(e)).

Note that the conductive films 18, 21, and 23 are not limited to polycrystalline silicon, but may be a silicide film, metal, or a combination of polycrystalline silicon, silicide metal, and the like. Also,
The first, second, and third insulating films are also 8i0. Not limited to films, nitride films, high dielectric films, or multi-M films that combine them.
Needless to say, it may be a membrane.

After this, a third insulating film 39, for example, a Sin film with a thickness of about 10 OA, is further formed on the conductive film 38, and then a conductive film, for example, a polycrystalline silicon film 40 containing phosphorus is formed on the entire surface as a capacitor counter electrode. , complete the memory cell (third
Figure (d)).

〔Effect of the invention〕

By adopting such a memory cell structure, it has become possible to realize a small memory cell area.

However, in the method of forming an impurity layer at the bottom of the trench by ion implantation after forming the trench, impurity ions are also implanted into the sidewalls 45 of the trench, as shown in FIG. It becomes very difficult to adjust the threshold value of the switching transistor formed on the sidewall 15≦, and a problem arises in that the electrical characteristics of the memory cell are significantly degraded.

Furthermore, as shown in FIG. 5, the formation of n''W+159 at the bottom of the trench was conventionally carried out by diffusion from a poly-Si film 57 doped with phosphorus; Due to variations in the concentration of phosphorus in the natural oxide film and the phosphorus 5i57, it was not possible to diffuse the phosphorus to the bottom corner 60 of the trench with good control.For this reason, the bottom corner 60 of the trench had an effect on the characteristics of the transistor that utilized the sidewalls of the trench. For example, a so-called "hump phenomenon" in which the subthreshold characteristics of a transistor becomes two-stage has been observed, significantly reducing product yields.

According to the present invention, there is no need to perform ion implantation to form an n-type high concentration impurity layer at the bottom of the groove after forming the groove. No n-type impurity is implanted. Therefore, a transistor using the side surfaces of the trench can be formed satisfactorily.

In addition, since there is no need to use the method of diffusion from poly-Si, the bottom corner of the trench does not become the channel region of the transistor, and abnormalities caused by the n-type impurity layer at the bottom of the trench do not occur in the transistor characteristics. . Further, according to the present invention, the area occupied by each cell is significantly reduced compared to the conventional example, and high integration becomes possible. In addition, the gate length can be freely controlled by adjusting the depth of the hole.
By making the hole deeper, the short channel effect can be reduced. Furthermore, since the entire sidewall of the hole becomes a channel portion, the transistor operates with a relatively large current, increasing the speed of memory operation. Also, since the capacitor part does not face the substrate, it has good resistance to soft air. Further, according to the present invention, the source 1 of the transistor! When making poles, ions are implanted into the bottom of the groove, and poly-Si doped with phosphorus is used.
Since there is no need for diffusion from the substrate, transistor characteristics do not deteriorate, and product yield and reliability are significantly improved.

[Brief explanation of drawings]

FIG. 1 is a plan view and a schematic diagram for explaining the memory cell structure of the present invention, FIG. 2 is a process sectional view for explaining an embodiment of the present invention, and FIG. 3 is for explaining a conventional example. 4 and 5 are cross-sectional views for explaining the problems of the conventional method. P-type silicon substrate...11.31.41.51N layer (drain)...14.32.52Sin, film...15
．． 33.43 Hole...16 nFll(7-x)-34,44,59 Gate insulating film (Sint)...17.35.54 Poly-Si (word line)...18.36.55 Hole bottom...20, 58 Bit line...23, 42, 52 Pitaxial layer...13 N-type buried layer...12 Agent Patent attorney Noriyuki Chika Yudo Kikuo Takehana m1 diagram Figure 2 (d)? 83 Figure 4

Claims (3)

[Claims] (1) In a method for manufacturing a semiconductor memory device in which a memory cell consisting of a MOS transistor and a MOS capacitor is integrated on a semiconductor substrate, at least a portion of a region of the semiconductor substrate that becomes a source of a MOS transistor is provided with a conductivity type opposite to that of the substrate. a step of forming a first high concentration impurity layer; a step of depositing a semiconductor layer containing an impurity of the same conductivity type as the substrate over the entire upper surface of the semiconductor substrate and the first impurity layer;
forming a third high-concentration impurity layer on the surface of the second impurity layer and having a conductivity type opposite to that of the substrate, which will become the drain of the MOS transistor; a step of forming a hole provided to reach the first impurity layer; and a step of forming a second impurity layer using the first impurity layer provided at the bottom of the hole and having a conductivity type opposite to that of the substrate as a source. forming a gate electrode of a MOS transistor by covering the hole via a first gate insulating film so as to form a channel region and a third impurity layer as a drain;
Contact is made with the first impurity layer at the opening provided in the first impurity layer at the bottom of the hole, and the contact layer is formed on at least the gate electrode layer via the gate electrode and the second insulating film. 1. A method of manufacturing a semiconductor memory device, comprising: forming a capacitor lower electrode layer; and forming a capacitor upper electrode on the capacitor lower electrode layer with a third insulating film interposed therebetween. (2) The gate electrode is a polycrystalline silicon film doped with phosphorus, the capacitor lower electrode is a polycrystalline silicon film doped with phosphorus, and the second insulating film is an oxide film or includes an oxide film. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the capacitor upper electrode is a multilayer film, and the capacitor upper electrode is a polycrystalline silicon film doped with phosphorus. (3) At least the surface layer of the capacitor lower electrode is a metal layer, the second insulating film is an insulating film including at least a high dielectric constant film, and the second insulating film is in contact with at least the second insulating film of the capacitor upper electrode. 2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the region is a metal layer.