JP2519215B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a gate portion of a switching transistor is formed vertically on a substrate and a capacitor portion is formed above a switching transistor. The present invention relates to a method of manufacturing a semiconductor memory device that enables high integration.

(Prior Art) A dynamic type memory cell is widely used as a memory element because it comprises a memory capacitor and a switching transistor and is suitable for high integration. However, as the degree of integration increases and the area per cell decreases, not only the area occupied by the memory capacitor but also the area occupied by the switching transistor must be reduced.

As one of the attempts to reduce the area occupied by the switching transistor, there is a method of forming the switching transistor portion vertically on the substrate. FIGS. 3A to 3D are process sectional views of a dynamic MOS memory cell in which a conventional switching transistor is formed vertically on a substrate.

The conventional example will be described below with reference to the process sectional view of FIG.

First, an N-type impurity layer 32 to be a bit line is formed in stripes on a P-type silicon substrate 31 by ion implantation or the like. Next, for example, a relatively thick SiO ₂ film 33 is formed, which is patterned into a predetermined shape to form a SiO ₂ film 33, which is patterned into a predetermined shape, and the SiO ₂ film 33 is used as an etching resistant mask. Reactive ion etching (RI
The substrate 31 is etched by E) to form one groove for one memory cell. Next, an impurity layer 34 having a conductivity type opposite to that of the substrate is formed on the bottom of the groove by ion implantation (FIG. 3A).

Then, on the side wall and the bottom of the groove, a first insulating film 35 such as SiO _{2 is formed.}
A film is formed, and a conductive film 36, for example, a polycrystalline silicon film containing phosphorus is formed in a stripe shape in a direction orthogonal to the bit line.

When processing into a stripe shape, at least a part of the polycrystalline silicon film at the bottom of the groove is removed by etching to form an opening. (FIG. 3 (b)).

Here, the insulating film 35 is used as the gate insulating film of the switching transistor, and the conductive film 36 is used as the gate electrode, that is, the word line of the memory cell. Next, the conductive film 36
After forming a _second insulating film 37, for example, a SiO ₂ film on the above, the insulating film 37 at the bottom of the groove is selectively removed, and a conductive film 38, for example, a polycrystalline silicon film containing phosphorus is crossed between the bit line and the word line. To form a capacitor lower electrode (FIG. 3 (c)). At this time, the conductive film 38 is formed so as to be electrically connected to the impurity layer 34.

(Problems to be Solved by the Invention) In the present invention, when an impurity layer is formed at the bottom of a groove, for example, when an ion implantation method is used, impurities are also injected into the sidewall of the groove and This solves the problem that the threshold control of the formed switching transistor deteriorates. Further, there have been the following problems in the past. That is, a step of forming a hole on the surface of a semiconductor substrate by reactive ion etching, and a step of forming a first impurity layer (source) of a conductivity type opposite to that of the substrate at the bottom of the hole by an ion implantation technique. In such a case, the total sum of damages to the semiconductor substrate due to the reactive ion etching and the ion implantation technique becomes very large, and a phenomenon occurs in which defects are concentrated at the corners of the bottom of the hole or in the vicinity thereof. Therefore, the accumulated charge leaks through the defect from the capacitor lower electrode layer that accumulates the charge and is formed so as to contact the first impurity layer (source).
There is a problem that it becomes impossible to retain memory. Furthermore, the defects are no longer recovered by some heat treatment thereafter, and the recovery may progress to some extent by increasing the heat treatment temperature or prolonging the heat treatment. Since the diffusion of the first impurity layer (source) existing at the bottom of the hole proceeds in the lateral direction, a short channel effect occurs in the MOS transistor formed vertically inside the hole, and it is difficult to miniaturize the device. There is a problem of becoming. The present invention also solves this problem.

[Structure of Invention]

(Means for Solving Problems) In the present invention, an N-type impurity layer is buried in a region where an impurity layer is to be formed at the bottom of a groove in advance, and then epitaxial growth is performed to form a P-type epitaxial layer. Further, a trench is opened at a predetermined place, a gate electrode is formed via a gate oxide film, and a word line is formed. After that, the N-type impurity layer is electrically contacted,
A capacitor lower electrode is formed. By doing so, the electrode at the bottom of the trench of the transistor can be formed without performing ion implantation after forming the trench.

(Operation) In the present invention, the transistor using the side surface of the groove as the channel region has, for example, the Si surface as the drain diffusion layer and the bottom of the groove as the source diffusion layer. To form the N-type impurity layer (source diffusion layer) at the bottom of the groove, conventionally, a method of forming an N-type high concentration layer by performing ion implantation after forming the groove and a method of depositing phosphorus at the bottom of the groove, for example, are used. Two methods have been proposed, one being a method of diffusing poly-doped Si from the other, but both methods have drawbacks.
Therefore, an n ⁺ type buried impurity layer is formed in advance, a P type epitaxial layer is formed thereon, and a groove is formed so as to reach the N type buried impurity layer. The present invention proposes a method of using as a source diffusion layer. By doing so, the source diffusion layer can be formed without deteriorating the transistor characteristics using the side surface of the groove. Further, according to the present invention, a first impurity layer having a conductivity type opposite to that of the substrate is previously formed in a region of the semiconductor substrate which is to be a source of the MOS transistor, and the substrate is formed on the entire upper surface of the semiconductor substrate and the first impurity layer. A second semiconductor made of a semiconductor containing impurities of the same conductivity type as
After the impurity layer is deposited by the epitaxial growth method, the hole is formed in the semiconductor substrate so as to reach the first impurity layer. Therefore, even when the first impurity layer is formed by, for example, the ion implantation technique, When the second impurity layer is formed thereon by the epitaxial growth method,
It becomes possible to immediately recover from defects that may exist,
Furthermore, even if a defect occurs when the hole is formed by reactive ion etching after that, it is possible to suppress the defect to a level that can be sufficiently recovered. Therefore, the phenomenon in which defects concentrate on the corner of the bottom of the hole or in the vicinity thereof does not occur, so that from the capacitor lower electrode layer that is formed so as to contact the first impurity layer (source) and accumulates electric charges. It is possible to prevent the accumulated charges from leaking, and it is possible to stably hold the memory.

(Embodiment) An embodiment of the present invention will be described with reference to process sectional views shown in FIGS.

First, for example, antimony (Sb) is used as an impurity on the P-type (100) silicon substrate 11. A first N-type high concentration layer 12 is formed, and then a P-type silicon layer 13 having a concentration of about 1 to 10 Ωcm is formed on the entire surface by an epitaxial growth method to have a thickness of, for example, about 2 μm. It is assumed that the N-type impurity layer 12 has a shape including at least a region where a groove is formed in a later step. Further, an N-type second impurity layer 14 to be a bit line is formed in a stripe shape on the surface of the epitaxial layer 13 by an ion implantation method (FIG. 2 (a)).

Next, for example, a relatively thick SiO ₂ film 15 is formed, for example, by thermal oxidation to a thickness of about 4000Å, and this is patterned into a predetermined shape. Using this SiO ₂ film 15 as an etching resistant mask, for example, reactive ion etching (RIE) is performed. 2), the second N-type layer 14 and the epitaxial layer 13 are continuously etched to form a groove 16 so as to reach the first N-type layer 12 (FIG. 2 (b)). Next, a first insulating film 17, for example, a SiO ₂ film of about 200 Å is formed on the side wall and the bottom of the groove 16, and further,
A conductive film 18, for example, a polycrystalline silicon film containing phosphorus is deposited on the entire surface through the first insulating film 17. At this time, it is preferable to select, as the deposition condition of the polycrystalline silicon film, for example, a thick film at the flat portion and a thin film at the sidewall and bottom of the groove. Next, reactive ion etching (RIE) is used to etch the polycrystalline silicon on the entire surface, and the etching is terminated when only the polycrystalline silicon film at the bottom of the groove is removed by etching. Etching is performed so that a flat portion having a thicker film thickness than the bottom portion of the groove and a sidewall portion of the groove are left with a polycrystalline silicon film sufficient to act as an electrode. Next, a conductive film 18 in which only the bottom of the groove is removed by etching is formed in a stripe shape in the direction orthogonal to the bit line by a patterning process using a normal resist (FIG. 2 (c)). Here, the insulating film 17 is used as a gate insulating film of a switching transistor, and the conductive film 17 is used as a gate electrode, that is, a word line of a memory cell. Next, after forming a _second insulating film 19, for example, a SiO ₂ film on the conductive film 18, the insulating film 19 at the bottom 20 of the groove is selectively removed,
The first N-type impurity layer 12 is exposed, and the conductive film 21, for example, a polycrystalline silicon film containing phosphorus is formed on the bit line 14 and the word line 18.
To form a capacitor lower electrode (FIG. 2 (d)). At this time, the conductive film 21 and the first N-type impurity layer 12
Are electrically connected to each other, and the first N-type impurity layer serves as the source electrode of the switching transistor. Also,
For example, if the second insulating film 19 is formed of a thermal oxide film, the polycrystalline silicon film has a higher oxidation rate than the silicon substrate. Therefore, if the entire surface is thereafter etched with a SiO ₂ film by RIE or the like, the groove bottom 20 It is possible to remove only the oxide film by etching.

After this, a third insulating film 22, such as Si, is further formed on the conductive film 21.
After forming an O ₂ film of about 100 Å, a conductive film 23, for example, a polycrystalline silicon film containing phosphorus is deposited on the entire surface as a capacitor counter electrode to form a capacitor portion (FIG. 2 (e)).

The conductive films 18, 21, and 23 are not limited to polycrystalline silicon, and may be a combination of a silicide film or metal, or polycrystalline silicon, silicide metal, or the like. Further, the first, second, and third insulating films are not limited to SiO ₂ films, but nitride films,
It goes without saying that it may be a high-dielectric film or a multi-layer film combining them.

After that, a third insulating film 39, for example, a SiO ₂ film having a film thickness of about 100Å is further formed on the conductive film 38, and then a conductive film, for example, a polycrystalline silicon film 40 containing phosphorus is formed on the entire surface as a capacitor counter electrode. , A memory cell is completed (FIG. 3 (d)).

〔The invention's effect〕

By adopting such a memory cell structure, a fine memory cell area can be realized. However, in the method of forming the impurity layer at the bottom of the groove by the ion implantation method after forming the groove, the impurity is also ion-implanted in the side wall portion 45 of the groove as shown in FIG. It becomes very difficult to adjust the threshold value of the switching transistor formed on the side wall, which causes a problem that the electrical characteristics of the memory cell are significantly deteriorated.

Further, the formation of the n ⁺ -type layer 59 at the bottom of the groove has been conventionally performed by diffusion from the poly-Si film 57 doped with phosphorus as shown in FIG. Due to the natural oxide film of 58 and the variation of phosphorus concentration in the poly-Si 57, it was not possible to diffuse to the bottom corner 60 of the groove with good controllability. Therefore, the bottom corner 60 of the groove affects the transistor characteristics using the side wall of the groove, and a so-called “hump phenomenon” such as a two-step transistor subthreshold characteristic is observed, resulting in a significant decrease in product yield. Was there.

According to the present invention, since the n-type high-concentration layer is not formed by performing ion implantation after forming the groove in order to form the n-type high-concentration impurity layer at the bottom of the groove, a high-concentration layer is formed on the side surface of the groove. n
No type impurities are injected. Therefore, a transistor using the side surface of the groove can be favorably formed.

Similarly, since the method of diffusion from poly-Si does not have to be taken, the bottom corner of the groove does not serve as the channel region of the transistor, and the transistor characteristics are not abnormal due to the n-type impurity layer at the bottom of the groove. . Further, according to the present invention, the occupied area per cell is greatly reduced as compared with the conventional example, and high integration is possible. In addition, the gate length can be freely controlled by the depth of the hole,
By making the holes deeper, the short channel effect can be reduced. Further, since the entire side wall of the hole serves as a channel portion, the transistor operates with a relatively large current, and the memory operation speed increases. Further, since the capacitor portion does not face the substrate, it has good resistance to soft air. Further, according to the present invention, when the source electrode of the transistor is formed, ion implantation into the bottom of the groove, or the diffusion from the phosphorus-doped poly-Si does not need to be performed so that the transistor characteristics do not deteriorate, and the product yield, The reliability is significantly improved. Further, according to the present invention, a first impurity layer having a conductivity type opposite to that of the substrate is previously formed in a region of the semiconductor substrate which is to be a source of the MOS transistor, and the substrate is formed on the entire upper surface of the semiconductor substrate and the first impurity layer. Since a second impurity layer made of a semiconductor containing an impurity of the same conductivity type as the above is deposited by an epitaxial growth method, and then a hole is formed in the semiconductor substrate so as to reach the first impurity layer, the first impurity Even when the layer is formed by, for example, an ion implantation technique, it is possible to immediately recover the defects that may exist when the second impurity layer is formed thereon by the epitaxial growth method, and then reactive ion etching is performed. Thus, even if a defect occurs when forming the hole, it is possible to suppress the defect to such a degree that it can be sufficiently recovered. Therefore, the phenomenon in which defects concentrate on the corner of the bottom of the hole or in the vicinity thereof does not occur, so that from the capacitor lower electrode layer that is formed so as to contact the first impurity layer (source) and accumulates electric charges. It is possible to prevent the accumulated charges from leaking, and it is possible to stably hold the memory.

[Brief description of drawings]

FIG. 1 is a plan view and a schematic view for explaining a memory cell structure of the present invention, FIG. 2 is a process sectional view for explaining one embodiment of the present invention, and FIG. 3 is a conventional example. 4A, 4B, and 5 are sectional views for explaining the problems of the conventional method. P-type silicon substrate …… 11, 31, 41, 51 n ⁺ layer (drain) …… 14, 32, 52 SiO ₂ film …… 15, 33, 43 Hole …… 16 n ⁺ layer (source) …… 34 , 44, 59 Gate insulating film (SiO ₂ film) …… 17, 35, 54 Poly Si (word line) …… 18, 36, 55 Hole bottom …… 20, 58 Bit line …… 23, 42, 52 Epitaxial layer …… 13 N-type buried layer …… 12

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor memory device in which memory cells each comprising a MOS transistor and a MOS capacitor are integrated on a semiconductor substrate, wherein at least a part of a region serving as a source of the MOS transistor on the semiconductor substrate has a reverse conductivity to the substrate. A first impurity layer of the same type, and a second impurity layer made of a semiconductor containing impurities of the same conductivity type as that of the substrate is epitaxially grown on the entire upper surface of the semiconductor substrate and the first impurity layer. And the second step
Forming a third impurity layer having a conductivity type opposite to that of the substrate, which becomes the drain of the MOS transistor, on the surface of the first impurity layer, and penetrating the second and third impurity layers to form the first impurity layer. A step of forming a hole provided so as to reach the layer by reactive ion etching, and using a first impurity layer of a conductivity type opposite to that of the substrate provided at the bottom of the hole as a source, and a second impurity layer Forming a gate electrode layer of the MOS transistor through the hole through the first insulating film as a gate insulating film so that the channel region is formed and the third impurity layer is formed as a drain; and the hole is formed. A capacitor lower electrode layer on at least the gate electrode layer through a second insulating film so as to contact the first impurity layer at the opening provided in the bottom of the first impurity layer. Forming process, Serial manufacturing method of the semiconductor memory device in the capacitor lower electrode layer through the third insulating film, characterized by comprising a step of forming a capacitor upper electrode layer. 2. The gate electrode layer is a phosphorus-doped polycrystalline silicon film, the capacitor lower electrode layer is a phosphorus-doped polycrystalline silicon film, and the second insulating film is an oxide film, or The invention is a multilayer film including an oxide film, and the capacitor upper electrode layer is a phosphorus-doped polycrystalline silicon film.
13. The method for manufacturing a semiconductor memory device according to claim 1. 3. A capacitor lower electrode layer at least a surface layer is a metal layer, the third insulating film is an insulating film including at least a high dielectric constant film, and at least the third upper electrode layer of the capacitor upper electrode layer. The method for manufacturing a semiconductor memory device according to claim 1, wherein the region in contact with the insulating film is a metal layer.