JPH0348656B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device in which an insulator is buried around semiconductor elements that are formed in an integrated manner to isolate the elements.

[Technical background of the invention and its problems]

Semiconductor devices using silicon as a semiconductor, particularly complementary MOS semiconductor devices, are extremely promising as future ultra-high-density semiconductor devices because of their low power consumption and high noise margin.

The drawback of conventional complementary MOS (hereinafter referred to as CMOS) semiconductor devices is that they are formed on the same semiconductor substrate.
In order to electrically isolate the channel MOS transistor and the p-channel MOS transistor and prevent the latch-up phenomenon, it is necessary to form them at a distance of, for example, 10 μm or more, which prevents an increase in the degree of integration. As an attempt to improve this drawback, a technique is known in which the periphery of a MOS transistor is surrounded by burying an insulating material such as an oxide.
An example of this will be explained using FIG. 1. A resist mask 12 is formed on an n-type silicon wafer 11 by a normal photolithography process, and a reactive ion etching (hereinafter referred to as RIE) process is used to form a resist mask 12 in an element isolation region with a width of about 1.5 μm and a depth of about 5 μm. a to form the groove 13. Subsequently, a silicon oxide film 14 is deposited on the entire surface of the wafer by a CVD process, and a fluid material 15, such as photoresist, is further applied thereon to flatten the surface b. Next, under conditions where the etching rates of the fluid substance 15 and the silicon oxide film 14 are equal, etching is performed by RIE until the surface of the semiconductor wafer 11 is exposed, and the silicon oxide film 14 is buried in the groove 13. Thereafter, a resist mask 16 is again formed by a normal photolithography process, and impurity ions are implanted into the n-channel MOS transistor formation region to form a p-well 17. Thereafter, an n-channel MOS transistor is formed in the p-well 17 and a p-channel MOS transistor is formed in the n-type region adjacent to the p-well 17 by normal steps.

However, in this method, since the width of the trench 13 in which the insulator for element isolation is buried is formed in the RIE process, it is extremely difficult to reduce the width to 1 μm or less, and the area taken up by the element isolation region is extremely difficult to reduce. is large, and is still insufficient from the perspective of improving the degree of integration. Further, since the width of the trench 13 is narrower than its depth, the insulator cannot be completely buried, and cavities are generated inside, which affects the reliability and electrical characteristics of the device. Furthermore, in the step of forming the p-well 17, the resist mask 16 as an ion implantation mask is used to form the buried silicon oxide film 1.
Positioning must be achieved with a high accuracy of 4.

[Purpose of the invention]

In view of the above points, the present invention reliably embeds an insulator in an element isolation region with an extremely small width, and forms semiconductor regions of a predetermined conductivity type in a self-aligned manner in each region divided by this insulator. An object of the present invention is to provide a method for manufacturing a semiconductor device that enables high-density integration of elements.

[Summary of the invention]

In the method of the present invention, a recess is formed in a predetermined element formation region of a semiconductor wafer, only the side walls of the recess are covered with an insulating film, and then a single crystal semiconductor layer is flatly buried in the recess, and each part divided by the insulating film is A feature is that an element is formed in a semiconductor region.

〔Effect of the invention〕

According to the present invention, first, the insulating film embedded in the element isolation region can be made to have a thickness of 1 μm or less by forming, for example, a thermal oxide film to cover the sidewalls of the recesses formed in the semiconductor wafer. It's easy. Therefore, the area occupied by the element isolation region on the surface of the semiconductor wafer becomes extremely small, making it possible to integrate elements at a high density. Second, unlike the conventional method of filling the entire narrow trench with an insulating film, no cavities are generated inside the element isolation region, and a semiconductor device with excellent reliability and electrical isolation characteristics can be obtained. Thirdly, by burying a semiconductor layer in the recess in a self-aligned manner using an epitaxial growth method, it is possible to make the regions separated by an insulating film have different conductivity types, which is complicated as in the past. Each element forming region can be made into a semiconductor layer of a desired conductivity type without requiring a mask alignment process. Fourth, in the present invention, only the side walls of the recess are covered with an insulating film, so crystallization progresses from the entire bottom of the recess, making it possible to bury a homogeneous single crystal semiconductor layer and achieve device characteristics close to those of the bulk. You can get it. In particular, when the present invention is applied to a CMOS semiconductor device, a significant effect can be obtained in that the latch-up phenomenon can be reliably prevented and the devices can be integrated at high density.

[Embodiments of the invention]

FIG. 2 is a diagram showing the manufacturing process of one embodiment.
A silicon wafer 21 in which a p-type layer 21 ₂ is epitaxially grown on the entire surface of an n-type silicon substrate 21 ₁ is prepared, a resist mask 22 is formed on the surface by a photolithography process, and predetermined elements are formed by an RIE process. a forming a recess 23 in the area; The recess 23 has steep side walls, and its depth is greater than the thickness of the p-type layer 21 ₂ . Next, the resist mask 22 is removed and an insulating film is formed only on the side walls of the recess 23.
There are various methods for this, but in this example it was carried out as follows. First, a thermal oxide film 24 with a thickness of approximately 5000 Å is formed over the entire surface of the wafer. Next, RIE is performed in an atmosphere of CF ₄ and H ₂ to remove the oxide film 24 on the side wall of the recess 23.
Leave only one thing and remove the other c. In that case, by utilizing anisotropic etching, which is a feature of RIE, the structure shown in the figure can be created. Thereafter, an n-type silicon layer 25 is formed on the entire surface to be thicker than the depth of the recess 23 by epitaxial growth, and then a resist film 26 is applied so that the surface is flat. After that, by RIE again, the resist film 2
6 and the silicon layer 25 are uniformly etched until the surface of the p-type layer 21 ₂ is exposed, and the n-type silicon layer 25 is buried flat in the recess 23 e. And thermal oxide film 2
Gate electrodes 28 1 and 28 ₁ made of polycrystalline silicon are formed on each of the p-type and n-type regions separated by polycrystalline silicon through gate oxide films 27 ₁ and 27 ₂ by a normal process.
28 ₂ and sequentially form n ⁺ type layers 29 ₁ and 29 ₂ and p ⁺ type layers 30 ₁ and 30 ₂ which will become the source and drain. Finally, although not shown, a CVD oxide film is formed, contact holes are made, and electrode wiring is formed to complete the CMOS semiconductor device.

According to this embodiment, the thickness of the thermal oxide film 24 used for element isolation can be controlled by the oxidation rate (determined by temperature and time), so the width of the element isolation region is determined by the patterning accuracy. Compared to the conventional method, the width of the element isolation region can be made extremely narrow by controlling the film thickness to, for example, 1 μm or less, thereby achieving high-density integration of CMOS semiconductor devices. In addition, since element isolation is performed using a stable thermal oxide film, it has excellent reliability and electrical characteristics.
A CMOS semiconductor device is obtained. Further, unlike the conventional method of forming a p-well or n-well by selective diffusion, the p and n element forming regions are formed in a self-aligned manner without requiring a complicated mask alignment process.
Furthermore, by forming the recess 23 deeper than the thickness of the p-type layer 21 ₂ , the thermal oxide film 24 in the element isolation region
becomes deeper, and the latch-up phenomenon is reliably prevented. In addition, since the insulating film 24 is formed only on the side walls of the recess 23, crystallization progresses from the entire bottom surface of the recess during epitaxial growth, making it possible to bury a homogeneous single crystal semiconductor layer, resulting in device characteristics close to those of the bulk. can be obtained.

In this example, normal epitaxial growth was used, but selective epitaxial growth techniques may also be used. Furthermore, there is a concern that the formed n-type silicon layer 25 has poor crystallinity, especially in the part that contacts the thermal oxide film 24, but it will be annealed in a later thermal process during element formation, and will become a sufficiently high-quality crystal. So there is no problem. If the annealing effect is not sufficient in the heat treatment in the element forming process, it is also effective to add a separate single crystallization process such as laser annealing, electron beam annealing, or thermal annealing. Further, if such a single crystallization process is added, the n-type silicon layer 25 may be deposited in the form of a polycrystalline layer or an amorphous layer instead of using the epitaxial growth method.

Further, in the above embodiment, a wafer in which a p-type layer was epitaxially grown on an n-type substrate was used.
Of course, the p-type layer may be a diffusion layer, and the conductivity type of each layer may be reversed from that in the embodiment.

Next, another embodiment of the present invention will be described with reference to FIG. A thermal oxide film 32 is formed on the surface of an n-type silicon wafer 31, and a resist mask 33 formed by a photolithography process is used to form a thermal oxide film 32.
After etching 2, the silicon wafer 31 is etched to a depth of about 5 μm using RIE to form a recess 34 with steep side walls, and then a p ⁺ layer 35 is formed at the bottom of the recess 34 by a boron ion implantation process. form a. After removing the resist mask 33, a thermal oxide film 36 with a thickness of approximately 5000 Å is formed on the surface of the silicon wafer 31b. At this time, the recess 34
The thermal oxide film 32' in other areas becomes thicker. Next, a polycrystalline silicon film 37 containing a high concentration of boron is formed on the entire surface of the wafer by CVD.
C. heat treatment is applied to diffuse boron in the polycrystalline silicon film 37 into the thermal oxide film 36. Through this step, an oxide film 38 is formed on the surface of the polycrystalline silicon film 37, and then the oxide film 38 and the polycrystalline silicon film 37 are removed by etching.
Next, RIE is performed in an atmosphere of CF ₄ and H ₂ to remove the thermal oxide film of 5000 Å. When etching is performed by RIE, the etching proceeds in a direction perpendicular to the substrate surface, so the thermal oxide film 36 on the side wall of the recess 34 remains unetched, and a portion equivalent to a thickness of approximately 5000 Å also remains in the area other than the recess 34. is etched, but a thermal oxide film 32' of 2000 to 3000 Å remains unetched, leaving the wafer surface at the bottom of the recess 34 exposed. Next, a p-type silicon layer 39 is epitaxially grown over the entire surface of the wafer. At this time, the silicon layer 39 is replaced by the thermal oxide film 3.
2' and 36 are polycrystalline silicon, but in the recess 34 where the silicon wafer 31 is exposed, it is a single crystal layer. Next, a resist film 40, which is a fluid film, is applied to the entire surface to flatten the surface f. In this case, an epitaxially formed silicon layer, 39
Since there is a level difference of approximately 5 μm on the surface, first fill in a resist film selectively on the recess 34 using a normal photolithography process, and then apply a resist film over the entire surface again to ensure that the surface is flat. be done. Then, when the resist film 40 and the silicon layer 39 are uniformly etched under conditions where the etching speed of the resist film 40 and the silicon layer 39 are the same, the silicon layer 39 is evenly embedded in the recess 34g.
When the thermal oxide film 32' left on a part of the surface of the silicon wafer 31 is etched and removed, a silicon layer 39 of the opposite conductivity type to that of the wafer is embedded in a part of the silicon wafer 31, and A state is obtained in which a thermal oxide film 36 with a thickness of about 5000 Å surrounds the wafer 31, and a p ⁺ layer 35 of a conductivity type opposite to that of the wafer 31 is buried at the bottom. Next, when the surface of this wafer is annealed using, for example, a laser, the silicon layer 39 is single-crystalized up to the portion in contact with the thermal oxide film 36, and at the same time, the silicon layer 39 in which the boron diffused in the thermal oxide film 36 is single-crystalized. Diffuse inside. Since the thickness of the thermal oxide film 36 for element isolation is very thin, this diffused boron prevents the surroundings of the side walls of the buried silicon layer 39 from being inverted due to the influence of the potential of the adjacent region. After this, as in the previous embodiment, n-channel and p-channel MOS transistors are formed in each of the p and n regions, respectively.
A CMOS semiconductor device is obtained.

As in the previous embodiment, this embodiment is also a CMOS transistor with excellent reliability and electrical characteristics, which is highly integrated by reducing the area occupied by the element isolation region.
A semiconductor device is obtained. Further, according to this embodiment, impurities are diffused in advance into the thermal oxide film 36 for element isolation, so that the periphery of the silicon layer 39 embedded in the recess 34 is connected to the adjacent element via the thin thermal oxide film 36. This prevents reversal due to the influence of the electric potential, resulting in stable characteristics. Also, the recess 34
Since the p ⁺ layer 35 is embedded in the bottom of the layer, the effect of suppressing the latch-up phenomenon is large.

Note that as a method for introducing impurities into the thermal oxide film 36 for element isolation, oblique ion implantation may be used instead of diffusion from the polycrystalline silicon film. In addition, in the step of flatly embedding the silicon layer in the recess, the silicon layer 3 is placed in the state shown in FIG. 3e.
The difference in etching speed between the single crystal portion on the recessed portion 34 and the other polycrystal portion may be used to reduce the difference in level by etching in advance, and then the next flattening film may be formed.

FIG. 4 shows an example of a device configuration formed in this manner. FIG. 4a shows a plan view of the CMOS, and FIG. 4b shows its circuit diagram. For convenience, the same reference numerals as in FIG. 2 are given. In the figure, an n formed in the p-type layer 21 ₂
Channel MOS transistor T and p-channel MOS transistor made in n-type silicon layer 25
The CMOS is configured with _T2 . If the surface of the recess formed by etching is covered with an insulating film and a part of the insulating film on the bottom is removed using a mask,
Even with epitaxial growth, it is difficult to fill the inside of the recess with a homogeneous single crystal, and a large depression is formed on the growth surface at the edge of the recess. The threshold value of a MOS transistor formed in such a silicon layer decreases at the edge. Therefore, as mentioned above, for example
When a CMOS circuit is constructed, there is a problem in that leakage occurs in the load side transistor _T1 , increasing power consumption. However, in the present invention, since the single-crystal semiconductor layer is embedded flatly, there is also the secondary effect that disconnection of wiring can be prevented and that deterioration in characteristics does not occur. The present invention is not limited to CMOS semiconductor devices, but is applicable to ordinary p-channel devices.
It is useful not only for MOS and n-channel MOS, but also for integrated formation of bipolar transistor circuits, I ² L circuits, and the like. Furthermore, as an insulating film formed on the sidewalls of the recess for element isolation, in addition to a thermal oxide film, a thermal nitride film by direct nitriding, an oxide film or a nitride film by CVD, etc. can be used, and the controllability is sufficient compared to conventional methods. Very small element isolation regions can be formed.
Furthermore, various methods can be used to form the insulating film on the side walls of the recessed portions, such as tilting the wafer and depositing the insulating film obliquely.

[Brief explanation of drawings]

Figures 1 a to d are diagrams for explaining the conventional CMOS manufacturing process, Figures 2 a to f are diagrams for explaining the CMOS manufacturing process of an embodiment of the present invention, and Figures 3 a to h are diagrams for explaining the CMOS manufacturing process of an embodiment of the present invention. Figures 4a and 4b are diagrams for explaining the CMOS manufacturing process of another embodiment, and are a plan view and a circuit diagram for explaining the embodiment of the present invention. 21... Silicon wafer, 21 ₁ ... N-type silicon substrate, 21 ₂ ... P-type layer, 22... Resist mask, 23... Concavity, 24... Thermal oxide film (insulating film for element isolation), 25... ...n-type silicon layer, 26
...Resist film (flattening film), 31...n-type silicon wafer, 32, 32'...thermal oxide film, 33...
...Resist mask, 34...Concavity, 35...p ⁺
Layer, 36...Thermal oxide film (insulating film for element isolation), 3
7... Polycrystalline silicon film, 38... Thermal oxide film, 3
9...p-type silicon layer, 40... resist film.

Claims (1)

[Claims] 1. A step of forming a recess in a predetermined element formation region of a semiconductor wafer, a step of covering only the sidewalls of the recess with an insulating film, a step of flatly embedding a single crystal semiconductor layer in the recess, and a step of covering the side walls of the recess with an insulating film. 1. A method of manufacturing a semiconductor device, comprising the step of forming an element in each semiconductor region divided by a film. 2. The semiconductor wafer has a second conductivity type semiconductor layer formed on the entire surface of the first conductivity type semiconductor substrate,
The recess is formed to a depth that reaches at least the first conductivity type semiconductor substrate, and the semiconductor layer embedded in the recess is of the first conductivity type, and the semiconductor layer is a first conductivity type and a second conductivity type semiconductor separated by the insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein MOS transistors of different conductive channels are formed in each region. 3. The semiconductor wafer is of a first conductivity type, and the semiconductor layer embedded in the recess is of a second conductivity type,
MOSs with different conductive channels are provided in the first and second conductive type semiconductor regions separated by the insulating film.
A method for manufacturing a semiconductor device according to claim 1, which comprises forming a transistor. 4. The step of covering only the side walls of the recess with an insulating film is as follows:
A semiconductor device according to claim 1, wherein a thermal oxide film is formed on the entire surface of a semiconductor wafer in which a recess is formed, and is removed by anisotropic dry etching, leaving the thermal oxide film only on the side walls of the recess. Production method. 5. The step of forming a recess in the semiconductor wafer includes:
A thermal oxide film is formed on the entire surface of the wafer in advance, a resist mask is formed on it, and the resist mask is used to etch the thermal oxide film and the exposed surface of the semiconductor wafer. In the process of covering only with an insulating film, after removing the resist mask, a thermal oxide film is again formed on the entire surface of the wafer, and then a polycrystalline semiconductor film containing impurities is deposited on top of it, and the impurities are diffused into the thermal oxide film. , and then the polycrystalline semiconductor is removed and the thermal oxide film is etched by anisotropic dry etching leaving only the sidewalls of the recesses together with the semiconductor wafer surface. . 6. The step of embedding a semiconductor layer in the recess includes epitaxially growing or depositing a semiconductor layer to a thickness greater than the depth of the recess on the entire surface of the semiconductor wafer in which the recess is formed, and then applying a planarizing film on top of the semiconductor layer to make the surface flat. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after depositing the planarizing film and the semiconductor layer, the entire surface of the planarizing film and the semiconductor layer is etched under etching conditions such that the etching rate of both is substantially equal.