JPS6238869B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a silicon gate MOS transistor.

FIG. 1 shows a typical example of a semiconductor device including an N-channel type silicon gate MOS transistor according to the prior art. 1 is a P-type silicon substrate,
2 is an insulating layer made of a silicon oxide film, 3 is a gate insulating layer, 4 and 5 are sources formed by diffusing phosphorus,
Drain diffusion layer, 6 a gate electrode made of polycrystalline silicon, 7 a wiring layer made of polycrystalline silicon,
8 and 9 are wiring layers made of aluminum, and 12 and 13 are openings for electrical connection between the source/drain diffusion layers 4 and 5 and the aluminum wiring layers 8 and 9. In general, in silicon gate MOS transistor structures, disconnections in the aluminum wiring layer that cross the polycrystalline silicon layer greatly reduce the yield rate of products, but in normal technology, polycrystalline silicon A method is adopted in which the surface of the corner portion 10 or 11 of the silicon oxide film covering the gate 6 or the polycrystalline silicon wiring layer 7 is covered with a phosphor glass layer having smooth corners to prevent disconnection of the aluminum wiring layers 8 and 9. has been done. This phosphorus glass layer with smooth corners is formed by heating the phosphorus glass layer grown on the surface of the silicon oxide layer covering silicon at a high temperature of about 1000°C when forming the source/drain diffusion layers 4 and 5 in a high temperature phosphorus atmosphere. It can be obtained by heat treatment and melting. As mentioned above, it is not convenient to form the source and drain diffusion layers 4 and 5 by diffusing phosphorus in order to prevent disconnection at the polycrystalline silicon step portions 9 and 10 of the aluminum wiring layers 8 and 9. However, since the diffusion coefficient of phosphorus is relatively large, there is a drawback that the junction depth between the source and drain diffusion layers 4 and 5 becomes large. For example, if phosphorus is diffused into the source and drain regions and then the aforementioned heat treatment for melting the phosphorus glass is performed at 1000°C for 30 minutes, the depth of the source and drain diffusion layers 4 and 5 will be approximately 1.5μ.
m, and at the same time, the effective channel length becomes about 3 μm shorter than the width of the gate electrode 6 because it diffuses and penetrates directly under the gate electrode 6 from both sides of the source and drain. On the other hand, in general, if the effective channel length of a MOS transistor is 1 to 2 μm or less, it is difficult to obtain normal operation by punch-through. Improving the density means that the source and drain diffusion layers 4 and 5
This was difficult to achieve with a structure formed by diffusing phosphorus. Figure 2 shows a conventional N-channel silicon gate MOS that uses arsenic to form shallow source and drain junctions to improve integration density.
1 shows a semiconductor device including a transistor. 101
1 is a P-type silicon substrate, 102 is an insulating layer made of a silicon oxide film, 103 is a gate insulating layer, 104, 1
05 is a source and drain diffusion layer containing arsenic as an impurity; 106 is a gate electrode made of polycrystalline silicon; 107 is a wiring layer made of polycrystalline silicon; 108 and 109 are wiring layers made of aluminum; 110 , 111 indicate a portion where the aluminum wiring layer crosses the stepped portion of the polycrystalline silicon layer. In the structure shown in FIG. 2, since the sources and drains 104 and 105 are formed using arsenic, which has a relatively small diffusion coefficient, as an impurity, the progress of diffusion during heat treatment after forming the sources and drains is small, and the diffusion coefficient is approximately 0.5 μm. It is easy to obtain the source and drain diffusion layers 104 and 105 with the junction depth. Therefore, the phenomenon in which the effective channel length decreases due to the infiltration of the source and drain diffusion layers directly under the gate electrode 106 is suppressed, and when the width of the gate electrode 106 is 3.5 μm, the effective channel length is 2.5μm, which is good.
It exhibits MOS transistor characteristics and allows MOS transistors to be integrated at high density. However, in the structure shown in FIG. 2, since phosphorous glass is not formed on the surface of the silicon oxide layer covering the polycrystalline silicon, the steps formed by the polycrystalline silicon become steep, and the aluminum electrodes 108 and 109 become polycrystalline. The disconnection rate at the portion beyond the silicon step portions 110 and 111 increased significantly, greatly reducing the yield rate. Also, the source and drain diffusion layers 104 and 10
When the junction depth of No. 5 is 1.0 μm or less, the source,
Drain diffusion layers 104 and 105 and aluminum wiring layer 1
A portion 112 that makes electrical connection with 08, 109,
In the region 113, silicon and aluminum are replaced at a relatively low temperature, and by heat treatment at 450° C. for 30 minutes, aluminum partially passes through the source and drain diffusion layers 104 and 105 and diffuses, reaching the silicon substrate 101. This phenomenon, so-called alloy spike, increases leakage, making it difficult to obtain source and drain electrodes with good breakdown voltage.

An object of the present invention is to provide an effective method for manufacturing a semiconductor device that eliminates the drawbacks of the prior art.

The present invention is characterized by the steps of forming a thick first silicon oxide layer and a thin second silicon oxide layer adjacent to the first silicon oxide layer on the main surface of a P-type semiconductor substrate; forming a gate electrode of polycrystalline silicon on a predetermined region of the second silicon oxide layer, and forming a first wiring layer of polycrystalline silicon on a predetermined region of the first silicon oxide layer; Using the first silicon oxide layer as a mask, arsenic is introduced into the semiconductor substrate through the second silicon oxide layer by ion implantation, and a first nitrogen gas is introduced from the bottom of the gate electrode to the first silicon oxide layer.
forming an aperture in the second silicon oxide layer over a predetermined portion of the first N-type region; and transferring phosphorus to the first N-type region through the aperture at high temperature. The first N is diffused into a predetermined portion of the mold region and
The phosphorus glass is grown by forming a second N-type region deeper than the type region and simultaneously growing phosphorus glass on the surface of the silicon oxide layer covering the gate electrode and the first wiring layer, and performing high-temperature heat treatment. a step of melting to smooth the stepped portion and at the same time diffusing the arsenic and phosphorus introduced into the semiconductor substrate to form a source and drain of a predetermined shape;
The silicon oxide layer in the opening caused by the phosphorus diffusion is removed, and the second N layer in the source and drain is removed.
forming a second wiring layer connected to the mold region and extending over the smoothed phosphor glass on the first wiring layer.

The present invention minimizes the penetration of the source and drain diffusion layers directly under the polycrystalline silicon electrode, and is therefore suitable for high-density integration of MOS transistors, and is suitable for aluminum wiring in the polycrystalline silicon step. An N-channel silicon gate MOS field-effect semiconductor device that significantly reduces layer disconnections, prevents aluminum intrusion at the junctions between the aluminum wiring layer and the source and drain diffusion layers, and has normal source and drain breakdown voltages. This provides an efficient manufacturing method.

An embodiment of the present invention is shown in FIG. 3, and the features of the present invention will be explained. As shown in FIG. 3a, a relatively thick silicon oxide layer 202, for example, 1.0 μm thick, is formed on the surface of a single-crystal P-type silicon substrate 201, and then a portion of the silicon oxide layer is selectively removed. , a gate insulating layer 203 is formed. The gate insulating layer 203 is, for example, a silicon oxide layer with a thickness of 500 Å. Next, a gate electrode 204 and a wiring layer 205 made of polycrystalline silicon are formed. Next, arsenic is implanted into the silicon substrate 201 by ion implantation to form the source and drain diffusion layers 20.
6,207 is formed. During the ion implantation, the thick oxide film 202 and gate electrode 204 have a masking effect, so that the source and gate electrodes are implanted only at predetermined positions.
Drain diffusion layers 206 and 207 are formed. The above method is a conventionally well-known method, and other conventional methods, for example, using single crystal silicon epitaxially grown on sapphire as the silicon single crystal substrate 201, or using a polycrystalline silicon gate electrode in advance. It can also be doped with phosphorus, arsenic, etc. Next, as shown in FIG. 3b, openings 20 are provided for electrically connecting the source and drain diffusion layers 206 and 207 to the external aluminum wiring layer.
Form 8,209. Then, as shown in FIG. 3c, from the openings 208 and 209, for example,
Phosphorus is diffused into the silicon substrate 201 at a high temperature of 1000° C. to form the source and drain diffusion layers 20.
N-type diffusion regions 210, 211 deeper than 6,207
form. Through the phosphorus diffusion process, the silicon substrate 201 and the polycrystalline silicon layers 204 and 205
Phosphorous glass grows on the surface of the silicon oxide layer that covers the surface of the silicon oxide layer. Next, when heat treatment is performed at 1000° C. for about 20 minutes, the phosphor glass is easily melted, and the steep steps on the surface are smoothed. In particular, the stepped portions 212 and 213 formed by the polycrystalline silicon gate electrode 204 and the polycrystalline silicon wiring layer become smooth. Through the heat treatment, arsenic and phosphorus are removed from the silicon substrate 201.
source and drain diffusion layers 201 and 211 having a final junction depth of approximately 0.5 μm and a phosphorus diffusion layer 21 having a junction depth of approximately 1.5 μm.
0,211 is obtained. In the example shown in FIG. 3c, the phosphorus diffusion layers 210 and 211 are formed to penetrate through the source and drain diffusion layers 206 and 207.
07 and the phosphorus diffusion layers 210, 211, and the phosphorus diffusion layers 210, 211 do not penetrate directly under the gate electrode 204, their arrangement can be freely determined. Next, as shown in FIG. 3d, the silicon oxide layer produced by the phosphorus diffusion is removed using a known selective removal technique to form openings 208 and 209 directly above the phosphorus diffusion layers 210 and 211. Form. Next, through normal aluminum vapor deposition and selective removal processes, aluminum wiring layers 214 and 215 are formed as shown in FIG. 3e.
N-channel type silicon gate MOS
Completes field effect semiconductor device. According to the structure shown in FIG. 3e, the source and drain diffusion layers 206 and 207 have a relatively small diffusion coefficient.
Since arsenic is used as an impurity, it is possible to suppress the junction depth to, for example, about 0.5 μm, and therefore the penetration of the source/drain diffusion layers 206 and 207 directly under the polycrystalline silicon gate electrode 204 is also suppressed. The reduction in effective channel length is also approximately 1.0μ, and the polycrystalline silicon gate electrode 204 is
It is easy to make the width 4.0 μm or less. In addition, all electrical connections between the source and drain diffusion layers 206 and 207 and the aluminum wiring layers 214 and 215 are made through the phosphorus diffusion layers 210 and 211, which have a deeper junction depth than the source and drain diffusion layers. Aluminum electrodes 214 and 2 are formed by infiltration of aluminum toward the silicon substrate 201 through the holes 208 and 209.
15 and the silicon substrate 201 is prevented, and source and drain electrodes having good breakdown voltage can be obtained. Moreover, the polycrystalline silicon gate electrode 20
4, and the step portions 212 and 213 on the surface of the polycrystalline silicon wiring 205 are smoothed by phosphorus glass, so that the disconnection rate of the aluminum wiring layers 214 and 215 is significantly reduced.

As described above, according to the structure of the semiconductor device manufacturing method of the present invention, it is possible to obtain a densely integrated semiconductor element, such as an N-channel type silicon gate MOS field effect element, with low leakage current and good characteristics with a high yield rate. I can do it. Further, according to the manufacturing method of the present invention, the step of forming a phosphorus diffusion layer deeper than the source/drain diffusion layer and the step of smoothing the steps formed by the polycrystalline silicon gate electrode and the polycrystalline silicon wiring layer can be performed in the same step. This allows the process to be shortened and costs to be reduced.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are sectional views each showing a semiconductor device according to the prior art. FIGS. 3a to 3e are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps. In the figure, 1, 101, 201... P-type silicon substrate, 2, 102, 202... Insulating layer,
3,103,203...gate insulating layer, 4,5...
... Source and drain diffusion layers formed by diffusing phosphorus, 6, 106, 204 ... Gate electrode, 7, 1
07,205...polycrystalline silicon wiring layer, 8,
9, 108, 109, 214, 215... Aluminum wiring layer, 10, 11, 110, 111, 2
12,213...Corner part of insulating layer, 12,1
3, 112, 113, 208, 209... Connection opening, 104, 105... Source/drain region formed by diffusing arsenic, 206, 207...
A portion of the source and drain regions formed by introducing arsenic, 210, 211 . . . a portion of the source and drain regions formed by introducing phosphorus.

Claims (1)

[Claims] 1. Forming a thick first silicon oxide layer and a thin second silicon oxide layer adjacent to the first silicon oxide layer on the main surface of a P-type semiconductor substrate, and forming the second silicon oxide layer. forming a polycrystalline silicon gate electrode on a predetermined region of the first silicon oxide layer, and forming a polycrystalline silicon first wiring layer on a predetermined region of the first silicon oxide layer;
Arsenic is introduced into the semiconductor substrate by ion implantation through the second silicon oxide layer using the second silicon oxide layer as a mask, and arsenic is introduced into the semiconductor substrate from the bottom of the gate electrode.
forming a first N-type region up to the silicon oxide layer; forming an opening in the second silicon oxide layer on a predetermined portion of the first N-type region;
Phosphorus is diffused into a predetermined portion of the first N-type region through the opening at high temperature to form a second N-type region deeper than the first N-type region, and at the same time, the gate electrode and the first A process of growing phosphorus glass on the surface of the silicon oxide layer covering the wiring layer, and performing high temperature heat treatment to melt the phosphorus glass and smooth the stepped portion, while at the same time diffusing arsenic and phosphorus introduced into the semiconductor substrate. forming a source and drain of a predetermined shape, and removing the silicon oxide layer in the opening caused by the phosphorus diffusion, connecting the source and drain to the second N-type region, and forming a second wiring layer extending over a smoothed phosphor glass on the first wiring layer.