JP2001244324A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a device by surely rounding the shape a trench corner. SOLUTION: A method for manufacturing a semiconductor device with a separating method of trench elements includes a step of; 1) forming a mask 3 for trench formation on a silicon substrate surface 1; 2) a step of converting a surface of trench formation area to amorphous structure 5 by ion implantation of Ge through the mask; 3) a step of forming a trench 6 on the silicon substrate 1; 4) a step of oxidizing a trench wall surface; and 5) and a step of forming an element separation film by filling the trench with an oxide film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of isolating a semiconductor device, and more particularly to a conventional selective oxidation method (LOCOS).
Element isolation method (Shallow T)
(Rench Isolation method: hereinafter referred to as STI method).

[0002]

2. Description of the Related Art In recent years, with the increase in the density and integration of semiconductor devices, miniaturization of elements has been promoted. In order to miniaturize the element and achieve high density and high integration, it is important to miniaturize the element isolation region at the same time as the element itself.

[0003] Conventional element isolation techniques include a selective oxidation method (LO
COS method) has been used. When the LOCOS method is used, even when a fine pattern with a processing limit of lithography and etching is formed, oxidation in the lateral direction progresses and the width of the element isolation region is widened. However, there is a problem that oxidation does not proceed and element isolation becomes incomplete. As described above, LOC
In element isolation by the OS method, reduction of the isolation width is becoming a limit. In addition, it is becoming difficult to process a fine pattern in the uneven portion due to the unevenness in the element isolation portion. Because of these problems, a new device isolation technology has been sought. Recently, STI has been used instead of the LOCOS method.
An element isolation technique by the method has been studied.

For example, the STI method disclosed in Japanese Patent Application Laid-Open No. 9-8118 will be described with reference to FIGS. 7 (a) to 7 (c).

(1) A silicon oxide film 52 as a pad oxide film, a silicon nitride film 53, a polysilicon film 54 and a silicon oxide film 55 are sequentially formed on a single crystal silicon substrate 51, and then these are formed by a lithography process. A trench 56 is formed from the film to the semiconductor substrate 51 (see FIG. 7A).

(2) In the trench 56 and on the substrate 51,
After depositing a BPSG film 57 as an insulating film for element isolation, the BPSG film 57 is heat-treated and reflowed.
The surface of the G film 57 is planarized (see FIG. 7B).

(3) BPSG film 57, silicon oxide film 5
5. The polysilicon film 54 and the silicon nitride film 53 are sequentially etched back, and finally a BPSG film (element isolation insulating film) 57 is buried in the trench 56 of the semiconductor substrate 51 (see FIG. 7C).

In the method of forming an element isolation film by the STI method, a trench (groove) is formed on a semiconductor substrate 51 as described above.
The step of forming 56 and burying an insulator therein is performed. The minimum element isolation width in the STI method can be reduced to the same level as the processing limit of lithography or etching.

When element isolation is performed by the trench element isolation method, if the corners of the trench are sharp, there is a problem that a stress in the process causes a defect in the silicon substrate and a junction leak increases. In particular, if the corner on the substrate surface side is sharp, transistor characteristic fluctuations such as the reliability of the gate oxide film formed on top of this corner being degraded and the reverse narrow channel effect occurring due to the concentration of the electric field from the gate electrode being caused. There was a problem that occurred.

[0010]

In order to solve these problems, if measures are taken to round the corners by oxidizing the surface of the silicon substrate after the formation of the trench, oxidation in a high-temperature oxidizing atmosphere or removal of HCl or the like is required. It was oxidized in the added atmosphere.

In order to round the corners of the trench, an oxidizing atmosphere to which a high temperature or HCl is added is required. In these cases, however, there is a problem in controllability since the oxidation rate is increased.

On the other hand, when element isolation is performed by the trench element isolation method, the impurity concentration of the substrate impurity at the corners and sidewalls of the trench is reduced with respect to other regions by transiently accelerated diffusion of the substrate impurity after ion implantation. Lower.
Therefore, an inverse narrow channel effect appears in which the threshold voltage of the transistor decreases as the transistor width decreases.

In order to solve these problems, after forming the trench, a substrate impurity is obliquely ion-implanted into the side wall to prevent the impurity concentration from decreasing. However, in this case, in order not to create an unimplanted area depending on the pattern direction,
There is a problem that the injection time becomes long because the injection direction needs to be rotated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has as its object to improve the reliability of a device by reliably rounding the shape of a corner of a trench.

[0015]

According to the present invention, in a method of manufacturing a semiconductor device using a trench element isolation method, a step of forming a trench forming mask on a surface of a silicon substrate and a step of forming a trench forming region using the mask are performed. The method includes a step of amorphizing a surface, a step of forming a trench in a silicon substrate, a step of oxidizing a trench wall surface, and a step of backfilling the trench with an oxide film to form an element isolation film.

Using a trench forming mask, silicon (Si) or germanium (Ge) may be ion-implanted to make the surface of the trench forming region amorphous.

The corner can be rounded at the time of etching the trench due to the difference in the etching rate between the amorphous region and the crystalline region.

Further, the corner can be rounded at the time of re-oxidation after the etching of the trench due to the difference in the oxidation rate between the amorphous region and the crystalline region.

As described above, when the region where the corner of the trench is to be rounded is made amorphous by ion implantation of Si, Ge, or the like in advance, this region has a lower oxidation rate and etching rate than the crystalline silicon substrate. Increase. Therefore, corners can be efficiently rounded by a method such as oxidation or etching.

Further, the present invention may be configured so that an impurity of the same type as that of the substrate is ion-implanted into the amorphous region.

As described above, by implanting impurities of the same type as the substrate into the amorphized region, the heat treatment after the formation of the trench allows enhanced diffusion by interstitial silicon generated in the pre-amorphous region in large numbers. Substrate impurities are diffused into the corners and side wall regions of the trench, so that the inverse narrow channel effect of the transistor can be suppressed.

Further, according to the present invention, an impurity of the same type as the substrate is ion-implanted by using a trench forming mask,
What is necessary is just to comprise so that the surface of a trench formation area may be made amorphous.

As described above, by amorphizing the substrate by injecting impurities of the same type as the substrate, the step for rounding the corner and the step for obtaining the enhanced diffusion effect are performed simultaneously. , The number of steps can be reduced.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention, and FIGS. 2A to 4J are cross-sectional views showing steps of a method of manufacturing a semiconductor device of the present invention.

In FIG. 1, reference numeral 1 denotes a silicon substrate, 10 denotes an element isolation insulating film buried in a trench (groove) 6 formed by the STI method, 7 denotes an oxide film provided on the wall surface of the trench 6, and 8 denotes It shows a rounded corner. Hereinafter, a method for manufacturing a semiconductor device of the present invention will be described.

Step 1 (see FIG. 2A): A silicon oxide film 2 (film thickness 10 to 150) is formed on a p-type single crystal silicon substrate 1 by using, for example, a thermal oxidation method using dry oxygen at 950 ° C.
nm), and a CVD method (low-pressure CVD) is formed thereon.
Silicon nitride film 3 (200 n) using a CVD method, a plasma CVD method, a high-density plasma CVD method, or a normal pressure CVD method.
m).

Step 2 (see FIG. 2B): The silicon nitride film 3 and the silicon oxide film 2 are etched by using a resist formed by photolithography as a mask corresponding to the element isolation region to form a trench. A hard mask for forming is formed. This etching is performed, for example, with Cl ₂
Is performed by RIE etching using a gas mainly composed of After completion of the etching, the resist is removed.

Step 3 (see FIG. 2C): silicon nitride
Gel is formed in the STI formation region opened using the film 3 as a mask.
Manganese (Ge), for example, at 20 keV and a dose of 5 ×
10 ¹⁴/ Cm^TwoIon implantation is performed to this silicon substrate 1
Amorphized layer 5 is formed on the surface of. This ion injection
Not only in the depth direction of the substrate but also in the lateral direction of the substrate
Amorphous area is wide about 40% in the depth direction.
You.

Step 4 (see FIG. 2D): Using the silicon nitride film 5 as a mask, for example, HBr and oxygen (O ₂ )
RIE using a gas such as
A groove 6 of about 50 nm is formed.

Step 5 (see FIG. 3E): The silicon substrate 1 after the formation of the groove is subjected to, for example, about 950 ° C. dry oxygen for about 1 hour.
Oxidation is performed by 5 nm to form oxide film 7. At this time, since the oxidation rate of the corner portion of the STI shown in FIG. 8 is improved by the pre-amorphization, the oxidation progresses and the corner becomes round.

Step 6 (see FIG. 3F): The groove 6 is formed by silicon dioxide (SiO ₂ film) by, for example, HDP-CVD.
9 is deposited to a thickness of about 200 nm and backfilled.

Step 7 (see FIG. 3G): The insulating film 9 deposited on the silicon nitride film 3 is removed by using the CMP method, and the entire upper surface of the silicon nitride film 3 is exposed. At this time, the thickness of the insulating film 3 is reduced by the CMP. In addition,
Instead of the CMP method, anisotropic overall etch-back may be performed to planarize. When this etch back is used, the silicon nitride film 3 serves as an etching stopper due to a difference in etching rate between the silicon oxide film 9 and the silicon nitride film 3, and the etch back is terminated when the silicon nitride film 3 is exposed.

Step 8 (see FIG. 3H): The silicon nitride film 33 is selectively removed using phosphoric acid heated to 160 ° C. The etching rate of hot phosphoric acid for the silicon nitride film and the silicon oxide film changes depending on the temperature, but the silicon nitride film is about 30 to 40 times faster. With the insulating film 2 and the element isolation film 7 exposed, the insulating film 2 is removed.

Step 9 (see FIG. 4 (i)): In the transistor forming region on the surface of the silicon substrate 1 from which the insulating film 2 has been removed,
A gate oxide film 11 is formed.

Step 11 (see FIG. 4 (j)): A conductive layer 12 such as doped polysilicon is formed on the gate oxide film 11. The gate electrode is formed by patterning the conductive layer 12.

In the transistor thus formed, since the corner portion of the trench can be rounded with good control, the reliability of the gate oxide film formed in this portion does not deteriorate, and the semiconductor device of high quality and high reliability can be obtained. Can be provided.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
The embodiment will be described with reference to FIG. Note that the description of the same steps as those in the first embodiment is omitted here to avoid duplication of description.

[0039] Based on the same process shown from step 1 described above in step 3, the forming region of the STI that opens a silicon nitride film 3 as a mask, germanium (Ge), for example a dose in the 20keV 5 × 10 ¹⁴ / Ion implantation of about ² cm ^{2 is performed} to form an amorphous layer 5 on the surface of the silicon substrate 1.

Step 4 (see FIG. 5A): For example, Cl ₂
Substrate 1 by RIE using a gas mainly composed of
Then, a groove having a depth of about 350 nm is formed. At this time, since the etching rate of the STI corner portion shown in FIG. 8 is increased by the amorphization, the etching proceeds in the lateral direction and the corner becomes round.

Step 5 (refer to FIG. 5B): The silicon substrate 1 after the formation of the groove is subjected to, for example, 950 ° C. dry oxygen for about 1 hour.
Oxide is performed by 5 nm to form an oxide film 7.

After step 6, the same steps as those of the first embodiment are performed to form the element isolation region 10, the gate insulating film, and the conductive layer, thereby completing the semiconductor device.

In the transistor formed according to the second embodiment, since the corner of the trench can be rounded with good control, the reliability of the gate oxide film formed in this portion does not deteriorate, and high quality can be obtained. A highly reliable semiconductor device can be provided.

(Third Embodiment) Next, a third embodiment of the present invention will be described.
Will be described with reference to FIG. Note that the description of the same steps as those in the first embodiment is omitted here to avoid duplication of description.

[0045] Based on the same process shown from step 1 described above in step 3, the forming region of the STI that opens a silicon nitride film 3 as a mask, germanium (Ge), for example a dose in the 20keV 5 × 10 ¹⁴ / Ion implantation of about ² cm ^{2 is performed} to form an amorphous layer 5 on the surface of the silicon substrate 1.

Step 3a (see FIG. 6A): After forming the amorphized layer 5, substrate impurity ions are implanted. In the case of a p-type substrate, for example, boron (B) is
At a keV, a dose of about 1 × 10 ¹⁴ / cm ^{2 is} implanted. In the case of an n-type substrate, a phosphorus (P) is implanted at a dose of about 1 × 10 ¹⁴ / cm ² at 30 keV. At this time,
The lateral implantation area extends approximately 30% of the depth.

Step 4 (see FIG. 6B): Using the silicon nitride film 5 as a mask, for example, HBr and oxygen (O ₂ )
RIE using a gas such as
A groove 6 of about 50 nm is formed. At this time, an amorphous region 5 ′ into which the substrate impurity is introduced remains at the corner of the groove.

Step 5 (see FIG. 6 (c)): The silicon substrate 1 after the formation of the groove is subjected to, for example, 950.degree.
Oxidation is performed by 5 nm to form an oxide film 7 '. At this time, due to the heat of about 700 ° C. at the time of ramp-up, the substrate impurities implanted in the step 3a diffuse into the STI side wall and the substrate surface by transient enhanced diffusion by interstitial silicon generated in the pre-amorphous step, and the impurities in this region Increase concentration. Further, since the oxidation rate of the corner portion of the STI shown in FIG. 8 is improved by pre-amorphization, the oxidation proceeds and the corner becomes round.

In step 6 and subsequent steps, the element isolation region 10, the gate insulating film, and the conductive layer are formed by the same steps as those in step 1 of the first embodiment, and a semiconductor device is formed.

In the transistor formed according to the third embodiment as described above, it is possible to suppress the occurrence of the inverse narrow channel effect due to the decrease in the substrate impurity concentration at the corner of the STI. Further, since the corner portion of the trench can be rounded with good control, the reliability of the gate oxide film formed in this portion does not deteriorate, and a high-quality and high-reliability semiconductor device can be provided.

In the above-described embodiment, Ge is ion-implanted to make the substrate surface amorphous. However, silicon (Si) atoms may be ion-implanted to make amorphous.

In the third embodiment, after the amorphous layer 5 is formed, the same type of impurity as that of the substrate is ion-implanted. However, the same type of impurity as that of the substrate is formed by using a trench forming mask. Impurities may be ion-implanted and the surface of the trench formation region may be made amorphous, and the substrate surface may be made amorphous and the impurities may be introduced into the substrate simultaneously. At this time, the impurity to be ion-implanted can be easily made amorphous by using arsenic or antimony if the substrate is n-type and by using indium if the substrate is p-type.

As described above, by amorphizing the substrate by injecting impurities of the same type as the substrate, the step for rounding the corner and the step for obtaining the enhanced diffusion effect are performed simultaneously. , The number of steps can be reduced.

[0054]

According to the present invention, since the corner portion of the STI can be rounded with good controllability, high quality and high reliability can be achieved without causing a problem such as deterioration in reliability of a gate oxide film formed in this portion. Semiconductor device can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing a method of manufacturing the semiconductor device according to the first embodiment of the present invention step by step.

FIG. 3 is a cross-sectional view showing a method of manufacturing the semiconductor device according to the first embodiment of the present invention step by step.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention step by step.

FIG. 5 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention for each process.

FIG. 6 is a sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention for each process.

FIG. 7 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device for each process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate, 2 Silicon oxide film 3 Silicon nitride film 5 Amorphization layer 6 Groove (trench) 7 Oxide film

Claims (6)

[Claims] In a method of manufacturing a semiconductor device using a trench element isolation method, a step of forming a trench forming mask on a surface of a silicon substrate, and a step of using the mask to amorphize the surface of a trench forming region. A method for manufacturing a semiconductor device, comprising: a step of forming a trench in a silicon substrate; a step of oxidizing a trench wall surface; and a step of back-filling the trench with an oxide film to form an element isolation film. 2. Using a trench forming mask, ion-implant silicon (Si) or germanium (Ge),
2. The method according to claim 1, wherein the surface of the trench formation region is made amorphous. 3. The method according to claim 1, wherein an impurity of the same type as the substrate is ion-implanted into the amorphous region. 4. The surface of a trench formation region is made amorphous by ion-implanting an impurity of the same type as that of a substrate using a trench formation mask.
13. The method for manufacturing a semiconductor device according to item 5. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the corner is rounded at the time of etching the trench, based on a difference in etching rate between the amorphous region and the crystalline region. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the corner is rounded at the time of re-oxidation after the etching of the trench, due to a difference in oxidation rate between the amorphous region and the crystalline region.