JPH11145273A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably obtain a structure wherein abnormality of transistor characteristic is not generated by side-etching a first insulation film below a second insulation film which becomes a stopper, selectively exposing and removing a corner part of a semiconductor substrate and rounding a corner part by thermally oxidizing the substrate. SOLUTION: A silicon board 1 is etched by using a silicon oxide film 4 as a mask and a groove 7 is formed. When silicon oxide films 2, 4 are etched by hydrofluoric acid, the silicon oxide film 2 is side-etched and a second opening part 6a is formed. A surface of an exposed part of the silicon substrate 1 is etched by using a silicon nitride film 3 as a mask and a corner of a shoulder part and a bottom part of the groove 7 are removed. Thereafter, a shoulder part can be thereby rounded readily by carrying out thermal oxidation. Accordingly, field concentration at a shoulder part is relaxed, transistor characteristic is stabilized, and high performance and high density of a semiconductor device are realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having an element isolation region.

[0002]

2. Description of the Related Art As one of element isolation methods in a semiconductor device, there is a technique called LOCOS (LOCal Oxidation of Silicon). In this technique, a predetermined portion of the surface of a silicon substrate is selectively thermally oxidized using a silicon nitride film as an oxidation prevention mask, and an oxide film formed thereby is used as an element isolation region. The oxide film formed in the element isolation region is generally called a field oxide film.

However, there are the following two problems in element isolation by the LOCOS method. One of them is called bird's beak. This is because, when the silicon substrate is thermally oxidized by the LOCOS method, oxygen enters from the edge of the antioxidant mask and the oxide film on the surface of the silicon substrate bites under the antioxidant mask. Is called a bird's beak because it is shaped like a bird's beak.

Since the bird's beak enlarges the field oxide film region, there arises a problem that the element isolation region is narrowed. The other is a phenomenon called a thinning (THINNING) effect, in which the field oxide film becomes thinner as the width of the element isolation region becomes narrower. This is caused by reducing the amount of oxygen supplied through the opening when the size of the opening of the antioxidant mask for supplying oxygen to the element isolation region of the silicon substrate is reduced. For this reason, there is a problem that element isolation is not perfect.

As described above, when the thickness of the field oxide film is reduced, the effect of introducing impurities introduced immediately below the field oxide film in order to prevent the formation of the channel of the parasitic MOS transistor may be lost. These problems have been conventionally known, but when the element size is large, the influence of bird's beak and thinning is small.

However, these problems have become apparent as not only elements but also element isolation regions have been miniaturized with the miniaturization of semiconductor devices. Since it is difficult to reduce the size of the bird's beak in accordance with the miniaturization of the element, the rate of the bird's beak eroding the element formation region and reducing the size of the element formation region increases. When the width of the element isolation region is set to 1 μm or less, a thinning effect is also remarkably exhibited, and the thickness of the field oxide film in a narrow element isolation region becomes less than half of that in a wide element isolation region. is there.

As an element isolation structure which does not cause such a problem, there is known a trench isolation in which a trench is formed in a silicon substrate and an insulator or polycrystalline silicon is embedded therein. This method has been conventionally applied to a bipolar transistor LSI requiring deep element isolation. However, since neither bird's beak nor thinning occurs, application to a MOS transistor LSI is also progressing.

The MOS transistor LSI does not require the element isolation as deep as the bipolar transistor LSI.
STI (Shal) that performs element isolation with a relatively shallow groove of about μm
A structure called low Trench Isolation) is used. Next, an element isolation method using STI will be described with reference to FIG.
5 and FIG.

First, as shown in FIG. 15A, after a first thermal oxide film 102 having a thickness of 10 nm is formed on a silicon substrate 101, a silicon nitride film 103 having a thickness of 150 nm is formed on the entire surface by a CVD method. Then, the window of the resist mask 104
By 105, the element isolation region S is determined. After that, FIG.
5B, the silicon nitride film 103 under the window 105,
The first thermal oxide film 102 is etched to form an opening 103a, and a 0.5 μm
RIE (Reactive Ion Etching) of the groove 106 with a depth of about
It is formed by a method.

Next, as shown in FIG. 15C, after the resist mask 104 is removed, the inner wall of the groove 106 is thermally oxidized,
A second thermal oxide film 107 having a thickness of 5 nm is formed. And C
A silicon oxide film 108 having a thickness of 1 μm is formed on the entire surface by the VD method, and the trench 106 is filled with the silicon oxide film 108. After performing an appropriate heat treatment, as shown in FIG. 15D, the silicon oxide film 108 on the silicon nitride film 103 is removed by CMP (Chemical Mechanical Polishing) or RIE, and the silicon oxide film 108 is Leave only on it. In this case, the silicon nitride film 103 functions as a stopper layer.

Then, as shown in FIG. 16E, the silicon nitride film 103 is removed using phosphoric acid. Next, the first thermal oxide film 102 on the silicon substrate 101 is removed with hydrofluoric acid. Next, after the surface of the silicon substrate 101 is thermally oxidized to form a third thermal oxide film (not shown) on the entire surface, impurities are ion-implanted into a part of the silicon substrate 101, and the impurities are activated to form a well. After forming (not shown), the third thermal oxide film is removed with hydrofluoric acid.

Thereafter, as shown in FIG. 16F, after the surface of the element formation region of the silicon substrate 101 is thermally oxidized to form a gate oxide film 109, a gate electrode 110 is formed on the gate oxide film 109. Next, an impurity diffusion layer 111 serving as a source and a drain is formed on the silicon substrate 101 on both sides of the gate electrode 110 (in a direction perpendicular to the paper surface).

[0013]

By the way, after the trench 106 is filled with a silicon oxide film 108 and the silicon nitride film 103 is removed, the above-described hydrofluoric acid treatment is performed a plurality of times to bury the trench 106 in the trench 106. The portion of the silicon oxide film 108 protruding from the silicon substrate 101 is isotropically etched by hydrofluoric acid. When the silicon oxide film 108 is isotropically etched as described above, the silicon oxide film 108 buried in the groove 106 has concave portions 121 as shown in FIG.
Is formed.

Since such a recess 121 is formed between the element formation region and the element isolation region S, the groove 121
The upper edge (shoulder) of 106 is exposed. Therefore, the gate electrode formed over the element isolation region S
When a voltage is applied to 110, as shown in FIG. 17B, the shoulder at the edge of the groove 106 has a corner, so that the electric field E concentrates on the shoulder.

Thus, even if the gate voltage is low, the groove
Leakage current easily flows through the silicon substrate 101 near the shoulder of 106. That is, the state is the same as when a parasitic transistor having a low threshold is formed, and the MOS transistor has characteristics as shown in FIG. The phenomenon in which the threshold voltage is reduced by the parasitic MOS transistor and a "bump" appears on the curve of the gate electrode-drain current characteristic is called "hump" or "kink".

In order to reduce the leakage current of the parasitic transistor, it is proposed in B. DAVARI ET AL., IEDM 1988, PP.92-95, to perform ion implantation at the shoulder of the groove 106. However, according to this method, the impurity spreads not only to the shoulder of the groove 106 but also to the periphery thereof, so that the element formation region is narrowed. Also, as another method, the groove 10
It has been proposed to reduce the electric field concentration at the shoulder by thermally oxidizing and rounding the shoulder. But,
In order to round the shoulder of the groove 106, high-temperature oxidation near 1200 ° C. is required, and at such a temperature, a large-diameter semiconductor wafer is easily warped.

As another method, a method in which a polycrystalline silicon film is used as a stopper layer for CMP and RIE instead of the silicon nitride film 103 and the polycrystalline silicon film is used as it is as a gate electrode is disclosed in C. Chen et al. , IEDM 19
96 Published in PP.837-840. However, in this method, it is necessary to implant impurity ions for forming a well through the gate electrode and the gate oxide film, so that the gate oxide film is damaged.

The silicon oxide film 108 shown in FIG.
A method of forming an insulating sidewall on the side surface of a portion protruding from the silicon substrate 101 and filling the recess 121 with the insulating sidewall is described in PIERRE C. FAZAN ET A
L., IEDM 1993, PP.57-60. But,
In this method, when forming the sidewall, it is necessary to suppress the variation in the growth of the insulating film and the variation in the etch-back process of the insulating film, and it is difficult to form the sidewall with good controllability. Further, since the sidewall is formed by performing etch back before forming the gate oxide film, the surface of the silicon substrate is roughened by ion irradiation at the time of etch back, so that the influence on the gate oxide film is also concerned.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can obtain good transistor characteristics and can prevent defects in a semiconductor wafer.

[0020]

SUMMARY OF THE INVENTION As shown in FIGS. 1 to 5, the above-mentioned problem is solved by forming a first insulating film on a semiconductor substrate and forming the first insulating film on the first insulating film. Forming a second insulating film having an etching characteristic different from that of the first insulating film; forming a first opening in the second insulating film to define an element isolation region; The first through an opening
Etching the insulating film, forming a groove in the semiconductor substrate through the first opening, and forming the first insulating film on the first insulating film by using the second insulating film as a mask. Forming a second opening having an opening diameter larger than that of the opening, etching the semiconductor substrate using the first insulating film having the second opening as a mask, Forming a buried film extending on the second insulating film by burying the inside, and removing the buried film on the second insulating film using the second insulating film as a stopper. And a step of removing the second insulating film.

That is, according to the present invention, the first insulating film (oxide film) under the second insulating film (nitride film) serving as a stopper is side-etched to selectively expose the corners of the semiconductor substrate. Then, the corner is removed by etching the substrate,
Furthermore, since the corners can be easily rounded by thermally oxidizing the substrate, even when the shoulders of the active region are subsequently exposed, electric field concentration at the shoulders can be made less likely to occur, such as a hump. It is possible to stably obtain a structure that does not cause abnormal transistor characteristics.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] A first embodiment of the present invention is shown in FIGS. In the figure, reference numeral 1 is a p-type silicon substrate,
2 is a pad oxide film, 3 is a stopper layer, 4 is a silicon oxide film, 5 is a resist mask, 6 is a first opening, 6a is a second opening, 7 is a groove, 8 is a substrate protective layer, 9 is A silicon oxide film, 9a is a protrusion of the silicon oxide film, 10 is a well,
11 denotes a gate insulating film, 12 denotes a gate electrode, and 13 and 14 denote impurity diffusion layers.

1A to 5K are sectional views for explaining the method for fabricating the semiconductor device according to the present embodiment, and FIG. 6 is a sectional view showing a MOS transistor formed through the process for fabricating the semiconductor device according to the present invention. is there. Hereinafter, a method for manufacturing the semiconductor device of the first embodiment will be described with reference to the drawings. Referring to FIG. 1A, the main surface of p-type silicon substrate 1 is thermally oxidized to form a pad oxide film having a thickness of 5 to 5 on the main surface.
A 50 nm silicon oxide film 2 is formed. Then, CVD
Thickness of 40 to 150 nm to be a stopper layer
After the silicon nitride film 3 is formed, a silicon oxide film 4 having a thickness of 50 to 150 nm serving as a mask layer is formed on the entire surface by CVD at about 750 to 800 ° C.

Referring to FIG. 1B, a photoresist is applied to the entire surface, and exposure, development, and the like are performed.
Then, a resist mask 5 having a window 5a is formed. The width of the window 5a in the element isolation region X is, for example, 1 μm or less, and decreases to 0.2 μm or less as the miniaturization of the semiconductor element progresses. Then, using the resist mask 5 as a mask, the silicon oxide film 4, the silicon nitride film 3, and the silicon oxide film 2 are etched by RIE using a mixed gas of CF4, CHF3, and Ar or a mixed gas of CF4 and Ar to form a window. A first opening 6 is formed below 5a. Next, the resist mask 5 is removed.

Referring to FIG. 1C, using a silicon oxide film 4 as a mask, a mixed gas of HBr and O 2, HBr and CF 4
The silicon substrate 1 is etched by RIE using a mixed gas of O.sub.2 and O.sub.2 or a mixed gas of Cl.sub.2 and O.sub.2 to form a groove 7 having a depth of 0.3 to 0.5 .mu.m. At this time, the side surface of the groove 7 is inclined by adding O2 as a reaction gas, so that the electric field concentration on the shoulder (upper edge) of the groove 7 can be reduced by the inclination.

Referring to FIG. 2D, the silicon oxide films 2 and 4 are etched by 10 to 50 nm using hydrofluoric acid. At this time, since the silicon nitride film 3 is hardly etched, the silicon nitride film 3 is in an overhang state. The silicon oxide film 2 is side-etched to form a second opening 6a. In addition,
The amount of side etching of the silicon oxide film 2 may be such that the silicon nitride film 3 is not lifted off, and it is necessary that the etching amount is about 45% or less of the minimum active region width. For example, when the minimum active region width is 200 nm, side etching up to 90 nm is an allowable range.

Referring to FIG. 2E, using silicon nitride film 3 as a mask, C 2 / CF 4 (flow ratio 0.5 to 5), pressure 1 torr or less, preferably 700 to 750 mtorr.
The exposed surface of the silicon substrate 1 is etched by about 30 nm by the DE (Chemical Dry Etching) method, and the shoulder and the bottom corner of the groove 7 are removed. The present invention is characterized in that the corner of the shoulder of the groove 7 is removed by etching (CDE method). In the etching, it is extremely important that the silicon oxide film 2 is side-etched. is there.

FIG. 7 shows that the silicon substrate is etched using the silicon oxide film 2, the silicon nitride film 3, and the silicon nitride film 4 as a mask to form a groove 7, and then the silicon oxide film 2, the silicon nitride film 3, The state where the film 4 is removed is shown. Thereafter, when the silicon substrate 1 is etched by the CDE method, as shown by a dotted line,
At the bottom, but not at the shoulders. Although the reason for this has not been elucidated in detail, it is considered that isotropic etching is usually performed on the shoulder and deposition occurs on the bottom, and the etching rate is reduced.

Further, as shown in FIG. 1C, the present inventors also tried to etch the silicon substrate 1 by CDE without forming the silicon oxide film 2 after the formation of the groove 7. However, only the same shape as shown by the dotted line in FIG. 7 was obtained. That is, the side surfaces of the silicon oxide film 2 are etched to form the grooves 7.
The silicon substrate around the shoulder was selectively exposed, so that the corner of the shoulder could be etched, and the shoulder could be easily rounded by subsequent thermal oxidation. it is conceivable that.

Referring to FIG. 3F, a silicon oxide film (substrate protection layer) 8 having a thickness of 5 to 50 nm is formed on the inner wall surface of groove 7 of silicon substrate 1 by thermal oxidation at about 900 to 1050 ° C. Covers the inner surface of groove 7 with silicon oxide film 8.
Referring to FIG. 3G, CVD using a mixed gas of SiH4 and oxygen or a mixed gas of TEOS and ozone is used.
Silicon oxide film 9 having a thickness of about 0.6 to 1 μm
Is grown so that the silicon oxide film 9 covers the silicon nitride film 3 and the silicon oxide film 4 and is buried in the trench 7.

If necessary, after the growth of the silicon oxide film 9, the silicon oxide film 9 is densified by annealing at about 1000 ° C. Referring to FIG. 4H, silicon oxide films 9 and 4 are polished by CMP using silicon nitride film 3 as a stopper, whereby silicon oxide films 4 and 9 on silicon nitride film 3 are removed.

The polishing is performed with the silicon substrate 1 interposed between the rotating upper and lower platens (not shown). The rotation speed of the upper and lower platens is 20 rpm, the pressure between the upper and lower platens is 5 PSI, the back pressure is 5 PSI, and a slurry containing colloidal silica as a main component or a cerium oxide slurry is used as an abrasive. Under such conditions, the etching rate of the silicon nitride film 3 is small and this is the end point of polishing. When the polishing is completed, the silicon oxide film 9 remains only in the opening 6 and the groove 7 of the silicon nitride film 3. become.

When removing the silicon oxide film 9 constituting the above-mentioned element isolation structure from the silicon nitride film 3, CMP is used, but RIE using a mixed gas of CF4 and Ar is also applicable. Good. Referring to FIG. 4I, when the silicon nitride film 3 is removed with a hot phosphoric acid solution, a part of the silicon oxide film 9 filling the trench 7 appears on the silicon substrate 1 as a protrusion 9a. Since the shape of the projection 9a substantially matches the shape of the silicon nitride film 3, the silicon substrate 1 with a rounded upper corner and the thermal oxide film 9 are present immediately below the vicinity of the end of the projection 9a. I have.

The etching of the silicon nitride film 3 is performed as follows.
In addition to wet etching with hot phosphoric acid, CF4, C
Dry etching in which HF3, HBr, SF6, 02 or Ar gas is arbitrarily selected may be used. Referring to FIG. 5J, silicon oxide film 2 remaining on silicon substrate 1 is removed with diluted hydrofluoric acid, and the surface of silicon substrate 1 is thermally oxidized to grow a sacrificial oxide film (not shown). After a well 10 of one conductivity type is formed in the substrate 1 by ion implantation, the sacrificial oxide film is removed by dilute hydrofluoric acid.

The protrusion 9a of the silicon oxide film 9 is reduced in size by the two hydrofluoric acid treatments to form a recess as in the prior art. This is because the silicon oxide film formed by the CVD method is formed. This is because the etching rate of the silicon oxide film 8 formed by the thermal oxidation method is slower than that of the silicon oxide film 9 because the film quality is denser. However, in the steps of FIGS. 2E and 2F, since the corners of the groove 7 are already rounded, the electric field concentration at the corners can be suppressed even if the gate insulating film and the gate electrode are formed at these corners. .

Thus, the element isolation structure is completed by the silicon oxide film 9 buried in the trench 7. Referring to FIG. 5K, the surface of silicon substrate 1 is thermally oxidized to a thickness of 5
After forming a gate oxide film (gate insulating film) 11 nm and a gate electrode 12 from the element formation region Y to the element isolation region X, an impurity of the opposite conductivity type to the impurity in the silicon substrate 1 is formed on the gate electrode. The impurity diffusion layers 13 and 14 serving as a source and a drain are implanted into both sides of the
To form Thus, the step of forming the MOS transistor shown in FIG. 6 is completed.

The impurity to be ion-implanted into the silicon substrate 1 to form the impurity diffusion layers 13 and 14 is a p-type impurity (boron or the like) when the well 10 is an n-type, or a p-type impurity In the case of n-type impurities (phosphorus,
Arsenic, etc.). According to the present invention, after forming a groove in a semiconductor substrate, and before forming an oxide film filling the groove,
By performing a process of side-etching the oxide film under the silicon nitride film serving as a stopper and rounding off the exposed corners of the silicon substrate, electric field concentration at the shoulder portion is less likely to occur, and a low threshold parasitic is generated. The formation of a transistor can be prevented.

Second Embodiment In the first embodiment, the silicon oxide film 4 on the silicon nitride film 3 is used as a mask when the silicon substrate 1 is etched to form the trench 7. A resist layer may be used instead. In this case, the growth of the silicon oxide film 4 on the silicon nitride film 3 may be omitted.

Hereinafter, the second embodiment will be described in detail with reference to the drawings. A second embodiment is shown in FIGS. 8A to 10G. In the drawings, the same reference numerals denote the same components, and a description of the steps corresponding to FIGS. 1A to 6 will be omitted. 8A to 10G are sectional views for explaining the method for fabricating the semiconductor device according to the present embodiment. Hereinafter, a method for manufacturing the semiconductor device of the second embodiment will be described with reference to the drawings.

Referring to FIG. 8A, the main surface of p-type silicon substrate 1 is thermally oxidized to form a 10 nm-thick silicon oxide film 2 serving as a pad oxide film on silicon substrate 1. Next, a thickness of 40 to serve as a stopper layer is formed on the entire surface by CVD.
After forming a silicon nitride film 3 of about 150 nm, a photoresist is applied to the entire surface. Referring to FIG. 8B, a resist mask 5 is formed in the same manner as described in the first embodiment. Next, using the resist mask 5 as a mask,
The opening 6 is formed below the window 5a by etching the silicon nitride film 3 and the silicon oxide film 2 by RIE using a mixed gas of CF4 and CHF3 and Ar or a mixed gas of CF4 and Ar.

Referring to FIG. 8C, using a resist mask 5 as a mask, a mixed gas of HBr and O 2, HBr and CF 4
The silicon substrate 1 is etched by RIE using a mixed gas of O.sub.2 and O.sub.2 or a mixed gas of Cl.sub.2 and O.sub.2 to form a groove 7 having a depth of 0.3 to 0.5 .mu.m. After that, the resist mask 5 is removed. Referring to FIG. 9D, silicon oxide film 2 is etched by 10 to 50 nm with hydrofluoric acid. At this time, since the silicon nitride film 3 is hardly etched, the silicon nitride film 3 is in an overhang state. The silicon oxide film 2 is side-etched to form an opening 6a. FIG. 9E
In the same manner as described in the first embodiment, the exposed portion of the surface of the silicon substrate 1 is etched by CDE to remove the shoulder and the corner of the bottom of the groove 7. Referring to FIG. 10F, a silicon oxide film (substrate protection layer) 8 having a thickness of 5 nm is formed on the inner wall surface of groove 7 of silicon substrate 1 by thermal oxidation at about 900 ° C., thereby forming the inner surface of groove 7 with silicon. Cover with oxide film 8.

Referring to FIG. 10G, a silicon oxide film 9 having a thickness of about 0.6 to 1 μm is grown by a CVD method using a mixed gas of SiH 4 and oxygen or a mixed gas of TEOS and ozone. Thus, the silicon nitride film 3 is covered with the silicon oxide film 9 and buried in the trench 7. After the growth of the silicon oxide film 9, the silicon oxide film 9 is densified by annealing at about 1000.degree.

FIGS. 4H to 5 show the first embodiment.
Through the same steps as in K, a semiconductor device is manufactured. According to the present embodiment, since the groove 7 is formed in the silicon substrate using the resist mask 5 used for patterning the silicon nitride film 3 serving as a stopper, it is necessary to form a silicon oxide film on the silicon nitride film 3. In addition, the steps of forming a silicon oxide film and performing etching can be reduced.

[Third Embodiment] In the first and second embodiments, after the groove 7 is formed in the silicon substrate 1, the silicon oxide film 2 is side-etched, and further, the corner of the substrate is rounded. However, the present invention is not limited to this. After the groove 7 is formed after the side etching of the silicon oxide film 2, a process of rounding the corner of the substrate may be performed.

Hereinafter, a method of forming the groove 7 after the side etching of the silicon oxide film 2 and then rounding the corner of the substrate will be specifically described with reference to the drawings. A third embodiment of the present invention is shown in FIGS. In the drawings, the same reference numerals denote the same components, and FIG.
The description of the steps corresponding to A to FIG. 6 is omitted.

11A to 12D are process sectional views for explaining the method for fabricating the semiconductor device according to the present embodiment.
Hereinafter, a method for manufacturing the semiconductor device of the third embodiment will be described with reference to the drawings. Referring to FIG. 11A, a silicon oxide film 2 serving as a pad oxide film, a silicon nitride film 3 serving as a stopper layer, a silicon oxide film 4 serving as a mask layer, and an element isolation region X are formed on a main surface of a p-type silicon substrate 1. A resist mask 5 having windows 5a is sequentially formed, and the resist mask 5
The silicon oxide film 4, the silicon nitride film 3, and the silicon oxide film 2 are etched by RIE using
A shape similar to that shown in FIG. 1B is obtained.

Referring to FIG. 11B, resist mask 5 is removed, and silicon oxide film 2 is isotropically etched by dry etching using hydrofluoric acid or NF3 or NH3.
Etch 50 nm. At this time, since the silicon nitride film 3 is hardly etched, the silicon nitride film 3 is in an overhang state. Also, the silicon oxide film 2
The opening 6a is formed by side etching.

Referring to FIG. 12C, a mixed gas of HBr and O2 or a mixed gas of Cl2 and O2 is
The silicon substrate 1 is etched by RIE using the mixed gas of No. 2 to form a groove 7 having a depth of 0.5 μm. FIG.
2D, the silicon oxide film 2 is used as a mask and O
The exposed portion of the surface of the silicon substrate 1 is etched by about 30 nm by the CDE method using 2 / CF4 (flow rate ratio 5) to remove the shoulder and the corner of the bottom of the groove 7. Hereinafter, the first
Through the same steps as in FIGS. 4H to 5K in the embodiment,
A semiconductor device is manufactured.

Fourth Embodiment In the third embodiment, after the silicon oxide film 2 is side-etched, a groove 7 is formed using the silicon oxide film 4 on the silicon nitride film 3 as a mask, Was rounded off, but the silicon nitride film 3 may be used as a mask when forming the groove 7, and in this case, the growth of the silicon oxide film 4 on the silicon nitride film 3 may be omitted.

FIG. 13 and FIG. 14 show a fourth embodiment of the present invention.
Is shown in In the drawings, the same reference numerals denote the same components, and a description of the steps corresponding to FIGS. 1A to 6 will be omitted. FIGS. 13A to 14D are process cross-sectional views illustrating the method for manufacturing the semiconductor device according to the present embodiment.
Hereinafter, a method for manufacturing the semiconductor device of the fourth embodiment will be described with reference to the drawings.

Referring to FIG. 13A, p-type silicon substrate 1
Is thermally oxidized to form a 10 nm thick silicon oxide film 2 serving as a pad oxide film on the silicon substrate 1. Next, a thickness of 40 to serve as a stopper layer is formed on the entire surface by CVD.
After forming a silicon nitride film 3 of about 150 nm, a photoresist is applied to the entire surface. Next, the photoresist is exposed and developed, and a window 5a is formed in the element isolation region X.
Forming a resist mask 5 having
Using a mixed gas of CF4 and Ar as a mask
By E, the silicon nitride film 3 is etched to form an opening 6 below the window 5a.

Referring to FIG. 13B, after the resist mask 5 is removed, the silicon oxide film 2 is
Etch 50 nm. At this time, since the silicon nitride film 3 is hardly etched, the silicon nitride film is in an overhang state. Also, the silicon oxide film 2
The opening 6a is formed by side etching.

Referring to FIG. 14C, the silicon substrate 1 is etched by RIE using a mixed gas of HBr and O 2 or a mixed gas of Cl 2 and O 2 to form a groove 7 having a depth of 0.5 μm. Referring to FIG. 14D, using the silicon oxide film 2 as a mask, the exposed surface of the silicon substrate 1 is etched by about 30 nm by CDE using O2 / CF4 to remove the shoulder and bottom corners of the groove 7. I do.

Hereinafter, a semiconductor device is manufactured through the same steps as in FIGS. 4H to 5K in the first embodiment. Although the present invention has been described along the first to fourth embodiments, the present invention is not limited to these. Therefore, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0055]

As described above, according to the present invention, the shoulder of the groove formed in the semiconductor substrate can be easily rounded, electric field concentration at the shoulder hardly occurs, and the transistor characteristics are stabilized. To improve the performance of semiconductor devices.
It greatly contributes to high density.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view (part 1) of a semiconductor device illustrating a first embodiment of the present invention;

FIG. 2 is a process cross-sectional view (part 2) of the semiconductor device illustrating the first embodiment of the present invention;

FIG. 3 is a process sectional view (part 3) of the semiconductor device for explaining the first embodiment of the present invention;

FIG. 4 is a process sectional view (No. 4) of the semiconductor device for explaining the first embodiment of the present invention;

FIG. 5 is a process sectional view (part 5) of the semiconductor device for explaining the first embodiment of the present invention;

FIG. 6 is a cross-sectional view showing a MOS transistor formed through a manufacturing process of the semiconductor device of the present invention.

FIG. 7 is a cross-sectional view illustrating a state where a silicon substrate is etched by a CDE method.

FIG. 8 is a process sectional view (part 1) of a semiconductor device illustrating a second embodiment of the present invention.

FIG. 9 is a process sectional view (part 2) of the semiconductor device for explaining the second embodiment of the present invention;

FIG. 10 is a process sectional view (part 3) of the semiconductor device for explaining the second embodiment of the present invention;

FIG. 11 is a process cross-sectional view (part 1) of a semiconductor device illustrating a third embodiment of the present invention.

FIG. 12 is a process sectional view (part 2) of the semiconductor device for explaining the third embodiment of the present invention.

FIG. 13 is a process sectional view (part 1) of a semiconductor device for explaining a fourth embodiment of the present invention.

FIG. 14 is a process sectional view (part 2) of the semiconductor device for explaining the fourth embodiment of the present invention;

FIG. 15 is a cross-sectional view (part 1) illustrating an example of a manufacturing process of a conventional semiconductor device.

FIG. 16 is a cross-sectional view (part 2) illustrating an example of a process for manufacturing a conventional semiconductor device.

FIG. 17 is a cross-sectional view showing a defect formed in an oxide film for element isolation in a conventional semiconductor device manufacturing process.

18 is a transistor characteristic diagram of the MOS transistor shown in FIG.

[Explanation of symbols]

 Reference Signs List 1 p-type silicon substrate (semiconductor substrate) 2 silicon oxide film (pad oxide film) 3 silicon nitride film (stopper layer) 4 silicon oxide film 5 resist 6 first opening 6a, second opening 7 groove 8 silicon oxide Film (substrate protection layer) 9 Silicon oxide film 9a Protrusion of silicon oxide film 10 Well 11 Gate insulating film 12 Gate electrode 13, 14 Impurity diffusion layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenji Kiuchi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Motomori Miyajima 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Limited (72) Inventor Takashi Sakuma 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Limited

Claims (9)

[Claims] A step of forming a first insulating film over a semiconductor substrate; and a step of forming a second insulating film over the first insulating film, the second insulating film having different etching characteristics from the first insulating film. Forming a first opening in the second insulating film to define an element isolation region; etching the first insulating film through the first opening; Forming a groove in the semiconductor substrate by etching the semiconductor substrate through the first opening; and forming the first opening in the first insulating film using the second insulating film as a mask. Forming a second opening having an opening diameter larger than the opening diameter, etching the semiconductor substrate using the first insulating film having the second opening as a mask, and filling the trench. Forming a buried film extending on the second insulating film, and the second insulating film As a stopper, a method of manufacturing a semiconductor device, characterized in that it comprises a step of removing the buried layer on the second insulating film, and removing the second insulating film. 2. The method according to claim 1, further comprising the step of forming a thermal oxide film on the inner wall of the groove after forming the second opening and before forming the buried film.
The manufacturing method of the semiconductor device described in the above. 3. The method according to claim 1, further comprising, after the step of removing the second insulating film, a step of reducing a side portion of the buried film protruding from the semiconductor substrate. 13. A method for manufacturing a semiconductor device according to 4. The method according to claim 3, wherein said buried film is a silicon oxide film, and said buried film protruding from said semiconductor substrate is reduced in size by hydrofluoric acid. 5. The semiconductor device according to claim 1, wherein said first insulating film is formed of an oxide film, and said second insulating film is formed of a nitride film. Production method. 6. forming a mask layer on the second insulating film before forming the first opening; forming a third opening in the mask layer; Forming the first opening through the opening. The method according to claim 1, further comprising: forming the first opening through the opening. 7. The method according to claim 7, wherein the mask layer is formed by growing a silicon oxide film or applying a resist. The step of forming a groove in the semiconductor substrate includes selectively etching the semiconductor substrate using the mask layer as a mask. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the groove is formed by the following. 8. The method according to claim 1, wherein the removal of the buried film on the second insulating film is performed by polishing or anisotropic etching. 9. The etching of the semiconductor substrate is performed by CDE.
2. The method according to claim 1, wherein the etching is performed by an etching method.