CN105336608A - Formation method of MOS transistor - Google Patents
Formation method of MOS transistor Download PDFInfo
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- CN105336608A CN105336608A CN201410230889.2A CN201410230889A CN105336608A CN 105336608 A CN105336608 A CN 105336608A CN 201410230889 A CN201410230889 A CN 201410230889A CN 105336608 A CN105336608 A CN 105336608A
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Abstract
The invention discloses a formation method of a MOS transistor. The method comprises the following steps: providing a silicon substrate; forming multiple split shallow trenches in the silicon substrate, the region between adjacent shallow trenches being an active region; after the shallow trenches are formed, carrying out silicon ion implantation on the silicon substrate until a silicon-enriched layer at least disposed at the corners of the shallow trenches is formed; after the silicon ion implantation, filling the shallow trenches by use of an insulation material to form a shallow trench isolation structure; forming a gate medium layer on the silicon substrate of the active region; and forming a grid electrode on the gate medium layer. By using the formation method of the MOS transistor, the reliability of the formed MOS transistor can be improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of formation method of MOS transistor.
Background technology
In production of integrated circuits, isolation structure is a kind of important technology, formed element on a semiconductor substrate must with other element separation.Along with the progress of semiconductor fabrication techniques, shallow trench isolation instead of as conventional semiconductor devices partition methods such as local oxidation of silicon (LOCOS) gradually from (ShallowTrenchIsolation, STI) technology.
The formation method of existing fleet plough groove isolation structure generally comprises: at high-temperature oxydation boiler tube internal oxidition wafer (wafer and Semiconductor substrate), form pad oxide (PadOxide) and hard mask layer on a semiconductor substrate, etching semiconductor substrate forms multiple discrete shallow trench again, formed protruding between adjacent shallow trench, the silicon substrate of described convex top is active area; Adopt thermal oxidation technology to form lining oxide layer (Liner) in the bottom of shallow trench and sidewall afterwards, and on described lining oxide layer, form the insulating barrier for filling shallow trench; Then carry out each body structure surface of cmp (CMP) planarization, using hard mask layer as grinding stop layer, leave smooth surface, last again by hard mask layer and pad oxide removal, to form opening, open bottom exposed raised upper surface, for the making of subsequent technique.
Subsequent technique belongs to a part for the formation method of MOS transistor usually, generally includes: after the opening is formed, forms gate dielectric layer, gate dielectric layer forms grid at upper convex surface (i.e. open bottom).
But, when the gate dielectric layer formed at described active area upper surface, gate dielectric layer is positioned at the thickness of corner on shallow trench and is less than the thickness that gate dielectric layer is positioned at described active area (that is described projection) upper surface flat position, namely occurs that gate dielectric layer is positioned at the problem (gateoxidecornerthinningissue) that on shallow trench, corner's thickness reduces.In fact, the thickness that gate dielectric layer is positioned at corner on shallow trench can reduce more than 50%.And once there is described problem, performance of semiconductor device will be caused unstable, such as cause gate dielectric layer time breakdown (TimeDependentDielectricBreakdown, TDDB), particularly for Nonvolatile semiconductor device, if there is described problem, the reliability of Nonvolatile semiconductor device can be had a strong impact on.
For this reason, need a kind of formation method of new MOS transistor, be positioned to prevent gate dielectric layer the problem that on shallow trench, corner's thickness reduces.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of MOS transistor, substantially equal with the thickness being positioned at active area upper surface to make gate dielectric layer be positioned at the thickness of corner on shallow trench, thus the reliability of raising semiconductor device.
For solving the problem, the invention provides a kind of formation method of MOS transistor, comprising:
Silicon substrate is provided;
In described silicon substrate, form multiple discrete shallow trench, the region between adjacent described shallow trench is active area;
After the described shallow trench of formation, Si ion implantation is carried out to described silicon substrate, until form the silicon-rich layer being at least positioned at corner on described shallow trench;
After described Si ion implantation, adopt the full described shallow trench of filling insulating material, form fleet plough groove isolation structure;
The silicon substrate of active area forms gate dielectric layer;
Described gate dielectric layer forms grid.
Optionally, described silicon-rich layer is only positioned at bottom and the sidewall of described shallow trench.
Optionally, described silicon-rich layer is only positioned at the top side wall of described shallow trench.
Optionally, the silicon ion concentration that described Si ion implantation adopts is greater than or equal to 5E15atom/cm
2.
Optionally, the energy range that described Si ion implantation adopts is 1KeV ~ 30KeV.
Optionally, the energy range that described Si ion implantation adopts is 5KeV ~ 6KeV.
Optionally, the angular range that described Si ion implantation adopts is 0 ° ~ 30 °.
Optionally, described employing furnace oxidation technique forms described gate dielectric layer on the silicon substrate of described active area.
Optionally, the gas that described furnace oxidation technique adopts comprise oxygen and ozone at least one of them.
Optionally, the temperature range adopting furnace oxidation technique to adopt is 800 DEG C ~ 1050 DEG C.
Optionally, after the described shallow trench of formation, and before the described shallow trench of filling, be also included in the step that described shallow trench surface forms lining oxide layer.
Optionally, the gas forming the employing of described lining oxide layer comprises oxygen and nitrogen.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, after formation shallow trench, Si ion implantation is carried out to silicon substrate, until form the silicon-rich layer being at least positioned at corner on described shallow trench, because on shallow trench, corner has silicon-rich layer, thus on shallow trench, the silicon atom density of corner raises, thus ensure in the process of follow-up formation gate dielectric layer, the growth rate of gate dielectric layer corner on shallow trench improves, and then ensure that the final gate dielectric layer each several part thickness formed is substantially equal, improve the reliability of semiconductor device.
Further, the silicon ion concentration that described Si ion implantation adopts is greater than or equal to 5E15atom/cm
2, thus ensureing after described Si ion implantation, on shallow trench, the silicon atom density of corner is comparatively large, is substantially equal to gate dielectric layer growth rate surperficial on the active area to make gate dielectric layer growth rate of corner on shallow trench be increased to.
Further, the energy range that described Si ion implantation adopts is 1KeV ~ 30KeV.The energy demand that described silicon ion adopts is greater than 1KeV, can be injected into corner on shallow trench to make silicon ion.But meanwhile, the energy demand that described Si ion implantation adopts is less than 30KeV, ensure that the silicon ion injected is positioned at the more shallow position of corner on shallow trench, and then ensure that in subsequent gate dielectric layer forming process, the silicon ion injected can be oxidized.
Further, the energy range that described Si ion implantation adopts is 5KeV ~ 6KeV.In the energy range of 5KeV ~ 6KeV, described silicon ion injection degree of depth of corner on described shallow trench is more shallow, and comparatively concentrated, and Si ion implantation can be avoided the impact of other doped regions on silicon substrate.
Accompanying drawing explanation
Fig. 1 to Fig. 8 is cross-sectional view corresponding to each step of formation method of embodiment of the present invention MOS transistor.
Embodiment
As described in background, when the active area of existing MOS transistor formation method between adjacent shallow trench forms gate dielectric layer, the gate dielectric layer thickness being usually located at corner on shallow trench is less, cause the gate dielectric layer time breakdown (TimeDependentDielectricBreakdown of MOS transistor, TDDB), have a strong impact on the reliability of the reliability of semiconductor device, particularly Nonvolatile semiconductor device.
On shallow trench, the gate dielectric layer thickness of corner is less, this is because gate dielectric layer is very fast in the growth rate of upper convex surface, and the growth rate of corner is slower on shallow trench.Trace it to its cause, active area upper surface is generally <100> crystal orientation, on this direction, crystal orientation, silicon atom density is higher, therefore gate dielectric layer growth rate is very fast, and be positioned on the direction, crystal orientation of corner's silicon atom on shallow trench, silicon atom density is lower, and therefore gate dielectric layer growth rate is slower.
For this reason, the invention provides a kind of formation method of new MOS transistor, described formation method is after formation shallow trench, Si ion implantation is carried out to corner on shallow trench, thus the silicon atom density of corner on shallow trench is raised, follow-up in gate dielectric layer forming process, the growth rate of gate dielectric layer corner on shallow trench improves, and it is substantially equal to be increased to the growth rate surperficial on the active area with gate dielectric layer, therefore, the gate dielectric layer of final formation can cover protruding upper corner well, thus improves the reliability of semiconductor device.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The embodiment of the present invention provides a kind of formation method of MOS transistor, incorporated by reference to referring to figs. 1 to Fig. 8.
Please refer to Fig. 1, silicon substrate 100 is provided, and form pad oxide 110 on silicon substrate 100, pad oxide 110 is formed hard mask layer 120.
In the present embodiment, silicon substrate 100 material can be monocrystalline silicon or polysilicon, and silicon substrate 100 also can be insulating barrier silicon-on, silicon Germanium compound structure or silicon gallium compound structure etc.
In the present embodiment, the material of pad oxide 110 can be silicon dioxide.The thickness of pad oxide 110 can be
such as be specifically as follows
pad oxide 110 can be formed by thermal oxidation technology growth.Thermal oxidation technology can be rapid thermal oxidation process (rapidthermaloxidation, RTO), or adopts the conventional anneal process (annealingprocess) of oxygen.
In the present embodiment, the material of hard mask layer 120 can be silicon nitride or carbonitride of silicium etc., and hard mask layer 120 can be single layer structure also can for sandwich construction.The thickness of hard mask layer 120 can be 100nm ~ 200nm, such as, be specifically as follows 150nm.Hard mask layer 120 can be formed on pad oxide 110 by deposition process or epitaxial growth method.Described deposition process can be chemical vapour deposition technique (CVD) or Low Pressure Chemical Vapor Deposition (lowpressureCVD, LPCVD) deposition etc.
Please refer to Fig. 2, form multiple discrete shallow trench in silicon substrate 100, the region between adjacent described shallow trench is active area (mark).Show shallow trench 101 and shallow trench 102 in Fig. 2 representatively, between shallow trench 101 and shallow trench 102, the silicon substrate 100 of (namely between adjacent shallow trench) is protruding (mark), and described convex top is described active area.
The described active area of part is surrounded with dotted line circle 103 in Fig. 2, be corner on shallow trench (in Fig. 2 with the upper corner of shallow trench 101 for representative) by the described active area that dotted line circle 103 surrounds, therefrom known, corner that is shallow trench top side wall on shallow trench.
In the present embodiment, the concrete forming process of shallow trench 101 and shallow trench 102 can comprise: spin coating photoresist layer (not shown) on hard mask layer 120, and form channel patterns by exposure imaging, on hard mask layer 120, namely form the photoresist layer of patterning; With described photoresist layer for mask, etching hard mask layer 120 and pad oxide 110 form opening (not shown), and silicon substrate 100 surface is exposed in the bottom of described opening; There is the hard mask layer 120 of described opening and pad oxide 110 for mask, shallow trench 101 and shallow trench 102 is formed along described opening etching silicon substrate 100, in silicon substrate 100 between shallow trench 101 and shallow trench 102, the part being positioned at described convex top is described active area.
In the present embodiment, reactive ion etching process (reactiveionetching can be passed through, RIE) or high-density plasma (highdensityplasma, HDP) etching technics etching hard mask layer 120, pad oxide 110 and silicon substrate 100.The gas that corresponding etching technics adopts can be the mist of hydrogen bromide, helium, oxygen and carbon hexa fluoride.Wherein the flow of hydrogen bromide can be 27sccm ~ 33sccm, can be specifically 30sccm; The flow of Helmholtz operator can be 34sccm ~ 40sccm, can be specifically 37sccm; The flow of sulphur hexafluoride can be 5sccm ~ 7sccm, can be specifically 6sccm.The pressure of etching can be 10mTorr ~ 20mTorr, can be specifically 15mTorr; The power adopted during etching can be 1100w ~ 1300w, can be specifically 1w; Etching voltage can be 136V ~ 164V, can be specifically 150V; The time of etching can be 50s ~ 65s, and concrete example is as 60s.The degree of depth of shallow trench 101 and shallow trench 102 controls by etch period.The described degree of depth can be selected according to actual needs, and the degree of depth of such as shallow trench 101 and shallow trench 102 can be between 300nm to 500nm, can be specifically 400nm.
Please refer to Fig. 3, form lining oxide layer 130 at shallow trench 101 and shallow trench 102 surface (comprising bottom and sidewall).
In the present embodiment, the material of lining oxide layer 130 can be silica, silicon oxynitride or their combination.The thickness of lining oxide layer 130 can be
form the upper corner round and smoothization (cornerrounding) that lining oxide layer 130 can make shallow trench; the shallow trench surface formed by above-mentioned etching technics is usually more coarse; shallow trench surface recovery smooth (repairing aforementioned etching technics to the surface damage that brings of shallow trench surface) can be made by forming lining oxide layer 130, and form lining oxide layer 130 and can also provide protection for follow-up filling step.
Lining oxide layer 130 can adopt thermal oxidation technology (thermaloxidationprocess) or chemical vapor deposition method (CVD) to be formed, and on-site steam growth technique (ISSG) also can be adopted to be formed.
In the present embodiment, the gas forming lining oxide layer 130 employing can comprise oxygen and nitrogen.The gas adopted owing to forming lining oxide layer 130 has nitrogen, and therefore, lining oxide layer 130 surface formed has nitrogen, and lining oxide layer 130 surface has the anti-etching ability that nitrogen can improve lining oxide layer 130.
In other embodiments of the invention, the process forming lining oxide layer also can comprise: first form the first lining oxide layer on shallow trench surface, first lining oxide layer thickness is less, then the first lining oxide layer (removing by hydrofluoric acid) is removed, thus make shallow trench surface become smooth, and increase the opening diameter of shallow trench, the second lining oxide layer is formed again afterwards on shallow trench surface, due to through the first lining oxide layer formation and remove process, therefore, second lining oxide layer better quality, surface is more smooth.
Please refer to Fig. 4, with hard mask layer 120 and pad oxide 110 for mask, Si ion implantation is carried out to the bottom of described shallow trench (comprising shallow trench 101 and shallow trench 102) and sidewall, is positioned at bottom described shallow trench and the silicon-rich layer 100a of sidewall to be formed.
In the present embodiment, after the silicon ion that silicon ion source produces by described Si ion implantation accelerates, shallow trench lower surface and sidewall surfaces described in high fast direction, and squeeze into the below of shallow trench lower surface and sidewall surfaces.When silicon ion enters described shallow trench lower surface and sidewall surfaces, silicon ion collides with the silicon atom in silicon substrate 100, will get into original intracell, thus forms silicon-rich layer 100a.
Mention before this specification, corner and shallow trench top side wall on described shallow trench, therefore, the present embodiment is by forming silicon-rich layer 100a in described shallow trench (comprising shallow trench 101 and shallow trench 102) lower surface and sidewall surfaces, thus make silicon-rich layer 100a be positioned at corner on described shallow trench, and then making the crystalline silicon of corner on described shallow trench be converted into amorphous silicon, the silicon namely in described silicon-rich layer 100a is amorphous silicon.The atomic density of described amorphous silicon is larger, therefore in follow-up formation gate dielectric layer process, oxygen can with the reaction of more silicon atom, thus improve speed that on described shallow trench, corner's silicon atom is oxidized (namely improving the growth rate of gate dielectric layer corner on described shallow trench).
In the present embodiment, the silicon ion concentration that described Si ion implantation adopts is greater than or equal to 5E15atom/cm
2thus ensure after described Si ion implantation, on described shallow trench, the silicon atom density of corner is comparatively large, is substantially equal to the growth rate of gate dielectric layer at described active area upper surface to make the growth rate of gate dielectric layer corner on described shallow trench be increased to.
In the present embodiment, the energy range that described Si ion implantation adopts is 1KeV ~ 30KeV.The energy demand that described silicon ion adopts is greater than 1KeV, can be injected into corner on described shallow trench to make silicon ion.But meanwhile, the energy demand that described Si ion implantation adopts is less than 30KeV, ensure that the silicon ion injected is positioned at the position that on described shallow trench, corner is more shallow, and then ensure that in subsequent gate dielectric layer forming process, the silicon ion injected can be oxidized.
Further, in the present embodiment, the energy range that described Si ion implantation adopts is 5KeV ~ 6KeV.In the energy range of 5KeV ~ 6KeV, described silicon ion injection degree of depth of corner on described shallow trench is more shallow, and comparatively concentrated, and Si ion implantation can be avoided the impact of other doped regions on silicon substrate 100.
In the present embodiment, described Si ion implantation angle is the angular range that Si ion implantation adopts is 0 ° ~ 30 °.The angle ranging from the angle of the straight line on the silicon ion direction of motion and vertical silicon substrate 100 surface.In the present embodiment, described angle can be understood as the angle of vertical direction in filled arrows IP1 and filled arrows IP2 and Fig. 4 in Fig. 4, that is filled arrows IP1 and filled arrows IP2 represents the direction of motion of silicon ion.
The Angle ambiguity of Si ion implantation is being less than or equal to 30 °, to improve injection efficiency by the present embodiment.Described Si ion implantation can select with once, twice or repeatedly injected.When injecting at twice, the angle of twice injection can be identical, but the direction of motion of silicon ion can lay respectively at the both sides of vertical direction, as shown in the filled arrows IP1 in Fig. 4 and filled arrows IP2.
Please refer to Fig. 5, after carrying out described Si ion implantation, adopt insulating material 140 to fill full described shallow trench, form fleet plough groove isolation structure (mark).Concrete, to fill shallow trench 101 shown in full Fig. 4 and shallow trench 102 is described.
Insulating material 140 can be silica.Can be filled by high density plasma CVD technique (HDP-CVD).After having filled insulating material 140, chemico-mechanical polishing (CMP) can be carried out to insulating material 140 upper surface, to remove unnecessary insulating material 140, thus make insulating material 140 upper surface and hard mask layer 120 upper surface flush, as shown in Figure 5.
The present embodiment, after the full shallow trench 101 of filling and shallow trench 102 form fleet plough groove isolation structure, can also carry out annealing in process to fleet plough groove isolation structure.This is because the film compactness that high density plasma deposition is formed is not fine, can be increased the compactness of film, make the isolation performance of fleet plough groove isolation structure better by high annealing.
Please refer to Fig. 6, remove the hard mask layer 120 and pad oxide 110 that are positioned on described active area, form opening 141.
In the present embodiment, phosphoric acid can be adopted to remove the hard mask layer 120 be positioned on described active area, and adopt hydrofluoric acid removal pad oxide layer 110, thus forming opening 141, opening 141 exposes upper surface and described shallow trench (now shallow trench is filled by insulating material 140) the upper corner edge of described active area.The temperature of the phosphoric acid solution used in described phosphoric acid etching technics can be 150 DEG C to 210 DEG C.In order to all be removed by hard mask layer 120, usually, described phosphoric acid etching technics will carry out the over etching of about 200%.
Please refer to Fig. 7, the silicon substrate of active area is formed gate dielectric layer 150.
In the present embodiment, adopt the silicon substrate 100 of active area described in oxidation process oxidizes, thus form gate dielectric layer 150.Namely the silicon substrate 100 of described active area comprises the silicon substrate 100 being positioned at upper surface place, active area, also comprises the silicon substrate 100 being positioned at corner on described shallow trench.
In the present embodiment, the silicon on active area silicon substrate 100 described in furnace oxidation process oxidizes (being namely positioned at the silicon of described convex top) can be adopted.The sull that furnace oxidation technique is formed is fine and close, and film thickness and sedimentation time are almost proportional, and therefore thin film composition and thickness are easy to control, and uniformity of film and reproducible, Step Coverage ability is good, easy to operate.
In the present embodiment, the gas that furnace oxidation technique adopts can comprise oxygen or ozone.When oxidizing gas dividing potential drop becomes large, oxidation reaction can acceleration.
In the present embodiment, the temperature range adopting furnace oxidation technique to adopt is 800 DEG C ~ 1050 DEG C.If temperature is lower than 800 DEG C, the compactness of the gate dielectric layer 150 then formed is not good, if temperature is higher than 1050 DEG C, adverse effect (board device temperature itself is also limited to uniform temperature) can be caused to board equipment, and also can produce thermal stress to silicon substrate 100 and bring other adverse effect simultaneously.
When described oxidation technology, because on described shallow trench, corner has silicon-rich layer 100a, therefore, on described shallow trench, the speed of corner's oxidized formation gate dielectric layer 150 is substantially equal with the speed of described active area upper surface oxidized formation gate dielectric layer 150.
Please refer to Fig. 8, gate dielectric layer 150 is formed grid 160.
In the present embodiment, the material of grid 160 can be polysilicon or metal.Described metal can be one deck or multilayer.And described metal is specifically as follows titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), ramet (TaC), nitrogen tantalum silicide (TaSiN), tungsten (W), tungsten nitride (WN), molybdenum nitride (MoN), nitrogen molybdenum oxide (MoON), ruthenium-oxide (RuO2), aluminium (Al) or copper (Cu) etc.Metal gates can be formed by physical vaporous deposition (PVD), chemical vapour deposition technique (CVD), atomic layer deposition method (ALD), plating (plating) or other applicable technique.
After formation grid 160, the present embodiment can also comprise, and with grid 160 and gate dielectric layer 150 for mask, in the silicon substrate 100 of grid 160 and gate dielectric layer 150 down either side, forms source region (not shown) and drain region (not shown).In the present embodiment, described source region and drain region are not be arranged in plane shown in Fig. 8, but lay respectively at plane shown in Fig. 8 inwards with outside two positions, that is, the line in Fig. 8 between shallow trench 101 and shallow trench 102 can perpendicular to the line between described source region and drain region.
In the formation method of the MOS transistor that the present embodiment provides, after the described shallow trench of formation, Si ion implantation is carried out to the upper corner of described shallow trench, thus the silicon atom density of corner on described shallow trench is raised, follow-up in gate dielectric layer 150 forming process, the growth rate of gate dielectric layer 150 corner on described shallow trench improves, and it is substantially equal to be increased to the growth rate surperficial on the active area with gate dielectric layer 150, therefore, the gate dielectric layer 150 of final formation can cover the upper corner of described shallow trench well, thus improve the reliability of semiconductor device.
In the formation method of the MOS transistor that the present embodiment provides, define silicon-rich layer 100a in the bottom of shallow trench and sidewall, and the thickness of silicon-rich layer 100a each several part is roughly equal simultaneously.Although in silicon-rich layer 100a; only be positioned at the part of corner on shallow trench and play the effect improving gate dielectric layer 150 growth rate; but; the technological operation simultaneously forming silicon-rich layer 100a in the bottom of shallow trench and sidewall is simple; do not need to do special protection process to shallow trench other parts; simplify technique, save process costs.And the silicon-rich layer 100a of other parts can not produce any adverse effect to the transistor of follow-up formation in the present embodiment.
But, in other embodiments of the invention, silicon-rich layer also can only be positioned at corner on shallow trench, that is, also can adopt the method for only corner's formation silicon-rich layer on shallow trench, reach the object improving gate dielectric layer corner's growth rate on shallow trench.Concrete, can after formation shallow trench, the mask layer forming patterning covers bottom and the partial sidewall of shallow trench, only exposes corner on shallow trench.Then the corresponding process of this specification previous embodiment and process conditions can be adopted to carry out Si ion implantation to corner on described shallow trench, to form the silicon-rich layer being only positioned at corner on shallow trench.The mask layer of described patterning can be removed afterwards.Finally can continue to adopt the process of the follow-up correspondence of this specification previous embodiment and process conditions to form complete transistor.
In addition, in other embodiments of the invention, silicon-rich layer also can be formed in there is shallow trench whole surface of silicon below.Concrete, after formation shallow trench, hard mask layer and pad oxide can be removed, then Si ion implantation is carried out to the whole surface of silicon with shallow trench, thus form the silicon-rich layer being positioned at whole surface of silicon, now part silicon-rich layer is positioned at corner on shallow trench equally, thus can realize the object improving subsequent gate dielectric layer corner's growth rate on shallow trench equally.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (12)
1. a formation method for MOS transistor, is characterized in that, comprising:
Silicon substrate is provided;
In described silicon substrate, form multiple discrete shallow trench, the region between adjacent described shallow trench is active area;
After the described shallow trench of formation, Si ion implantation is carried out to described silicon substrate, until form the silicon-rich layer being at least positioned at corner on described shallow trench;
After described Si ion implantation, adopt the full described shallow trench of filling insulating material, form fleet plough groove isolation structure;
The silicon substrate of described active area forms gate dielectric layer;
Described gate dielectric layer forms grid.
2. the formation method of MOS transistor as claimed in claim 1, it is characterized in that, described silicon-rich layer is only positioned at bottom and the sidewall of described shallow trench.
3. the formation method of MOS transistor as claimed in claim 1, it is characterized in that, described silicon-rich layer is only positioned at corner on described shallow trench.
4. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the silicon ion concentration that described Si ion implantation adopts is greater than or equal to 5E15atom/cm
2.
5. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the energy range that described Si ion implantation adopts is 1KeV ~ 30KeV.
6. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the energy range that described Si ion implantation adopts is 5KeV ~ 6KeV.
7. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the angular range that described Si ion implantation adopts is 0 ° ~ 30 °.
8. the formation method of MOS transistor as claimed in claim 1, it is characterized in that, described employing furnace oxidation technique forms described gate dielectric layer on the silicon substrate of described active area.
9. the formation method of MOS transistor as claimed in claim 8, is characterized in that, the gas that described furnace oxidation technique adopts comprise oxygen and ozone at least one of them.
10. the formation method of MOS transistor as claimed in claim 8, is characterized in that, the temperature range adopting furnace oxidation technique to adopt is 800 DEG C ~ 1050 DEG C.
The formation method of 11. MOS transistor as claimed in claim 1, is characterized in that, after the described shallow trench of formation, and before the described shallow trench of filling, is also included in the step that described shallow trench surface forms lining oxide layer.
The formation method of 12. MOS transistor as claimed in claim 11, is characterized in that, the gas forming the employing of described lining oxide layer comprises oxygen and nitrogen.
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| CN1213860A (en) * | 1997-10-01 | 1999-04-14 | 日本电气株式会社 | Field-effect transistor with trench isolation structure and method for manufacturing the same |
| US6143624A (en) * | 1998-10-14 | 2000-11-07 | Advanced Micro Devices, Inc. | Shallow trench isolation formation with spacer-assisted ion implantation |
| JP2001244324A (en) * | 2000-03-02 | 2001-09-07 | Sanyo Electric Co Ltd | Method for manufacturing semiconductor device |
| CN101159237A (en) * | 2006-10-08 | 2008-04-09 | 上海华虹Nec电子有限公司 | Pre amorphous ion injection process for improving high-pressure gate oxide homogeneity |
| CN102054702A (en) * | 2009-11-09 | 2011-05-11 | 上海华虹Nec电子有限公司 | Method for manufacturing groove power MOSFET device |
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|---|---|---|---|---|
| CN1213860A (en) * | 1997-10-01 | 1999-04-14 | 日本电气株式会社 | Field-effect transistor with trench isolation structure and method for manufacturing the same |
| US6143624A (en) * | 1998-10-14 | 2000-11-07 | Advanced Micro Devices, Inc. | Shallow trench isolation formation with spacer-assisted ion implantation |
| JP2001244324A (en) * | 2000-03-02 | 2001-09-07 | Sanyo Electric Co Ltd | Method for manufacturing semiconductor device |
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Application publication date: 20160217 |