CN102054702A - Method for manufacturing groove power MOSFET device - Google Patents
Method for manufacturing groove power MOSFET device Download PDFInfo
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- CN102054702A CN102054702A CN2009102017788A CN200910201778A CN102054702A CN 102054702 A CN102054702 A CN 102054702A CN 2009102017788 A CN2009102017788 A CN 2009102017788A CN 200910201778 A CN200910201778 A CN 200910201778A CN 102054702 A CN102054702 A CN 102054702A
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Abstract
The invention relates to a method for manufacturing groove power metal oxide semiconductor field effect transistor (MOSFET) device, which comprises the following steps of: forming a groove with a hard mask first; manufacturing dielectric layers on the side wall and bottom of the groove; removing the dielectric layer at the bottom of the groove by an anisotropic etching process, and reserving the dielectric layer on the side wall of the groove; performing silicon ion implantation at the bottom of the groove by utilizing ion implantation; removing the dielectric layer on the side wall of the groove and the silicon oxide hard mask; forming a gate oxide layer on the side wall of the groove and an oxide layer at the bottom of the groove by high-temperature oxidation; and forming a grid electrode, a source electrode and a drain electrode. By the method, the oxide layer, which is thicker than the gate oxide layer on the side wall of the groove, at the bottom of the groove can be formed, and parasitic capacitance between the grid electrode and the drain electrode in the device is reduced, so that the switch speed of the device is improved, and dynamic power consumption of the device is reduced. Simultaneously, the method has a simple process, is easy to integrate, and can be used for batch production.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to a kind of groove power MOSFET device making method.
Background technology
Groove structure is widely used in power electronic device, as Metal-oxide-semicondutor field effect transistor (MOSFET) and igbt (IGBT).Because it has transferred to the vertical direction of silicon chip with conductive channel from the surface of silicon chip, trench type device can be on unit are than planar device integrated more unit, thereby make conducting resistance obtain greatly lowering, reduced power consumption.Therefore in power device, trench MOSFET device and groove-shaped IGBT device are by more and more widely employing.As shown in Figure 1, cell schematics for existing groove power MOSFET device, N type outer layer growth is on heavy doping N type substrate, inject P type ion and annealing formation P trap in the epitaxial loayer, utilize etching technics in the P trap, to form groove, utilize high-temperature oxydation to form the trenched side-wall grid oxide layer, also form simultaneously the channel bottom oxide layer, fill polysilicon in the groove as grid, carry out the heavy doping of N type near the P trap groove top and form source electrode, heavy doping N type substrate receiving electrode is as drain electrode.When grid adds certain positive voltage, will between the source electrode of groove both sides and drain electrode, form conducting channel.In said structure, channel bottom oxidated layer thickness and trenched side-wall grid oxide layer thickness basically identical, be that the channel bottom oxide layer is a thin oxide layer, grid and drain electrode are isolated by described channel bottom oxide layer, because grid has very big stack area with drain electrode, adding the channel bottom oxide layer is a thin oxide layer, and this just makes that the parasitic capacitance of device grids and drain electrode is very big, influences the switching speed and the dynamic power consumption of device.
There is a kind of improvement process to be to use silicon nitride to make mask channel bottom is carried out selective oxidation, form a thicker channel bottom oxide layer, but (white emblem effect is interacted by silicon nitride and high ambient temperatures high humidity environment and causes the white emblem effect of silicon nitride when defective that silicon nitride stress causes in this technology and selective oxidation, both results of interaction are to generate ammonia and be diffused into silicon and the ribbon of the interface of silicon dioxide and formation white, the white emblem can cause that the puncture voltage of silicon dioxide oxide layer descends) can cause the puncture voltage of trenched side-wall grid oxide layer to descend, even electric leakage, make this technology that very big risk be arranged.
Summary of the invention
Technical problem to be solved by this invention provides a kind of groove power MOSFET device making method, can form the channel bottom oxide layer thicker than trenched side-wall grid oxide layer, reduce the grid of device and the parasitic capacitance between drain electrode, thereby improve the switching speed of device and reduce dynamic power consumption.
For solving the problems of the technologies described above, groove power MOSFET device making method provided by the invention at first is the epitaxial loayer of growth first conduction type on the heavy doping substrate of first conduction type, the hard mask of well region, growing silicon oxide of making second conduction type, photoetching formation groove figure, etching formation groove; Next is to make the channel bottom oxide layer thicker than trenched side-wall grid oxide layer, comprises the steps:
Step 1, make dielectric layer in trenched side-wall and bottom;
Step 2, utilize the anisotropic etching method to remove described channel bottom dielectric layer, keep described trenched side-wall dielectric layer;
Step 3, utilize ion to be infused in described channel bottom to carry out silicon ion and inject;
Step 4, the described trenched side-wall dielectric layer of removal and the hard mask of described silica;
Step 5, employing high-temperature oxydation form trenched side-wall grid oxide layer and channel bottom oxide layer;
Step 6, formation grid, source electrode and drain electrode.
Groove power MOSFET device of the present invention is owing to injected silicon ion at channel bottom, having increased channel bottom silicon density makes trench bottom surfaces decrystallized simultaneously, when high-temperature oxydation, improved the oxidation rate of channel bottom silicon, thereby can form the channel bottom oxide layer thicker than trenched side-wall grid oxide layer, reduce the grid of device and the parasitic capacitance between drain electrode, thereby improve the switching speed of device and reduce dynamic power consumption.Simultaneously technology of the present invention is fairly simple, is easy to integratedly, can be used for producing in batches.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the cell schematics of existing groove power MOSFET device;
Fig. 2 is the flow chart of groove power MOSFET device making method of the present invention;
Fig. 3 is the groove schematic diagram in each step of groove power MOSFET device making method of the present invention;
Fig. 4 is to use the cell schematics of the groove power MOSFET device of embodiment of the invention making.
Embodiment
As shown in Figure 2, be the flow chart of groove power MOSFET device making method of the present invention.
At first be to form the groove that has hard mask.As shown in Figure 3A, described groove is formed on the silicon substrate, silicon substrate is grown on the heavy doping substrate of first conduction type epitaxial loayer of first conduction type and the structure of having made the well region of second conduction type on epitaxial loayer, wherein said first conduction type can be N type or P type, and second conduction type then corresponds to P type or N type; Described in embodiments of the present invention first conduction type can be the N type, and second conduction type then corresponds to the P type.Described hard mask is the hard mask of silica; Utilize photoetching process to form groove figure is promptly made groove at needs the hard mask open of place formation silica after forming the hard mask of silica; Be that the etching mask etching forms groove with the hard mask of described silica again.
Then make the channel bottom oxide layer thicker, comprise the steps: than trenched side-wall grid oxide layer
Step 1, make dielectric layer in trenched side-wall and bottom.Described dielectric layer is the combination of silica, silicon nitride, silica and silicon nitride; The thickness of described dielectric layer is the 500-5000 dust; The silica medium layer adopts thermal oxidation or chemical gas-phase deposition method preparation, and the silicon nitride medium layer adopts the chemical vapor deposition preparation.Shown in Fig. 3 B, be to select the silica medium layer for use.
Step 2, shown in Fig. 3 C, utilize the anisotropic etching method to remove described channel bottom silica medium layer, keep described trenched side-wall silica medium layer.
Step 3, shown in Fig. 3 D, utilize ion to be infused in described channel bottom and carry out silicon ion and inject; Described silicon ion injects to be selected to inject once or twice to finish, and implant angle is 0～15 degree, and energy is 30～300 kiloelectron-volts, and implantation dosage is 1 * 10
11～1 * 10
16Individual/cm
2
Step 4, shown in Fig. 3 E, remove described trenched side-wall silica medium layer and the hard mask of described silica.
Step 5, adopt high-temperature oxydation to form trenched side-wall grid oxide layer and channel bottom oxide layer simultaneously as Fig. 3 F.Because after injecting through silicon ion, described channel bottom have high silicon density and described trench bottom surfaces decrystallized, so just improved the oxidation rate of described channel bottom silicon, be that 50 kiloelectron-volts, dosage are 4 * 10 for example at ion implantation energy
15Individual/cm
2The time, 1.3 times of the oxidation rate right and wrong injection region when 1000 ℃ of following high-temperature oxydations form 500 dust oxide layers.So the last described channel bottom oxide layer that forms will be thicker than described trenched side-wall grid oxide layer.
Step 6, formation grid, source electrode and drain electrode.Fill polysilicon as grid in groove, carry out the heavy doping of N type near the P trap groove top and form source electrode, heavy doping N type substrate receiving electrode is as drain electrode.Form groove power MOSFET device as shown in Figure 4 at last.
As shown in Figure 4, because described channel bottom oxide layer will be thicker than described trenched side-wall grid oxide layer, device with respect to channel bottom oxide layer in the prior art and trenched side-wall grid oxide layer consistency of thickness, the groove power MOSFET device of made of the present invention can reduce the parasitic capacitance between grid and drain electrode, thereby improves the switching speed of device and reduce dynamic power consumption.Because described trenched side-wall grid oxide layer is to make, and the making flow process of grid is closelyed follow after described trenched side-wall grid oxide layer completes, thereby obtains high-quality grid oxide layer, guarantee the reliability of device simultaneously when described channel bottom oxide layer forms or subsequently.To have technology simple in the present invention in addition, be easy to integrated, the advantage that can be used to produce in batches.
More than by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. groove power MOSFET device making method, the epitaxial loayer of growth first conduction type, the hard mask of well region, growing silicon oxide of making second conduction type, photoetching form groove figure on the heavy doping substrate of first conduction type, etching forms groove;
It is characterized in that, also comprise the steps:
Step 1, make dielectric layer in trenched side-wall and bottom;
Step 2, utilize the anisotropic etching method to remove described channel bottom dielectric layer, keep described trenched side-wall dielectric layer;
Step 3, utilize ion to be infused in described channel bottom to carry out silicon ion and inject;
Step 4, the described trenched side-wall dielectric layer of removal and the hard mask of described silica;
Step 5, employing high-temperature oxydation form trenched side-wall grid oxide layer and channel bottom oxide layer;
Step 6, formation grid, source electrode and drain electrode.
2. groove power MOSFET device making method as claimed in claim 1 is characterized in that: described dielectric layer is the combination of silica, silicon nitride, silica and silicon nitride; The thickness of described dielectric layer is the 500-5000 dust; The silica medium layer adopts thermal oxidation or chemical gas-phase deposition method preparation, and the silicon nitride medium layer adopts the chemical vapor deposition preparation.
3. groove power MOSFET device making method as claimed in claim 1 is characterized in that: silicon ion described in the step 3 injects to be selected to inject once or twice to finish, and implant angle is 0～15 degree, and energy is 30～300 kiloelectron-volts, and implantation dosage is 1 * 10
11～1 * 10
16Individual/cm
2
4. groove power MOSFET device making method as claimed in claim 1, it is characterized in that: the atmosphere of the described high-temperature oxydation of step 5 is the oxygen atmosphere or makes oxygen add the water vapour atmosphere that the hydrogen igniting forms, oxidizing temperature is 600～1300 ℃, and annealing time is 3～180 minutes.
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| CN2009102017788A CN102054702A (en) | 2009-11-09 | 2009-11-09 | Method for manufacturing groove power MOSFET device |
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| CN2009102017788A CN102054702A (en) | 2009-11-09 | 2009-11-09 | Method for manufacturing groove power MOSFET device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102737973A (en) * | 2011-10-13 | 2012-10-17 | 上海华虹Nec电子有限公司 | Device manufacturing method for enhancing IGBT (Insulated Gate Bipolar Translator) reliability |
| CN103855018A (en) * | 2012-12-04 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Method for adjusting BV and improving RDSON through ion implantation at bottoms of trenches |
| CN105336608A (en) * | 2014-05-28 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Formation method of MOS transistor |
| CN105655246A (en) * | 2016-01-04 | 2016-06-08 | 株洲南车时代电气股份有限公司 | Manufacturing method of groove-type IGBT grid electrode |
| CN108155231A (en) * | 2017-12-22 | 2018-06-12 | 广东美的制冷设备有限公司 | Igbt and its grid making method, IPM modules and air conditioner |
-
2009
- 2009-11-09 CN CN2009102017788A patent/CN102054702A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102737973A (en) * | 2011-10-13 | 2012-10-17 | 上海华虹Nec电子有限公司 | Device manufacturing method for enhancing IGBT (Insulated Gate Bipolar Translator) reliability |
| CN103855018A (en) * | 2012-12-04 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Method for adjusting BV and improving RDSON through ion implantation at bottoms of trenches |
| CN105336608A (en) * | 2014-05-28 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Formation method of MOS transistor |
| CN105655246A (en) * | 2016-01-04 | 2016-06-08 | 株洲南车时代电气股份有限公司 | Manufacturing method of groove-type IGBT grid electrode |
| CN108155231A (en) * | 2017-12-22 | 2018-06-12 | 广东美的制冷设备有限公司 | Igbt and its grid making method, IPM modules and air conditioner |
| CN108155231B (en) * | 2017-12-22 | 2021-07-27 | 广东美的制冷设备有限公司 | Insulated gate bipolar transistor, gate manufacturing method thereof, IPM module and air conditioner |
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Application publication date: 20110511 |