CN108155231B - Insulated gate bipolar transistor, gate manufacturing method thereof, IPM module and air conditioner - Google Patents
Insulated gate bipolar transistor, gate manufacturing method thereof, IPM module and air conditioner Download PDFInfo
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- CN108155231B CN108155231B CN201711429620.7A CN201711429620A CN108155231B CN 108155231 B CN108155231 B CN 108155231B CN 201711429620 A CN201711429620 A CN 201711429620A CN 108155231 B CN108155231 B CN 108155231B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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Abstract
The invention discloses an insulated gate bipolar transistor and a grid manufacturing method thereof, an IPM module and an air conditioner, wherein the grid manufacturing method of the insulated gate bipolar transistor comprises the following steps: preparing a semiconductor substrate; etching the first surface of the semiconductor substrate to form a groove; bombarding the bottom of the groove by using inert particles and/or an oxidizing agent to form a damage layer; oxidizing the side wall of the groove and the damage layer to form a gate oxide layer on the inner wall surface of the groove; filling polycrystalline silicon in the groove to form a polycrystalline layer; an insulating material is coated on the top of the polycrystalline layer from the first surface to form an insulating layer. The invention realizes the shortening of the on/off time of the insulated gate bipolar transistor, ensures that the insulated gate bipolar transistor has better conduction threshold voltage, namely lower conduction voltage drop, and is beneficial to optimizing the compromise relationship between the conduction voltage drop and the switching time.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to an insulated gate bipolar transistor, a grid electrode manufacturing method thereof, an IPM module and an air conditioner.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a Bipolar Transistor (BJT) and an Insulated Gate field effect Transistor (MOSFET), and has the advantages of high input impedance of the MOSFET device and low conduction voltage drop of a power Transistor (i.e., a giant Transistor, GTR for short), and because the IGBT has the advantages of small driving power and low saturation voltage drop, the IGBT is widely used in various fields as a novel power electronic device at present.
The manufacturing process steps of the IGBT substantially comprise: and sequentially manufacturing a grid electrode, a p-well and an emitting electrode on the silicon chip, and finally manufacturing a collector electrode on the back surface.
At present, the thickness of the gate trench oxide layer is uniform, i.e. the thickness of the trench bottom oxide layer is equal to the thickness of the trench sidewall oxide layer. Under the requirement that the oxide layer on the wall of the trench is thin, the thickness of the oxide layer at the bottom of the trench is also thin, so that the capacitance between the polysilicon of the IGBT and the collector is large, the turn-on time of the IGBT is long (namely, the turn-on loss is large), and the performance of the IGBT is reduced.
Disclosure of Invention
The invention mainly aims to provide an insulated gate bipolar transistor, a gate manufacturing method thereof, an IPM module and an air conditioner, and aims to shorten the on/off time of the insulated gate bipolar transistor, ensure that the insulated gate bipolar transistor has better conduction threshold voltage, namely conduction voltage drop, and have better compromise relationship between the conduction voltage drop and the on/off time.
In order to achieve the above object, the present invention provides a method for manufacturing a gate of an insulated gate bipolar transistor, wherein the method for manufacturing the gate of the insulated gate bipolar transistor comprises the following steps:
preparing a semiconductor substrate;
etching the first surface of the semiconductor substrate to form a groove;
bombarding the bottom of the groove by using inert particles and/or an oxidizing agent to form a damage layer;
oxidizing the side wall of the groove and the damage layer to form a gate oxide layer on the inner wall surface of the groove;
filling polycrystalline silicon in the groove to form a polycrystalline layer;
and covering an insulating material on the top of the polycrystalline layer from the first surface to form an insulating layer.
Preferably, the method further comprises the steps of, between the step of etching the first surface of the semiconductor substrate to form a trench and the step of bombarding the bottom of the trench with inert particles and/or oxidizing agent to form a damaged layer:
and oxidizing the bottom and the side wall of the groove to form a silicon dioxide layer, and removing the silicon dioxide layer.
Preferably, the thickness of the gate oxide layer covering the bottom of the trench is greater than the thickness of the gate oxide layer covering the inner peripheral wall of the trench.
Preferably, the damage layer thickness is greater than 0.1 um.
Preferably, the inert particle and/or oxidant bombardment energy is from 0.2keV to 500 keV.
Preferably, the inert particle and/or oxidant bombardment dose is 1 × e13-1*e16/cm2。
Preferably, the inert particles have a center density greater than an edge density thereof when they bombard the trench bottom.
The present invention also proposes an insulated gate bipolar transistor, comprising:
a semiconductor substrate;
an active region formed on the first surface of the semiconductor substrate;
the active region comprises a trench gate region; the groove grid electrode area comprises a groove formed in the first surface of the semiconductor substrate, a damage layer formed at the bottom of the groove, a grid electrode oxidation layer formed on the damage layer and the inner side wall surface of the groove, a polycrystalline layer filled in the groove and an insulating layer covering the top of the polycrystalline layer from the first surface.
Preferably, the thickness of the damage layer decreases from the central region to the inner side wall of the trench.
The invention also provides an IPM module comprising the insulated gate bipolar transistor; the insulated gate bipolar transistor includes: a semiconductor substrate; an active region formed on the first surface of the semiconductor substrate; the active region comprises a trench gate region; the groove grid electrode area comprises a groove formed in the first surface of the semiconductor substrate, a damage layer formed at the bottom of the groove, a grid electrode oxidation layer formed on the damage layer and the inner side wall surface of the groove, a polycrystalline layer filled in the groove and an insulating layer covering the top of the polycrystalline layer from the first surface.
Preferably, the thickness of the damage layer decreases from the central region to the inner side wall of the trench.
The invention also provides an air conditioner, which comprises the IPM module.
When the gate oxide layer is manufactured, inert particles such as argon particles, helium particles and neon particles or an oxidizing agent are used for bombarding the bottom of the groove, so that a damaged layer is formed at the bottom of the groove under the bombardment of argon particle beams, and the damaged layer has more defects and dangling bonds. Because the side wall of the groove is parallel to the direction of the argon particle beam, the side wall of the groove cannot be bombarded by the argon particle beam, the quality of the surface of the side wall of the groove is still high, and therefore during oxidation, the oxidation speed of the bottom is higher than that of the side wall of the groove, and therefore under the same oxidation condition, grid oxide layers with different thicknesses are formed at the bottom of the groove and the side wall of the groove. That is, the thickness of the gate oxide layer covering the bottom of the trench is greater than the thickness of the gate oxide layer covering the inner peripheral wall of the trench. By the arrangement, the thickness of the gate oxide layer at the bottom of the groove is designed to be thicker, so that parasitic capacitance is reduced, the purpose of shortening the on/off time of the insulated gate bipolar transistor is prolonged, and the conduction power consumption of the device is reduced. Meanwhile, the thickness of the grid oxide layer on the side wall of the groove is designed to be thinner, so that the threshold voltage of the well region inversion type, namely the turn-on voltage of the IGBT, is reduced, and the conduction loss of the device is reduced. The invention realizes the shortening of the on/off time of the insulated gate bipolar transistor, ensures that the insulated gate bipolar transistor has better conduction threshold voltage, namely lower conduction voltage drop, and is beneficial to optimizing the compromise relationship between the conduction voltage drop and the switching time.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a first embodiment of an IGBT according to the present invention;
FIG. 2 is a schematic structural diagram of a second embodiment of an IGBT according to the present invention;
FIG. 3 is a schematic structural diagram of a third embodiment of an IGBT according to the present invention;
FIG. 4 is a schematic structural diagram of a fourth embodiment of an IGBT according to the present invention;
FIG. 5 is a schematic structural diagram of a fifth embodiment of an IGBT according to the present invention;
fig. 6 is a flow chart of a gate manufacturing method of an insulated gate bipolar transistor according to the present invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 10 | |
22 | Damaged |
| 20 | |
23 | |
| 30 | Inert particles and/or oxidizing |
24 | |
| 21 | Groove | 25 | Insulating layer |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides a grid electrode manufacturing method of an insulated gate bipolar transistor.
A trench gate type insulated gate bipolar transistor generally includes an emitter, a trench gate, a well region, a drift region, and a collector. The manufacturing process steps of the trench gate type insulated gate bipolar transistor are approximately as follows: and sequentially manufacturing a grid electrode, a p-well and an emitting electrode on the silicon chip, and finally manufacturing a collector on the back surface.
In the process of manufacturing the gate, a high-quality gate oxide layer needs to be formed on the surface of the etched trench again, and the thickness of the gate oxide layer at the bottom of the trench is equal to that of the sidewall of the trench. Since the thickness of the sidewall oxide layer determines the threshold voltage of the inversion type well region, i.e., the turn-on voltage of the IGBT, the thickness of the trench oxide layer is generally made thinner to reduce the driving voltage of the IGBT.
However, the requirement of the thinner oxide layer on the trench wall makes the thickness of the oxide layer at the bottom of the trench thinner, so that the capacitance between the polysilicon of the IGBT and the collector will be larger, resulting in a longer turn-on time of the IGBT (i.e. a larger turn-on loss). Therefore, the ideal state is: the thickness of the gate oxide layer on the side wall of the groove is less than that of the bottom of the groove.
However, because the width of the trench of the IGBT is generally about 1um, and the depth is generally about 6um, for such a deep trench, direct filling of the oxide layer can lead to random deposition of the trench wall, adsorption and accumulation of the oxide layer, thereby bringing about great uncertainty to the threshold voltage design of the IGBT, and therefore, it is difficult to increase the thickness of the bottom oxide layer as much as possible without affecting the thickness and quality of the oxide layer of the trench wall of the IGBT, so as to shorten the turn-on time of the IGBT.
In order to solve the above problem, referring to fig. 1 to 6, in an embodiment of the present invention, a method for manufacturing a gate of an insulated gate bipolar transistor includes the following steps:
step S1, preparing the semiconductor substrate 10;
in this embodiment, the semiconductor substrate 10 may have a single crystal, polycrystalline, or amorphous structure such as silicon Si, silicon carbide SiC, germanium Ge, silicon germanium crystal SiGe, gallium nitride GaN, or gallium arsenide GaAs. The semiconductor substrate 10 may be rectangular, square, or the like. After the semiconductor substrate 10 is doped N-type or P-type, the present embodiment preferably dopes lightly doped N-ions to form a corresponding doped region on the semiconductor substrate 10.
Step S2, etching the first surface of the semiconductor substrate 10 to form a trench 21;
in this embodiment, the method for etching the trench 21 may adopt wet etching or dry etching, and in this embodiment, an etching manner of a reactive particle beam is preferably adopted, that is, the etching is implemented by combining ion bombardment and a chemical reaction, the ion bombardment destroys atomic bonds on the surface of the semiconductor substrate 10 to enhance the chemical reaction, so as to knock out atoms in the semiconductor substrate 10, and then the etching is performed to remove products or polymers deposited on the surface of the semiconductor substrate 10, so as to form the trench 21.
Step S3, bombarding the bottom of the groove 21 by using inert particles and/or oxidizing agents 30 to form a damaged layer 22;
referring to fig. 1 and 2, in the present embodiment, the inert particles may be one or more of argon particles, helium particles, and neon particles. For example, the bottom of the trench 21 is bombarded by an argon particle beam, so that under the bombardment of the argon particle beam, a damaged layer 22 is formed at the bottom of the trench 21, and the damaged layer 22 has more lattice defects and dangling bonds, and the more dangling bonds can accelerate the chemical reaction speed of oxygen and the semiconductor substrate 10, such as monocrystalline silicon. Because the side wall of the trench 21 is parallel to the direction of the argon particle beam, the side wall of the trench 21 is not bombarded by the argon particle beam, the quality of the surface of the side wall of the trench 21 is still high, that is, the chemical property of the monocrystalline silicon of the side wall of the trench 21 is not changed, so that the oxidation speed of the bottom is faster than that of the side wall of the trench 21 when oxidation is performed, and the gate oxide layer 23 at the bottom of the trench 21 is thicker than that of the gate oxide layer 23 at the side wall of the trench 21 under the same oxidation condition.
Step S4, oxidizing the sidewall of the trench 21 and the damaged layer 22 to form a gate oxide layer 23 on the inner wall surface of the trench 21;
referring to fig. 3, in this embodiment, the gate oxide layer 23 may be formed by a thermal oxidation method or a deposited oxide layer, and the present embodiment preferably uses a thermal oxidation method, specifically, uses high-purity oxygen, and performs an oxidation process on the entire semiconductor substrate 10 in a high-temperature environment, so as to form the gate oxide layer 23 on the sidewall of the trench 21 and the bottom of the trench 21, and since the damaged layer 22 exists at the bottom of the trench 21 and the sidewall of the trench 21 is still high-quality silicon, the oxidation speed at the bottom of the trench 21 is faster, so that after the oxidation is completed, the gate oxide layer 23 with different thicknesses can be formed on the bottom of the trench 21 and the sidewall of the trench 21. That is, the thickness of the gate oxide layer 23 covering the bottom of the trench 21 is greater than the thickness of the gate oxide layer 23 covering the inner peripheral wall of the trench 21.
The gate oxide layer 23 is a dielectric layer between the gate and the emitter and collector, and the capacitor formed by the trench gate region 20 and the collector region and the capacitor formed by the trench gate region 20 and the emitter region satisfy the following relations, as seen from electrostatics:
C＝ε·S/L (1)
wherein epsilon is the dielectric constant of the silicon dioxide dielectric, S is the area of the two electrode plates in the capacitor formed by the grid electrode and the collector electrode of the trench 21, and L is the distance between the grid electrode and the collector electrode, that is, the thickness of the silicon dioxide layer. When the insulated gate bipolar transistor is turned on, the collector region is connected to the outer wall of the gate of the trench 21 through the drift region, so that two polar plates of a capacitor formed by the gate of the trench 21 and the collector are formed with the inner wall of the gate of the trench 21, when the thickness degree of the gate oxide layer 23 at the bottom of the trench 21 is increased, the distance between the two polar plates is increased, and under the condition that the areas and the dielectric constants of the two polar plates are not changed, the capacitor is reduced along with the increase of the distance between the two polar plates.
The on/off time of the insulated gate bipolar transistor is in direct proportion to the parasitic capacitance, namely the larger the parasitic capacitance is, the longer the on/off time of the insulated gate bipolar transistor is, the parasitic capacitance is reduced by increasing the thickness of the gate oxide layer 23 at the bottom of the trench 21, namely the dielectric layer, so as to achieve the purpose of shortening the on/off time of the insulated gate bipolar transistor and reduce the conduction power consumption of the device.
It can be understood that, since the thickness of the gate oxide layer 23 on the bottom of the IGBT is only increased in this embodiment, and the thickness of the gate oxide layer 23 on the inner side wall of the trench 21 is not changed, the thickness of the gate oxide layer 23 on the side wall of the trench 21 can be designed to be thinner, so as to reduce the threshold voltage of the well inversion, that is, the turn-on voltage of the IGBT, and reduce the conduction loss of the device.
The thickness of the sidewall oxide layer determines the threshold voltage of the inversion type well region, i.e. the turn-on voltage of the IGBT, so the thickness of the oxide layer of the trench 21 is generally made thinner to reduce the driving voltage of the IGBT.
Step S5, filling polysilicon in the trench 21 to form a polycrystalline layer 24;
referring to fig. 4, in the present embodiment, polysilicon is deposited on the gate oxide layer 23 by using a chemical vapor deposition (cvd) technique to fill the trench 21 with polysilicon, and then the polysilicon outside the trench 21 is etched, or amorphous silicon is prepared first and then crystallized by solid phase crystallization, laser crystallization, and rapid thermal processing (rtp) technique to fill the trench 21 with the amorphous silicon.
Step S6, cover the polycrystalline layer 24 with an insulating material from the first surface to form an insulating layer 25.
Referring to fig. 5, in this embodiment, a thermal oxidation process may be used to process the device, so that a polysilicon oxide layer is grown on the surface of the polysilicon, where the polysilicon oxide layer is an insulating layer 25, or an insulating layer 25 is deposited on the entire surface by sputtering, and then the insulating layer 25 outside the trench 21 is etched away, where the insulating layer 25 may be made of a material with good insulating properties, such as silicon dioxide and silicon nitride.
In this embodiment, when the gate oxide layer 23 is formed, the bottom of the trench 21 is bombarded with inert particles such as argon particles, helium particles, neon particles, or the like, or an oxidizing agent, so that the damaged layer 22 is formed at the bottom of the trench 21 by the bombardment of the argon particle beam, and the damaged layer 22 has many defects and dangling bonds. Since the sidewall of the trench 21 is parallel to the direction of the argon particle beam, the sidewall of the trench 21 is not bombarded by the argon particle beam, and the quality of the surface of the sidewall of the trench 21 is still high, so that the oxidation speed of the bottom is faster than that of the sidewall of the trench 21 during oxidation, and thus, under the same oxidation condition, gate oxide layers 23 with different thicknesses are formed on the bottom of the trench 21 and the sidewall of the trench 21. That is, the thickness of the gate oxide layer 23 covering the bottom of the trench 21 is greater than the thickness of the gate oxide layer 23 covering the inner peripheral wall of the trench 21. With such an arrangement, the thickness of the gate oxide layer 23 at the bottom of the trench 21 is advantageously designed to be thicker, so as to reduce parasitic capacitance, thereby achieving the purpose of shortening the on/off time of the insulated gate bipolar transistor and reducing the on power consumption of the device. Meanwhile, the thickness of the gate oxide layer 23 on the side wall of the trench 21 is designed to be thinner, so that the threshold voltage of the well region inversion type, namely the turn-on voltage of the IGBT is reduced, and the conduction loss of the device is reduced.
The invention realizes that the on/off time of the insulated gate bipolar transistor is shortened, and simultaneously ensures that the insulated gate bipolar transistor has better conduction threshold voltage, namely lower conduction voltage drop, and is beneficial to optimizing the compromise relationship between the conduction voltage drop and the switching time.
Referring to fig. 1 to 5, it can be understood that in the above embodiment, between the step of etching the first surface of the semiconductor substrate 10 to form the trench 21 and the step of bombarding the bottom of the trench 21 with the inert particles and/or the oxidizing agent 30 to form the damaged layer 22, the steps of:
the bottom and sidewalls of the trench 21 are oxidized to form a silicon dioxide layer, which is removed.
In this embodiment, silicon dioxide is formed on the surface of the trench 21 on the semiconductor substrate 10, for example, on the single crystal silicon damaged layer 22, due to reactive ion beam etching; after the silicon dioxide is removed, the surface of the trench 21 is not damaged, that is, the gate oxide layer 23 with high quality can be formed on the wall of the trench 21, so that the consistency of the threshold voltage and the conductive channel with high quality are ensured.
Referring to fig. 1-5, in a preferred embodiment, the damage layer 22 is greater than 0.1um thick.
In this embodiment, the bottom of the trench 21 is bombarded by the inert particles and/or the oxidant 30, the thickness of the formed damage layer 22 is greater than 0.1um, and the inner side wall of the trench 21 is parallel to the direction bombarded by the inert particles and/or the oxidant 30, so that the damage layer is not affected, and by such arrangement, when the gate oxide layer 23 is formed, the inner side wall of the trench 21 and the gate oxide layer 23 at the bottom of the trench 21 both have a better thickness, thereby ensuring that the electric field is not weakened, and causing the threshold voltage to rise. And meanwhile, the capacitance values of the gate emitter parasitic capacitance Cgc and the gate and collector parasitic capacitance Cge are reduced, so that the charging time and the discharging time of the gate emitter parasitic capacitance Cge and the gate and collector parasitic capacitance Cgc are shortened, and the purpose of shortening the turn-on and turn-off time of the insulated gate bipolar transistor is realized.
Referring to FIGS. 1 through 5, in a preferred embodiment, the inert particles, such as argon particles, neon particles, or the like, or oxidizing agents, such as oxygen atoms, have a bombardment energy of 0.2keV to 500 keV. The bombardment dose of the inert particles is 1 × e13-1*e16/cm2。
In this embodiment, the particle beam is emitted to the surface of the semiconductor substrate 10 after obtaining energy, so that lattice defects and dangling bonds are formed on the surface of the semiconductor substrate 10 to accelerate the oxidation speed between oxygen and the semiconductor substrate 10 when the gate oxide layer 23 is formed, and thus both the bombardment energy and the dose must reach a certain value. In the scheme, the bombardment energy of the inert particles is 0.2keV-500keV, and preferably, the ion implantation energy is 70 Kev. When the ion implantation energy is less than 0.2keV, the chemical properties of the semiconductor substrate 10 cannot be damaged well, and lattice defects and dangling bonds are entangled. When the implantation energy is greater than 500keV, sputtering may occur on the semiconductor substrate 10 to damage the semiconductor substrate 10.
Referring to fig. 1-5, in a preferred embodiment, the inert particles have a center density that is greater than an edge density of the inert particles as they bombard the bottom of the trench 21.
In this embodiment, when bombarding the bottom of the trench 21, the density of the ion beam may be adjusted, for example, the center density of the inert particles is greater than the edge density thereof, and after bombarding by the non-uniform particle beam, the damaged layer 22 with different degrees of damaged layer 22 is formed at the bottom of the trench 21, the damage of the center region is severe, and the damage of the edge region is light. Because the central area of the bottom of the trench 21 is damaged seriously, the number of dangling bonds is large, the oxidation speed is high, and a formed gate oxide layer 23 is also thick when gate oxidation is carried out; the damage of the edge region at the bottom of the groove 21 is light, so that the dangling bond is less, the oxidation speed is low, and the formed gate oxide layer 23 is also thin, so that the arc-shaped gate oxide layer 23 is formed at the bottom of the groove 21, compared with a flat-bottom oxide layer, the arc-shaped gate oxide layer 23 can relieve the concentrated distribution of an electric field at the bottom of the groove 21, especially the right angle at the bottom of the groove 21, the situation that the IGBT is broken down too fast at the bottom of the groove 21 is avoided, and the voltage endurance capability of the IGBT is favorably improved.
The invention also provides an insulated gate bipolar transistor.
Referring to fig. 5, in an embodiment of the present invention, an insulated gate bipolar transistor includes:
a semiconductor substrate 10;
an active region (not shown) formed on the first surface of the semiconductor substrate 10;
the active region comprises a trench gate region 20; the trench gate region 20 includes a trench 21 opened from the first surface of the semiconductor substrate 10, a damaged layer 22 formed at the bottom of the trench 21, a gate oxide layer 23 formed on the damaged layer 22 and the inner sidewall surface of the trench 21, a polycrystalline layer 24 filled in the trench 21, and an insulating layer 25 covering the top of the polycrystalline layer 24 from the first surface.
It should be noted that, when the gate oxide layer 23 is formed, the damaged layer 22 formed by bombarding the bottom of the trench 21 has more lattice defects and dangling bonds, and the more dangling bonds can accelerate the chemical reaction rate of oxygen with the semiconductor substrate 10. The thickness of the damaged layer 22 is gradually reduced with the degree of oxidation of the gate oxide layer 23 formed on the damaged layer 22, and when the oxidation is sufficient, the damaged layer 22 may be completely replaced by the gate oxide layer 23 and disappear.
According to the invention, when the gate oxide layer 23 is manufactured, inert particles or an oxidizing agent is used for bombarding the bottom of the groove 21, so that a damaged layer 22 is formed at the bottom of the groove 21, and more defects and dangling bonds exist in the damaged layer 22, so that the oxidation speed of the bottom of the groove 21 is higher than that of the side wall of the groove 21, and thus, under the same oxidation condition, the gate oxide layers 23 with different thicknesses are formed at the bottom of the groove 21 and the side wall of the groove 21. That is, the thickness of the gate oxide layer 23 covering the bottom of the trench 21 is greater than the thickness of the gate oxide layer 23 covering the inner peripheral wall of the trench 21. With such an arrangement, the thickness of the gate oxide layer 23 at the bottom of the trench 21 is advantageously designed to be thicker, so as to reduce parasitic capacitance, thereby achieving the purpose of shortening the on/off time of the insulated gate bipolar transistor and reducing the on power consumption of the device. Meanwhile, the thickness of the gate oxide layer 23 on the side wall of the trench 21 is designed to be thinner, so that the threshold voltage of the well region inversion type, namely the turn-on voltage of the IGBT is reduced, and the conduction loss of the device is reduced.
The invention realizes that the on/off time of the insulated gate bipolar transistor is shortened, and simultaneously ensures that the insulated gate bipolar transistor has better conduction threshold voltage, namely conduction voltage drop, and has better compromise relation between the conduction voltage drop and the on/off time.
It will be appreciated that the insulated gate bipolar transistor of the present invention also includes an emitter, a well region, a drift region and a collector, the specific structure of which may be arranged with reference to a conventional insulated gate bipolar transistor. The manufacturing process includes ion implantation, surface oxidation, photolithography and other conventional techniques, and the details are not repeated here.
In this embodiment, the thickness of the damaged layer 22 decreases from the central region to the inner sidewall of the trench 21.
In the embodiment, when the bottom of the trench 21 is bombarded, the central density of the particles is greater than the edge density of the particles, so that the central region of the bottom of the trench 21 is seriously damaged, and therefore, the number of dangling bonds is large, the oxidation speed is high, and the formed gate oxide layer 23 is also thick when gate oxidation is performed; the damage of the edge area of the bottom of the groove 21 is light, so that the dangling bond is less, the oxidation speed is low, and the formed gate oxide layer 23 is also thin, so that the arc-shaped gate oxide layer 23 is formed at the bottom of the groove 21 to relieve the concentrated distribution of an electric field at the bottom of the groove 21, particularly the right angle at the bottom of the groove 21, further avoid the over-fast breakdown of the IGBT at the bottom of the groove 21, and be beneficial to improving the voltage endurance capability of the IGBT.
The present invention further provides an IPM module, where the IPM module includes the insulated gate bipolar transistor, and the specific structure of the insulated gate bipolar transistor refers to the above embodiments, and since the IPM module adopts all technical solutions of all the above embodiments, at least all beneficial effects brought by the technical solutions of the above embodiments are achieved, and details are not repeated herein.
It will be understood by those skilled in the art that the IPM module may include 4 igbts or 6 igbts, and the connection relationship between the igbts is not described herein.
The invention also provides an air conditioner which comprises the IPM module. The IPM module may be used in a main circuit or a control circuit of an air conditioner, and is not particularly limited herein.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A method for manufacturing a gate of an insulated gate bipolar transistor is characterized by comprising the following steps:
preparing a semiconductor substrate;
etching the first surface of the semiconductor substrate to form a groove;
bombarding the bottom of the groove by using inert particles and/or an oxidizing agent to form a damage layer; wherein the inert particles are parallel to the direction of the side wall of the groove;
oxidizing the side wall of the groove and the damage layer to form a gate oxide layer on the inner wall surface of the groove; the grid oxide layer is a dielectric layer of a grid, an emitter of the insulated gate bipolar transistor and a collector;
filling polycrystalline silicon in the groove to form a polycrystalline layer;
covering an insulating material on the top of the polycrystalline layer from the first surface to form an insulating layer;
when the inert particles and/or the oxidizing agent bombard the bottom of the groove, the density of the inert particles and/or the oxidizing agent at the center area of the bottom of the groove is larger than that at the edge area of the bottom of the groove.
2. The method of fabricating a gate of an insulated gate bipolar transistor according to claim 1, wherein between the step of etching the first surface of the semiconductor substrate to form a trench and the step of bombarding the bottom of the trench with inert particles and/or an oxidizing agent to form a damage layer, further comprising the steps of:
and oxidizing the bottom and the side wall of the groove to form a silicon dioxide layer, and removing the silicon dioxide layer.
3. The method of claim 1, wherein the thickness of the gate oxide layer covering the bottom of the trench is greater than the thickness of the gate oxide layer covering the inner peripheral wall of the trench.
4. The method of manufacturing a gate of an insulated gate bipolar transistor according to claim 1, wherein the thickness of the damaged layer is greater than 0.1 um.
5. The method of claim 1, wherein the inert particle and/or oxidizing agent bombardment energy is 0.2keV to 500 keV.
6. Such as rightThe method of claim 1, wherein the inert particle and/or oxidant bombardment dose is 1 xe13-1*e16/cm2。
7. An insulated gate bipolar transistor, comprising:
a semiconductor substrate;
an active region formed on the first surface of the semiconductor substrate;
the active region comprises a trench gate region; the groove grid electrode area comprises a groove formed in the first surface of the semiconductor substrate, a damage layer formed at the bottom of the groove, a grid electrode oxidation layer formed on the damage layer and the inner side wall surface of the groove, a polycrystalline layer filled in the groove and an insulating layer covering the top of the polycrystalline layer from the first surface;
the thickness of the damage layer is gradually reduced from the central area of the bottom of the groove to the edge of the bottom of the groove.
8. An IPM module comprising the insulated gate bipolar transistor according to claim 7.
9. An air conditioner, characterized in that it comprises an IPM module according to claim 8.
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| CN109473474A (en) * | 2018-11-09 | 2019-03-15 | 上海擎茂微电子科技有限公司 | Insulated trench gate electrode bipolar type transistor device and its generation method |
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| US6228720B1 (en) * | 1999-02-23 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Method for making insulated-gate semiconductor element |
| US6489652B1 (en) * | 1995-11-11 | 2002-12-03 | Fairchild Semiconductor Corporation | Trench DMOS device having a high breakdown resistance |
| CN102054702A (en) * | 2009-11-09 | 2011-05-11 | 上海华虹Nec电子有限公司 | Method for manufacturing groove power MOSFET device |
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| US6489652B1 (en) * | 1995-11-11 | 2002-12-03 | Fairchild Semiconductor Corporation | Trench DMOS device having a high breakdown resistance |
| US6228720B1 (en) * | 1999-02-23 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Method for making insulated-gate semiconductor element |
| CN102054702A (en) * | 2009-11-09 | 2011-05-11 | 上海华虹Nec电子有限公司 | Method for manufacturing groove power MOSFET device |
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