CN108155231A - Igbt and its grid making method, IPM modules and air conditioner - Google Patents
Igbt and its grid making method, IPM modules and air conditioner Download PDFInfo
- Publication number
- CN108155231A CN108155231A CN201711429620.7A CN201711429620A CN108155231A CN 108155231 A CN108155231 A CN 108155231A CN 201711429620 A CN201711429620 A CN 201711429620A CN 108155231 A CN108155231 A CN 108155231A
- Authority
- CN
- China
- Prior art keywords
- groove
- igbt
- layer
- grid
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000002245 particle Substances 0.000 claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 230000001590 oxidative effect Effects 0.000 claims abstract description 19
- 239000007800 oxidant agent Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000011810 insulating material Substances 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 230000006378 damage Effects 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000007423 decrease Effects 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 2
- 238000004904 shortening Methods 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 description 29
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 28
- 230000003647 oxidation Effects 0.000 description 28
- 229910052786 argon Inorganic materials 0.000 description 14
- 230000003071 parasitic effect Effects 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- 230000007547 defect Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910052754 neon Inorganic materials 0.000 description 4
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000001307 helium Substances 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
Abstract
The present invention discloses a kind of igbt and its grid making method, IPM modules and air conditioner, and the grid making method of igbt includes the following steps：Prepare Semiconductor substrate；It performs etching to form groove in the first surface of Semiconductor substrate；Using the bottom of inert particle and/or oxidant bombardment groove, to form damaging layer；The side wall and damaging layer of groove are aoxidized, grid oxic horizon is formed with wall surface in the trench；Polysilicon is filled in the trench to form polycrystal layer；Insulating materials is covered in the top of polycrystal layer to form insulating layer from first surface.The present invention realizes the ON/OFF time for shortening igbt, while ensures that igbt has preferably on state threshold voltage namely relatively low conduction voltage drop, is conducive to optimize conduction voltage drop and the tradeoff between switch time.
Description
Technical field
The present invention relates to electronic circuit technology field, more particularly to a kind of igbt and its fabrication side
Method, IPM modules and air conditioner.
Background technology
Igbt (Insulated Gate Bipolar Transistor, abbreviation IGBT) is by bipolar
The compound full-control type voltage driven type power semiconductor device of triode (BJT) and insulating gate type field effect tube (MOSFET) composition
Part has the high input impedance of MOSFET element and the low conduction voltage drop two of power transistor (i.e. huge transistor, abbreviation GTR) concurrently
The advantages of aspect, since IGBT has the advantages that driving power is small and saturation pressure reduces, IGBT is as a kind of novel electricity at present
Power electronic device is widely applied to every field.
The manufacturing process steps of IGBT generally comprise for：It makes grid, p traps, emitter successively on silicon chip, finally exists again
The back side makes collector.
At present, the thickness of gate trench oxide layer is uniform, i.e., the thickness of channel bottom oxide layer is equal to the oxygen of trenched side-wall
Change the thickness of layer.Under the relatively thin requirement of the oxide layer of trench wall, the thickness that can cause channel bottom oxide layer is also relatively thin so that
Capacitance between the polysilicon and collector of IGBT is larger, so as to cause IGBT service time it is longer (namely turn-on consumption compared with
Greatly), the performance of IGBT is reduced.
Invention content
The main object of the present invention be propose a kind of igbt and its grid making method, IPM modules and
Air conditioner, it is intended to shorten the ON/OFF time of igbt, while ensure that igbt has and preferably lead
Logical threshold voltage namely conduction voltage drop, have preferable conduction voltage drop and the tradeoff between switch time.
To achieve the above object, the present invention proposes a kind of grid making method of igbt, the insulation
The grid making method of grid bipolar transistor includes the following steps：
Prepare Semiconductor substrate；
It performs etching to form groove in the first surface of the Semiconductor substrate；
The bottom of the groove is bombarded using inert particle and/or oxidant, to form damaging layer；
Side wall and the damaging layer to the groove aoxidize, to form gate oxidation in the trench wall face
Layer；
Polysilicon is filled in the trench to form polycrystal layer；
Insulating materials is covered in the top of the polycrystal layer to form insulating layer from the first surface.
Preferably, the first surface of the Semiconductor substrate is performed etching to form groove the step of and inertia grain is utilized
Son and/or oxidant bombard the bottom of the groove, the step of to form damaging layer between further include step：
Bottom and side wall to the groove are aoxidized to form silicon dioxide layer, and the silicon dioxide layer are gone
It removes.
Preferably, be covered in the grid oxic horizon of the channel bottom thickness be more than be covered in groove internal perisporium
The thickness of the grid oxic horizon.
Preferably, the damage layer thickness is more than 0.1um.
Preferably, the inert particle and/or oxidant bombarding energy are 0.2keV-500keV.
Preferably, the inert particle and/or oxidant bombardment dosage are 1*e13-1*e16/cm2。
Preferably, when the inert particle bombards channel bottom, the center density of the inert particle is more than its edge
Density.
The present invention also proposes a kind of igbt, and the igbt includes：
Semiconductor substrate；
It is formed in the active area of the Semiconductor substrate first surface；
The active area includes trench gate polar region；The trench gate polar region includes the first surface from the Semiconductor substrate
The groove that opens up, the damaging layer for being formed in the channel bottom are formed in the damaging layer and the interior sidewall surface of the groove
Grid oxic horizon, the polycrystal layer being filled in the groove and be covered in from the first surface polycrystal layer top it is exhausted
Edge layer.
Preferably, the thickness of the damaging layer successively decreases from its central area to the groove madial wall.
The present invention also proposes a kind of IPM modules, including igbt as described above；The insulated gate bipolar
Transistor includes：Semiconductor substrate；It is formed in the active area of the Semiconductor substrate first surface；The active area includes groove
Gate regions；The trench gate polar region includes the groove opened up from the first surface of the Semiconductor substrate, is formed in the groove
The damaging layer of bottom is formed in the grid oxic horizon of the damaging layer and the interior sidewall surface of the groove, is filled in the groove
In polycrystal layer and be covered in from the first surface polycrystal layer top insulating layer.
Preferably, the thickness of the damaging layer successively decreases from its central area to the groove madial wall.
The present invention also proposes a kind of air conditioner, and the air conditioner includes IPM modules as described above.
The present invention passes through inert particles or the oxidants such as argon particle, helium particle, neon particle when making grid oxic horizon
Channel bottom is bombarded, so as under the bombardment of the argon particle beams, forms damaging layer in trench bottom, there are more in the damaging layer
Defect and dangling bonds.Since trenched side-wall is parallel with argon particle beams direction, trenched side-wall will not be by argon particle beam bombardment, ditch
The quality of flute wall surfaces is still very high, so as to which in oxidation, the oxidation rate of bottom is faster than the oxidation rate of trenched side-wall, this
Under identical oxidizing condition, the grid oxic horizon of different-thickness is formed in channel bottom and trenched side-wall for sample.That is, it is covered in
The thickness of the grid oxic horizon of the channel bottom is more than the thickness for the grid oxic horizon for being covered in groove internal perisporium.
So set, be conducive to the thickness of grid oxide layer of channel bottom being designed thicker, so as to reduce parasitic capacitance, to realize contracting
ON/OFF time of short igbt longer purpose reduces the conducting power consumption of device.Simultaneously by trenched side-wall grid
The thickness of oxide layer is designed relatively thin, so as to reduce the threshold voltage of well region transoid, that is, the turning-on voltage of IGBT, to reduce
The conduction loss of device.The present invention realizes the ON/OFF time for shortening igbt, while ensures insulated gate bipolar
Transistor has preferably on state threshold voltage namely relatively low conduction voltage drop, be conducive to optimize conduction voltage drop and switch time it
Between tradeoff.
Description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention, for those of ordinary skill in the art, without creative efforts, can be with
Structure according to these attached drawings obtains other attached drawings.
Fig. 1 is the structure diagram of igbt first embodiment of the present invention；
Fig. 2 is the structure diagram of igbt second embodiment of the present invention；
Fig. 3 is the structure diagram of igbt 3rd embodiment of the present invention；
Fig. 4 is the structure diagram of igbt fourth embodiment of the present invention；
Fig. 5 is the structure diagram of the 5th embodiment of igbt of the present invention；
Fig. 6 is the flow chart of the grid making method of igbt of the present invention.
Drawing reference numeral explanation：
| Label | Title | Label | Title |
| 10 | Semiconductor substrate | 22 | Damaging layer |
| 20 | Trench gate polar region | 23 | Grid oxic horizon |
| 30 | Inert particle and/or oxidant | 24 | Polycrystal layer |
| 21 | Groove | 25 | Insulating layer |
The embodiments will be further described with reference to the accompanying drawings for the realization, the function and the advantages of the object of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only the part of the embodiment of the present invention, instead of all the embodiments.Base
Embodiment in the present invention, those of ordinary skill in the art obtained without creative efforts it is all its
His embodiment, shall fall within the protection scope of the present invention.
If it is to be appreciated that related in the embodiment of the present invention directionality instruction (such as up, down, left, right, before and after ...),
Then directionality instruction be only used for explaining relative position relation under a certain particular pose (as shown in drawings) between each component,
Motion conditions etc., if the particular pose changes, directionality instruction also correspondingly changes correspondingly.
If in addition, relating to the description of " first ", " second " etc. in the embodiment of the present invention, it is somebody's turn to do " first ", " second " etc.
Description be only used for description purpose, and it is not intended that instruction or implying its relative importance or implicit indicating indicated skill
The quantity of art feature." first " is defined as a result, and the feature of " second " can be expressed or implicitly includes at least one spy
Sign.In addition, the technical solution between each embodiment can be combined with each other, but must be with those of ordinary skill in the art's energy
Based on enough realizations, the knot of this technical solution is will be understood that when the combination appearance of technical solution is conflicting or can not realize
Conjunction is not present, also not the present invention claims protection domain within.
The present invention proposes a kind of grid making method of igbt.
Trench gate igbt generally comprises emitter, trench-gate, well region, drift region and collector.
Trench gate igbt manufacturing process steps are substantially：On silicon chip, grid, p traps, emitter are made successively,
Finally collector is overleaf made again.
In the processing step for making grid, need to re-form the grid oxygen of high quality in the flute surfaces that etching is formed
Change layer, and grid oxic horizon is equal with the thickness of trenched side-wall in the thickness of channel bottom oxide layer.Due to sidewall oxide
Thickness decides the threshold voltage of well region transoid, that is, the turning-on voltage of IGBT, therefore the thickness of trench oxide layer is generally all
It is made relatively thin, to reduce the driving voltage of IGBT.
However, under the relatively thin requirement of the oxide layer of trench wall, the thickness that can cause channel bottom oxide layer is also relatively thin, this
Capacitance between the polysilicon and collector of sample IGBT will be larger, the service time for leading to IGBT longer (namely turn-on consumption
It is larger).Therefore, perfect condition is：The thickness of grid oxide layer thickness of trenched side-wall is less than the thickness of channel bottom.
But since the groove width of IGBT is generally in 1um or so, depth is generally in 6um or so, for so thin deep
Groove, direct filling oxide layer can cause trench wall that can also accumulate absorption, tired oxide layer at random, and then be set to the threshold voltage of IGBT
Meter brings very big uncertainty, therefore relatively difficult to achieve in the case where not influencing IGBT trench walls oxidated layer thickness, quality, to the greatest extent
Possibly increase the thickness of bottom oxidization layer, to shorten the service time of IGBT.
To solve the above-mentioned problems, referring to figs. 1 to Fig. 6, in an embodiment of the present invention, the igbt
Grid making method includes the following steps：
Step S1, prepare Semiconductor substrate 10；
In the present embodiment, Semiconductor substrate 10 can be silicon Si, silicon carbide SiC, germanium Ge, Si Ge crystal SiGe, gallium nitride
The monocrystalline such as GaN or GaAs GaAs, polycrystalline or non-crystal structure.Semiconductor substrate 10 can be rectangle, rectangular etc..Also,
After n-type doping or p-type doping are carried out in Semiconductor substrate 10, the present embodiment, which is preferably incorporated into, is lightly doped N- ions, in semiconductor
Corresponding doped region is formed on substrate 10.
Step S2, it performs etching to form groove 21 in the first surface of the Semiconductor substrate 10；
In the present embodiment, wet etching or dry etching may be used in the method that groove 21 etches, and the present embodiment is preferred
Using the etching mode of reaction particle beam, i.e., it is combined to realize by ion bombardment and chemical reaction, ion bombardment will partly be led
The atom key destruction on 10 surface of body substrate enhances chemical reaction, so as to hit the atom in Semiconductor substrate 10, then carry out
Etching is deposited on the product or polymer on 10 surface of Semiconductor substrate to remove, so as to form groove 21.
Step S3, the bottom of the groove 21 is bombarded using inert particle and/or oxidant 30, to form damaging layer 22；
Referring to Figures 1 and 2, in the present embodiment, inert particle can be argon particle, helium particle, one kind in neon particle or
It is a variety of.Such as by 21 bottom of argon particle beam bombardment groove, so as under the bombardment of the argon particle beams, be formed and damaged at 21 bottom of groove
Layer 22, there are more lattice defect and dangling bonds in the damaging layer 22, and more dangling bonds can accelerate oxygen with partly leading
Body substrate 10, such as the chemical reaction velocity of monocrystalline silicon.Since 21 side wall of groove is parallel with argon particle beams direction, groove 21
Side wall will not be by argon particle beam bombardment, and the quality of 21 wall surface of groove is still very high namely the change of the monocrystalline silicon of 21 side wall of groove
Property is learned not change, in this way when being aoxidized, the oxidation rate of bottom is faster than the oxidation rate of 21 side wall of groove,
Under identical oxidizing condition, the grid oxic horizon 23 of 21 bottom of groove is thick bigger than the grid oxic horizon 23 of 21 side wall of groove.
Step S4, the side wall and the damaging layer 22 of the groove 21 are aoxidized, in 21 internal face of groove
Form grid oxic horizon 23；
With reference to 3, in the present embodiment, thermal oxidation method may be used in grid oxic horizon 23 or deposited oxide layer sends progress,
This implementation preferably using thermal oxidation method, specifically, using the higher oxygen of purity, and under high temperature environment serves as a contrast entire semiconductor
Bottom 10 carries out oxidation processes, so as to form grid oxic horizon 23 in the side wall of groove 21 and 21 bottom of groove, due to groove 21
Bottom is there are damaging layer 22, and 21 side wall of groove is still high quality silicon, therefore the oxidation rate of 21 bottom of groove is faster, this
Sample, after oxidation, you can form the grid oxic horizon 23 of different-thickness in 21 bottom of groove and 21 side wall of groove.That is,
The thickness for being covered in the grid oxic horizon 23 of 21 bottom of groove is more than the grid for being covered in 21 internal perisporium of groove
The thickness of oxide layer 23.
The grid oxic horizon 23 is grid and emitter and the dielectric layer of collector, by electrostatics it is found that for ditch
Slot gate regions 20 and the capacitor of collector area composition and the capacitor of trench gate polar region 20 and emitter region composition are full
The following relational expression of foot：
C=ε S/L (1)
Wherein, ε is the dielectric constant of silicon dioxide dielectric, and S is in the capacitance that 21 grid of groove and collector are formed two
The area of a pole plate, L be the thickness of the distance between grid and collector namely silicon dioxide layer, by formula it is found that capacitance
Capacity is directly proportional to dielectric dielectric constant, directly proportional to the area of two pole plates, and the distance between two pole plates are into anti-
Than.When igbt is connected, collector area is connected to the outer wall of 21 grid of groove through drift region, thus and groove
The inner wall of 21 grids forms two pole plates of capacitance that 21 grid of groove and collector are formed, when increase 21 bottom grid oxygen of groove
When the thickness of change layer 23 is spent, then the distance increase of two pole plates, in the case where two polar plate areas and dielectric constant are constant,
Capacitance increases with the distance of two pole plates and is reduced.
The ON/OFF time of igbt and the parasitic capacitance direct proportionality namely parasitic capacitance are bigger,
The ON/OFF time of igbt is longer, this implementation is situated between by increasing by 21 bottom grid oxide layer 23 of groove namely electricity
The thickness of matter layer, so as to reduce parasitic capacitance, to realize the ON/OFF time longer purpose for shortening igbt,
Reduce the conducting power consumption of device.
It is understood that since the present embodiment only increases the thickness of igbt bottom grid oxide layer 23
Degree, and the thickness of 21 madial wall grid oxic horizon 23 of groove is constant, can set the thickness of 21 sidewall gate oxidation layer 23 of groove
Count relatively thin, so as to reduce the threshold voltage of well region transoid, that is, the turning-on voltage of IGBT, to reduce the conducting of device damage
Consumption.
The thickness of sidewall oxide decides the threshold voltage of well region transoid, that is, the turning-on voltage of IGBT, therefore ditch
The thickness of 21 oxide layer of slot is generally all made relatively thin, to reduce the driving voltage of IGBT.
Step S5, polysilicon is filled in the groove 21 to form polycrystal layer 24；
With reference to Fig. 4, in the present embodiment, the technologies such as mode chemical vapor deposition of polysilicon are filled in groove 21, in grid
Deposition forms polysilicon in pole oxide layer 23, then etches away the polysilicon other than groove 21 again or first prepares non-crystalline silicon, so
Afterwards again by technologies such as solid phase crystallization, laser crystallization and rapid thermal treatment crystallization, by amorphous crystallization of silicon into after polysilicon, filling with
In groove 21.
Step S6, insulating materials is covered in the top of the polycrystal layer 24 to form insulating layer from the first surface
25。
With reference to Fig. 5, in the present embodiment, thermal oxidation technology may be used, device is handled, grow polysilicon surface
Go out polysilicon oxide layer, polysilicon oxide layer is for insulating layer 25 or by the way of sputter in whole surface depositing insulating layer
25, the insulating layer 25 other than groove 21 is then etched away again, and it is silica, nitrogen that wherein the material of insulating layer 25, which can be material,
The good material of the insulating properties such as SiClx is made.
The present embodiment passes through inert particles or the oxygen such as argon particle, helium particle, neon particle when making grid oxic horizon 23
Agent bombards 21 bottom of groove, so as to which under the bombardment of the argon particle beams, damaging layer 22, the damaging layer 22 are formed at 21 bottom of groove
In there are it is more the defects of and dangling bonds.Since 21 side wall of groove is parallel with argon particle beams direction, 21 side wall of groove will not
By argon particle beam bombardment, the quality of 21 wall surface of groove is still very high, so as to which in oxidation, the oxidation rate of bottom is than groove 21
The oxidation rate of side wall is fast, in this way, under identical oxidizing condition, different-thickness is formed in 21 bottom of groove and 21 side wall of groove
Grid oxic horizon 23.That is, the thickness for being covered in the grid oxic horizon 23 of 21 bottom of groove, which is more than, is covered in groove
The thickness of the grid oxic horizon 23 of 21 internal perisporiums.So set, be conducive to the grid oxic horizon 23 of 21 bottom of groove is thick
Degree is designed thicker, so as to reduce parasitic capacitance, with the mesh that the ON/OFF time of realization shortening igbt is longer
, reduce the conducting power consumption of device.The thickness of 21 sidewall gate oxidation layer 23 of groove is designed relatively thin simultaneously, so as to reduce trap
The threshold voltage of area's transoid, that is, the turning-on voltage of IGBT, to reduce the conduction loss of device.
The present invention, which realizes, is shortening the ON/OFF time of igbt, while ensure insulated gate bipolar transistor
Pipe has preferably on state threshold voltage namely relatively low conduction voltage drop, is conducive to optimize conduction voltage drop and between switch time
Tradeoff.
Referring to figs. 1 to Fig. 5, it is to be understood that in above-described embodiment, the Semiconductor substrate 10 first surface into
The step of row etching is to form groove 21 and the bottom that the groove 21 is bombarded using inert particle and/or oxidant 30, with shape
Step is further included between the step of damaging layer 22：
Bottom and side wall to the groove 21 are aoxidized to form silicon dioxide layer, and the silicon dioxide layer is gone
It removes.
In the present embodiment, Semiconductor substrate 10 that 21 surface of groove is brought by reactive ion beam etching (RIBE), such as monocrystalline silicon
Damaging layer 22 forms silica；Then after removing silica so that 21 wall of groove is hindered namely ensured to 21 surface nondestructive of groove
The grid oxic horizon 23 of high quality can be formed, so that it is guaranteed that the conducting channel of the consistency of threshold voltage and high quality.
Referring to figs. 1 to Fig. 5, in a preferred embodiment, 22 thickness of damaging layer is more than 0.1um.
In the present embodiment, the bottom of the groove 21, the damage formed are bombarded by inert particle and/or oxidant 30
Layer 22 thickness be more than 0.1um, and the madial wall of groove 21 due to inert particle and/or oxidant 30 bombardment direction it is parallel,
So as to be unaffected, it is arranged such so that when forming grid oxic horizon 23,21 bottom of 21 madial wall of groove and groove
Grid oxic horizon 23 is respectively provided with preferably thickness, and ensures that electric field will not be weakened, and threshold voltage is caused to rise.Reduce grid simultaneously to penetrate
The capacitance of pole parasitic capacitance Cgc and grid and collector parasitic capacitance Cge, so as to shorten grid emitter-base bandgap grading parasitic capacitance Cge and
The charging time and discharge time of grid and collector parasitic capacitance Cgc, realize shorten igbt open with
The purpose of turn-off time.
Referring to figs. 1 to Fig. 5, in a preferred embodiment, the inert particle such as argon particle, neon particle etc. or such as oxygen original
The oxidants such as son bombarding energy is 0.2keV-500keV.The inert particle bombardment dosage is 1*e13-1*e16/cm2。
In the present embodiment, the particle beams emits after energy is obtained to 10 surface of Semiconductor substrate, so as in Semiconductor substrate
The formation lattice defect and dangling bonds on 10 surfaces, with when forming grid oxic horizon 23, accelerate oxygen and Semiconductor substrate 10 it
Between oxidation rate, therefore bombarding energy and dosage must reach certain value.In the present solution, it is by inert particle bombarding energy
0.2keV-500keV, it is preferable that the ion implantation energy is 70Kev.When ion implantation energy be less than 0.2keV when, then without
Method destroys 10 chemical attribute of Semiconductor substrate well, and be burdened with lattice defect and dangling bonds.And when example Implantation Energy is more than
During 500keV, then it may cause to occur to sputter and destroy Semiconductor substrate 10 over the semiconductor substrate 10.
Referring to figs. 1 to Fig. 5, in a preferred embodiment, when the inert particle bombards 21 bottom of groove, the inertia
The center density of particle is more than its marginal density.
In the present embodiment, when bombarding 21 bottom of groove, the density of ion beam can be adjusted, such as inertia
The center density of particle is more than its marginal density, and after non-uniform particle beam bombardment, damaging layer is formed in 21 bottom of groove
22 degree of different damaging layers 22, central area damage is more serious, and fringe region damage is lighter.Due to 21 area of bottom centre of groove
Domain damage is more serious, thus its dangling bonds is more, and oxidation rate is very fast, when carrying out gate oxidation, the grid oxic horizon of formation
23 is also thicker；The damage of 21 bottom edge region of groove is lighter, thus its dangling bonds is less, and oxidation rate is slower, the grid of formation
Oxide layer 23 is also relatively thin, so as to form the grid oxic horizon 23 of arc, compared to flat oxide layer, arc in 21 bottom of groove
Grid oxic horizon 23 can alleviate the right angle of integrated distribution of the electric field in 21 bottom of groove, especially 21 bottom of groove, and then keep away
Exempt from IGBT in 21 bottom of groove by too fast breakdown, be conducive to be promoted the voltage endurance capability of IGBT.
The present invention also proposes a kind of igbt.
With reference to Fig. 5, in an embodiment of the present invention, igbt includes：
Semiconductor substrate 10；
It is formed in the active area of 10 first surface of Semiconductor substrate (figure does not indicate)；
The active area includes trench gate polar region 20；The trench gate polar region 20 includes the from the Semiconductor substrate 10
Groove 21 that one surface opens up, the damaging layer 22 for being formed in 21 bottom of groove, are formed in the damaging layer 22 and the ditch
The grid oxic horizon 23 of the interior sidewall surface of slot 21, the polycrystal layer 24 being filled in the groove 21 and from the first surface cover
Insulating layer 25 in the top of the polycrystal layer 24.
It should be noted that when forming grid oxic horizon 23, formed damaging layer is bombarded to 21 bottom of groove
There are more lattice defect and dangling bonds in 22, and more dangling bonds can accelerate the chemistry of oxygen and Semiconductor substrate 10
Reaction speed.And with the degree of oxidation that grid oxic horizon 23 is formed in damaging layer 22, the thickness of damaging layer 22 can slowly subtract
Small, when aoxidizing abundant, damaging layer 22 may be substituted by grid oxic horizon 23 and be disappeared completely.
The present invention by inert particle or oxidant by when making grid oxic horizon 23, bombarding 21 bottom of groove
Portion, so as to form damaging layer 22 at 21 bottom of groove, in the damaging layer 22 there are it is more the defects of and dangling bonds so that 21 bottom of groove
The oxidation rate in portion is faster than the oxidation rate of 21 side wall of groove, in this way, under identical oxidizing condition, in 21 bottom of groove and groove
21 side walls form the grid oxic horizon 23 of different-thickness.That is, it is covered in the grid oxic horizon 23 of 21 bottom of groove
Thickness be more than be covered in 21 internal perisporium of groove the grid oxic horizon 23 thickness.So set, be conducive to groove 21
23 thickness of grid oxic horizon of bottom is designed thicker, so as to reduce parasitic capacitance, to realize shortening igbt
ON/OFF time longer purpose, reduce the conducting power consumption of device.The thickness of 21 sidewall gate oxidation layer 23 of groove is set simultaneously
Count relatively thin, so as to reduce the threshold voltage of well region transoid, that is, the turning-on voltage of IGBT, to reduce the conducting of device damage
Consumption.
The present invention, which realizes, is shortening the ON/OFF time of igbt, while ensure insulated gate bipolar transistor
Pipe has preferably on state threshold voltage namely conduction voltage drop, and there is preferable conduction voltage drop and the compromise between switch time to close
System.
It is understood that igbt of the present invention further includes emitter, well region, drift region and collector,
Its concrete structure can refer to conventional igbt setting.And its manufacturing process include ion implanting, surface oxidation,
Edge grid bipolar transistor production method in the routine techniques such as photoetching, details are not described herein again.
In the present embodiment, the thickness of the damaging layer 22 successively decreases from its central area to 21 madial wall of groove.
In the present embodiment, during by bombarding 21 bottom of groove, the center density of particle is more than its marginal density, makes
It is more serious to obtain the damage of 21 bottom center region of groove, thus its dangling bonds is more, oxidation rate is very fast, is carrying out gate oxidation
When, the grid oxic horizon 23 of formation is also thicker；The damage of 21 bottom edge region of groove is lighter, thus its dangling bonds is less, oxidation
Speed is slower, and the grid oxic horizon 23 of formation is also relatively thin, so as to form the grid oxic horizon 23 of arc in 21 bottom of groove, with slow
Right angle of the electric field in the integrated distribution, especially 21 bottom of groove of 21 bottom of groove is solved, and then avoids IGBT in groove 21
Bottom by too fast breakdown, be conducive to be promoted the voltage endurance capability of IGBT.
The present invention also proposes a kind of IPM modules, which includes the igbt, the insulated gate
The concrete structure of bipolar transistor is with reference to above-described embodiment, since IPM modules employ whole technologies of above-mentioned all embodiments
Scheme, therefore all advantageous effects at least caused by the technical solution with above-described embodiment, this is no longer going to repeat them.
It will be appreciated by persons skilled in the art that the IPM modules can include 4 insulated gate bipolar transistors
Pipe can also include 6 igbts, and the connecting tube relationship between the igbt is herein
It repeats no more.
The present invention also proposes a kind of air conditioner, and the air conditioner includes above-mentioned IPM modules.The IPM modules can be used for sky
It adjusts in main circuit or the control circuit of device, is not specifically limited herein.
The foregoing is merely the preferred embodiment of the present invention, are not intended to limit the scope of the invention, every at this
The equivalent structure transformation made under the inventive concept of invention using description of the invention and accompanying drawing content or directly/utilization indirectly
It is included in the scope of patent protection of the present invention in other related technical areas.
Claims (11)
- A kind of 1. grid making method of igbt, which is characterized in that the grid of the igbt Pole production method includes the following steps：Prepare Semiconductor substrate；It performs etching to form groove in the first surface of the Semiconductor substrate；The bottom of the groove is bombarded using inert particle and/or oxidant, to form damaging layer；Side wall and the damaging layer to the groove aoxidize, to form grid oxic horizon in the trench wall face；Polysilicon is filled in the trench to form polycrystal layer；Insulating materials is covered in the top of the polycrystal layer to form insulating layer from the first surface.
- 2. the grid making method of igbt as described in claim 1, which is characterized in that in the semiconductor The step of first surface of substrate is performed etching to form groove and utilization inert particle and/or oxidant bombard the groove Bottom, the step of to form damaging layer between further include step：Bottom and side wall to the groove are aoxidized to form silicon dioxide layer, and the silicon dioxide layer are removed.
- 3. the grid making method of igbt as described in claim 1, which is characterized in that be covered in the ditch The thickness of the grid oxic horizon of trench bottom is more than the thickness for the grid oxic horizon for being covered in groove internal perisporium.
- 4. the grid making method of igbt as described in claim 1, which is characterized in that the damage thickness Degree is more than 0.1um.
- 5. the grid making method of igbt as described in claim 1, which is characterized in that the inert particle And/or oxidant bombarding energy is 0.2keV-500keV.
- 6. the grid making method of igbt as described in claim 1, which is characterized in that the inert particle And/or oxidant bombardment dosage is 1*e13-1*e16/cm2。
- 7. the grid making method of the igbt as described in claim 1 to 6 any one, which is characterized in that When the inert particle bombards channel bottom, the center density of the inert particle is more than its marginal density.
- 8. a kind of igbt, which is characterized in that the igbt includes：Semiconductor substrate；It is formed in the active area of the Semiconductor substrate first surface；The active area includes trench gate polar region；The trench gate polar region includes opening up from the first surface of the Semiconductor substrate Groove, be formed in the damaging layer of the channel bottom, be formed in the grid of the damaging layer and the interior sidewall surface of the groove Oxide layer, the polycrystal layer being filled in the groove and be covered in from the first surface polycrystal layer top insulation Layer.
- 9. igbt as claimed in claim 8, which is characterized in that the thickness of the damaging layer is from its center Successively decrease to the groove madial wall in domain.
- 10. a kind of IPM modules, which is characterized in that including igbt as claimed in claim 8.
- 11. a kind of air conditioner, which is characterized in that the air conditioner includes IPM modules as claimed in claim 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711429620.7A CN108155231B (en) | 2017-12-22 | 2017-12-22 | Insulated gate bipolar transistor, gate manufacturing method thereof, IPM module and air conditioner |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711429620.7A CN108155231B (en) | 2017-12-22 | 2017-12-22 | Insulated gate bipolar transistor, gate manufacturing method thereof, IPM module and air conditioner |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108155231A true CN108155231A (en) | 2018-06-12 |
| CN108155231B CN108155231B (en) | 2021-07-27 |
Family
ID=62462926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711429620.7A Expired - Fee Related CN108155231B (en) | 2017-12-22 | 2017-12-22 | Insulated gate bipolar transistor, gate manufacturing method thereof, IPM module and air conditioner |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108155231B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109103180A (en) * | 2018-08-15 | 2018-12-28 | 深圳市金誉半导体有限公司 | A kind of power device chip and its manufacturing method |
| CN109473474A (en) * | 2018-11-09 | 2019-03-15 | 上海擎茂微电子科技有限公司 | Insulated trench gate electrode bipolar type transistor device and its generation method |
| CN112067967A (en) * | 2020-09-25 | 2020-12-11 | 上海大学 | Device switching loss-based power electronic online reliability state detection device and method |
| CN112864249A (en) * | 2021-01-11 | 2021-05-28 | 江苏东海半导体科技有限公司 | Low-grid-leakage-charge groove type power semiconductor device and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6228720B1 (en) * | 1999-02-23 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Method for making insulated-gate semiconductor element |
| US20010026989A1 (en) * | 2000-04-04 | 2001-10-04 | International Rectifier Corp. | Low voltage power MOSFET device and process for its manufacture |
| US6489652B1 (en) * | 1995-11-11 | 2002-12-03 | Fairchild Semiconductor Corporation | Trench DMOS device having a high breakdown resistance |
| CN102054702A (en) * | 2009-11-09 | 2011-05-11 | 上海华虹Nec电子有限公司 | Method for manufacturing groove power MOSFET device |
| US20110230025A1 (en) * | 2008-12-12 | 2011-09-22 | Niko Semiconductor Co., Ltd. | Fabrication method of trenched metal-oxide-semiconductor device |
-
2017
- 2017-12-22 CN CN201711429620.7A patent/CN108155231B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6489652B1 (en) * | 1995-11-11 | 2002-12-03 | Fairchild Semiconductor Corporation | Trench DMOS device having a high breakdown resistance |
| US6228720B1 (en) * | 1999-02-23 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Method for making insulated-gate semiconductor element |
| US20010026989A1 (en) * | 2000-04-04 | 2001-10-04 | International Rectifier Corp. | Low voltage power MOSFET device and process for its manufacture |
| US20110230025A1 (en) * | 2008-12-12 | 2011-09-22 | Niko Semiconductor Co., Ltd. | Fabrication method of trenched metal-oxide-semiconductor device |
| CN102054702A (en) * | 2009-11-09 | 2011-05-11 | 上海华虹Nec电子有限公司 | Method for manufacturing groove power MOSFET device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109103180A (en) * | 2018-08-15 | 2018-12-28 | 深圳市金誉半导体有限公司 | A kind of power device chip and its manufacturing method |
| CN109103180B (en) * | 2018-08-15 | 2023-09-05 | 深圳市金誉半导体股份有限公司 | Power device chip and manufacturing method thereof |
| CN109473474A (en) * | 2018-11-09 | 2019-03-15 | 上海擎茂微电子科技有限公司 | Insulated trench gate electrode bipolar type transistor device and its generation method |
| CN112067967A (en) * | 2020-09-25 | 2020-12-11 | 上海大学 | Device switching loss-based power electronic online reliability state detection device and method |
| CN112864249A (en) * | 2021-01-11 | 2021-05-28 | 江苏东海半导体科技有限公司 | Low-grid-leakage-charge groove type power semiconductor device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108155231B (en) | 2021-07-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108155231A (en) | Igbt and its grid making method, IPM modules and air conditioner | |
| JP2006261703A (en) | Mesa separated silicon on insulator transistor and manufacturing method of the same | |
| JPS6336147B2 (en) | ||
| US7714396B2 (en) | Metal-oxide semiconductor field effect transistor | |
| US20060141726A1 (en) | Field effect transistor with a high breakdown voltage and method of manufacturing the same | |
| CN104103515A (en) | Manufacturing method for PMOS transistor and manufacturing method for NMOS transistor | |
| CN108538911B (en) | Optimized L-type tunneling field effect transistor and preparation method thereof | |
| CN106876368A (en) | A kind of semiconductor field positive feedback devices | |
| WO2019119861A1 (en) | Manufacturing method for finfet device | |
| CN103681315A (en) | Method for forming buried layer | |
| US9312378B2 (en) | Transistor device | |
| CN103579003A (en) | Method for manufacturing super joint MOSFET | |
| CN102097463B (en) | Semi self-aligned bipolar transistor and manufacturing method thereof | |
| CN117253924A (en) | Silicon carbide LDMOS and preparation method | |
| CN115332329A (en) | IGBT device with deep buffer layer high-density groove and preparation method thereof | |
| CN113838914A (en) | RET IGBT device structure with separation gate structure and manufacturing method | |
| CN103915335B (en) | The forming method of semiconductor device | |
| CN109411347A (en) | Triode and preparation method thereof | |
| CN103377939B (en) | The manufacture method of trench power semiconductor structure | |
| CN106257646B (en) | It is embedded in the CMOS production method of PIP capacitor | |
| CN103811324A (en) | Fin type field effect transistor forming method | |
| CN103811325B (en) | The forming method of fin field effect pipe | |
| JPH05326556A (en) | Manufacture of semiconductor device | |
| US20220320310A1 (en) | Method of forming asymmetric thickness oxide trenches | |
| JPS5972174A (en) | Semiconductor device and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20210727 |