CN109411347A - Triode and preparation method thereof - Google Patents
Triode and preparation method thereof Download PDFInfo
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- CN109411347A CN109411347A CN201811286546.2A CN201811286546A CN109411347A CN 109411347 A CN109411347 A CN 109411347A CN 201811286546 A CN201811286546 A CN 201811286546A CN 109411347 A CN109411347 A CN 109411347A
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 146
- 229920005591 polysilicon Polymers 0.000 claims abstract description 143
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 238000005530 etching Methods 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 6
- 239000001301 oxygen Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 43
- 238000000926 separation method Methods 0.000 claims description 16
- 230000026267 regulation of growth Effects 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 12
- 230000006378 damage Effects 0.000 abstract description 10
- 208000027418 Wounds and injury Diseases 0.000 abstract description 9
- 230000003321 amplification Effects 0.000 abstract description 7
- 208000014674 injury Diseases 0.000 abstract description 7
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 238000000407 epitaxy Methods 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical group [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052787 antimony Inorganic materials 0.000 description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000007521 mechanical polishing technique Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66265—Thin film bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7317—Bipolar thin film transistors
Abstract
The invention discloses a kind of triode and preparation method thereof, this method makes well region by the upper surface grown epitaxial layer in substrate；Epitaxial layer is doped and forms base area in the epitaxial layer；Emitter polysilicon layer is formed in the upper surface of the base area；Heat is carried out under an oxygen-containing atmosphere to drive in, and forms emitter region in the base area；Oxide layer is grown in the outer surface of the emitter polysilicon layer；Base polysilicon layer is formed in the upper surface of the base area；Form the collector of the emitter for connecting the emitter polysilicon layer, the base stage of the connection base polysilicon layer and the connection well region.The production method of triode of the present invention is by being initially formed emitter polysilicon layer; emitter region-base area interface is protected using the emitter polysilicon layer; to avoid causing etching injury to the emitter region-base area interface during making triode, and then guarantee the stability of the amplification coefficient of the triode.
Description
Technical field
The present invention relates to technical field of semiconductors, especially a kind of triode and preparation method thereof.
Background technique
Triode is also referred to as bipolar junction transistor comprising base area, emitter region and collecting zone, when lesser electric current is injected in base area
When, it will form biggish electric current between emitter region and collecting zone, here it is the Current amplifier effects of triode.In triode
In, electrons and holes simultaneously participate in conduction.Single the small in size, light-weight of triode, little power consumption, service life length, high reliablity, because
This triode is widely used in the neck such as broadcast, TV, communication, radar, computer, self-con-tained unit, electronic instrument, household electrical appliance
Domain, the effects of playing amplification, oscillation, switch.
It, can be in one dielectric layer of upper surface growth regulation of the epitaxial layer, to institute in the production method of general triode
First medium layer is stated to carry out through etching to form first window；It is heavy in the upper surface of the epitaxial layer by the first window
The doping of the impurity of the first conduction type of doping is injected to the intrinsic polycrystal layer later and formed to product intrinsically polysilicon layer
Polysilicon layer；Oxide layer is grown in the upper surface of the doped polysilicon layer；Photoetching and through etching the oxide layer and described
Doped polysilicon layer forms the second window.In above-mentioned steps, in order to avoid the emitter and base stage of the triode of formation are short
Road then must assure that the doped polysilicon layer in second window of formation is etched completely away.In general, in order to complete
The doped polysilicon layer in second window is removed entirely, needs to carry out over etching to the doped polysilicon layer, at once
The depth of erosion is slightly larger than the thickness of the doped polysilicon layer.Since the doped polysilicon layer directly connects with the epitaxial layer
It connects, the doped polysilicon layer described in over etching during inevitably causes etching injury to the epitaxial layer.Pass through institute
State the base area that the second window injects the epitaxial layer and forms the first conduction type in the epitaxial layer；It carries out
The impurity of first time high-temperature heat treatment, first conduction type in the doped polysilicon layer is spread simultaneously to the epitaxial layer
The base contact area for connecting the first conduction type of the base area is formed in the epitaxial layer；By second window in institute
The upper surface deposition second dielectric layer for stating base area, connects the doped polysilicon layer through etching the second dielectric layer and being formed
With the side wall and third window of the oxide layer.Etching can be also caused to damage to the epitaxial layer when etching forms the side wall
Wound.In the fabrication of above-mentioned triode, either doped polysilicon layer described in over etching still forms the side wall, all can
Emitter region-base area interface damage is caused, is asked so as to cause unstable, the electric leakage increase of amplification coefficient etc. of the triode of formation
Topic.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of production method of triode, this method can effectively avoid transmitting
Area-base area interface damage, to promote the stability and yield of the amplification coefficient of triode.
In order to solve the above technical problems, the present invention adopts the following technical solutions: the production method of the triode includes
S01: provide substrate, the substrate include the first conduction type substrate, be located at the substrate in and at least partly
It is exposed to the buried layer of the second conduction type of the upper surface of the substrate and positioned at the upper surface of the substrate and the buried layer
The epitaxial layer of second conduction type；Secondth area in the firstth area and adjacent firstth area is provided on the substrate, described the
It is formed through the epitaxial layer in 2nd area and extends to the well region of the second conduction type of the buried layer；
S02: in one dielectric layer of upper surface growth regulation of the epitaxial layer, to the first medium layer carry out through etching with
Form the window in corresponding firstth area；
S03: being doped the epitaxial layer by the window and the first conduction type is formed in the epitaxial layer
Base area, the base area is located in firstth area；
S04: the doped polysilicon layer of the impurity of the second conduction type of doping is formed in the upper surface of the base area；Removal one
The part doped polysilicon layer keeps the upper surface of the base area locally exposed to form the hair positioned at the upper surface of the base area
Emitter polysilicon layer；
S05: under an oxygen-containing atmosphere carry out heat drive in, second conduction type in the emitter polysilicon layer it is miscellaneous
Matter spreads to the base area and forms emitter region in the base area, and simultaneously in the upper surface of the exposed base area and described
The outer surface of emitter polysilicon layer grows oxide layer；
S06: etching the oxide layer and only retains the outer surface that the oxide layer is located at the emitter polysilicon layer
Part；
S07: the base polysilicon layer of the impurity of the first conduction type of doping is formed in the upper surface of the base area；
S08: second medium is grown in the upper surface of the oxide layer, the base polysilicon layer and the first medium layer
Layer；
S09: the transmitting through the second dielectric layer and the oxide layer and the corresponding emitter polysilicon layer is formed
Pole contact hole is situated between through the base stage contact hole of the second dielectric layer and the corresponding base polysilicon layer, through described second
The collector contact hole of matter layer and the first medium layer and the corresponding well region；
S10: the emitter for connecting the emitter polysilicon layer, the base stage of the connection base polysilicon layer and company are formed
Connect the collector of the well region.
The production method of triode of the present invention utilizes the emitter polycrystalline by being initially formed emitter polysilicon layer
Silicon layer protects emitter region-base area interface, to avoid during making triode to the emitter region-base area circle
Etching injury is caused in face, and then guarantees the stability of the amplification coefficient of the triode.
Correspondingly, the present invention also provides a kind of triode, which includes:
Substrate, the substrate include the substrate of the first conduction type, in the substrate and are at least partly exposed to institute
State the buried layer of the second conduction type of the upper surface of substrate and the second conduction positioned at the upper surface of the substrate and the buried layer
The epitaxial layer of type；Secondth area in the firstth area and adjacent firstth area is provided on the substrate；
Positioned at secondth area, through the epitaxial layer and extend to the buried layer the second conduction type well region；
Positioned at firstth area and the base area of the first conduction type in the epitaxial layer；
The emitter region of the second conduction type in the base area；
First medium layer positioned at the upper surface of the epitaxial layer；
Window through the first medium layer and the corresponding base area；
In the window and the emitter polysilicon layer of the connection emitter region；
Oxide layer positioned at the outer surface of the emitter polysilicon layer；
In the window and the base polysilicon layer of the connection base area；
Second dielectric layer positioned at the oxide layer, the upper surface of the base polysilicon layer and the first medium layer；
Through the emitter of the second dielectric layer and the oxide layer and the connection emitter polysilicon layer, run through institute
State the base stage of second dielectric layer and the connection base polysilicon layer, through the second dielectric layer and the first medium layer and
Connect the collector contact hole of the well region.
The emitter polysilicon layer of triode of the present invention can protect emitter region-base area interface, to avoid
Etching injury is caused to the emitter region-base area interface during making triode, and then guarantees putting for the triode
The stability of big coefficient.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the flow diagram of the production method for the triode that one embodiment of the invention provides；
Fig. 2 to Figure 13 is the schematic diagram of the section structure of the forming process for the triode that one embodiment of the invention provides；
Figure 14 is the schematic diagram of the section structure for the triode that one embodiment of the invention provides.
Description of symbols:
1: substrate；A: the first area；B: the second area；10: substrate；11: buried layer；20: epitaxial layer；21: isolated groove；21a: the
One isolated groove；21b: the second isolated groove；22: separation layer；22a: the first separation layer；22b: the second separation layer；23: well region；
23a: the first well region；23b: the second well region；30: first medium layer；31: window；50: doped polysilicon layer；70: oxide layer；40:
Base area；81: base contact area；90: second dielectric layer；51: emitter polysilicon layer；60: emitter region；80: base polysilicon layer；
101: emitter contact hole；102: base stage contact hole；103: collector contact hole；111: emitter；112: base stage；113: current collection
Pole.
Specific embodiment
Emitter region-base area to triode is easy during present invention is generally directed to use conventional method to make triode
The problem of etching injury is caused to provide a solution in interface.
It is clear in order to be more clear the purpose of the present invention, technical solution and advantageous effects, below in conjunction with this hair
Attached drawing in bright embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described
Embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field
Those of ordinary skill's every other embodiment obtained without making creative work, belongs to protection of the present invention
Range.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
Special to illustrate herein for convenience of subsequent description: first conduction type can be N-type, then, described second leads
Electric type is p-type, conversely, first conduction type may be p-type, correspondingly, second conduction type is N-type.?
In next embodiment, retouched so that first conduction type is p-type and second conduction type is N-type as an example
It states, but is defined not to this.
Referring to Fig. 1, a kind of production method of triode comprising following steps:
S01: providing substrate 1, and the substrate 10 of the substrate 1 including the first conduction type is located in the substrate 10 and extremely
Small part is exposed to the buried layer 11 of the second conduction type of the upper surface of the substrate 10 and positioned at the substrate 10 and described buries
The epitaxial layer 20 of second conduction type of the upper surface of layer 11；The first area A and adjacent firstth area are provided on the substrate 1
The second area B of A is formed through the epitaxial layer 20 in the secondth area B and extends to the second conduction of the buried layer 11
The well region 23 of type；
S02: in one dielectric layer 30 of upper surface growth regulation of the epitaxial layer 20, the first medium layer 30 is run through
Etching corresponds to the window 31 of the firstth area A to be formed；
S03:, which being doped the epitaxial layer 20 by the window 31, and first is formed in the epitaxial layer 20 leads
The base area 40 of electric type, the base area 40 are located in the firstth area A；
S04: the doped polysilicon layer 50 of the impurity of the second conduction type of doping is formed in the upper surface of the base area 40；It goes
Except a part of doped polysilicon layer 50 makes the upper surface of the base area 40 is locally exposed to be located at the base area 40 to be formed
The emitter polysilicon layer 51 of upper surface；
S05: carrying out heat under an oxygen-containing atmosphere and drive in, second conduction type in the emitter polysilicon layer 51
Impurity spreads to the epitaxial layer 50 and forms emitter region 60 in the base area 40, and simultaneously in the exposed base area 40
Upper surface and the outer surface of the emitter polysilicon layer 51 grow oxide layer 70；
S06:, which etching the oxide layer 70, and only retains the oxide layer 70 is located at the outer of the emitter polysilicon layer 51
The part on surface；
S07: the base polysilicon layer 80 of the impurity of the first conduction type of doping is formed in the upper surface of the base area 40；
S08: in the upper surface growth regulation of the oxide layer 70, the base polysilicon layer 80 and the first medium layer 30
Second medium layer 90；
S09: it is formed through the second dielectric layer 90 and the oxide layer 70 and the corresponding emitter polysilicon layer 51
Emitter contact hole 101, through the second dielectric layer 90 and the base stage contact hole of the corresponding base polysilicon layer 80
102, through the collector contact hole 103 of the second dielectric layer 90 and the first medium layer 30 and the corresponding well region 23；
S10: it is formed and connects the emitter 111 of the emitter polysilicon layer 51, connects the base polysilicon layer 80
Base stage 112 and the collector 103 for connecting the well region 23.
The production method of triode of the present invention is more using the emitter by being initially formed emitter polysilicon layer 51
Crystal silicon layer 51 protects emitter region-base area interface, to avoid during subsequent production triode to the transmitting
Etching injury is caused at area-base area interface, and then guarantees the stability of the amplification coefficient of the triode.
With reference to the accompanying drawings, described triode and preparation method thereof is elaborated.
Fig. 2 and Fig. 3 are please referred to, step S01 is executed: offer substrate 1 first.In the longitudinal direction, the substrate 1 includes substrate
10, it in the substrate 10 and is at least partly exposed to the buried layer 11 of the upper surface of the substrate 10 and is located at the substrate 10
And the epitaxial layer 20 of the upper surface of the buried layer 11.The longitudinal direction is the thickness direction of the substrate 1.Horizontally, the base
The second area B of the first area A and the adjacent firstth area A are provided on piece 1.The transverse direction is the width direction of the substrate 1.?
In the present embodiment, the substrate 1 includes the firstth area A and two the secondth area B, the firstth area A positioned at described
The middle position of substrate 1, the secondth area B are located at the two sides of the firstth area A.
Specifically, carrier of the substrate 10 as triode, primarily serves the effect of support.In the present embodiment, institute
Stating substrate 10 is silicon substrate, and silicon is most common, cheap and stable performance semiconductor material, can effectively reduce cost and is promoted
Yield.In other embodiments, the material of the substrate 10 can also be silicon carbide, germanium or germanium silicon etc..In detail, at this
Substrate 10 described in embodiment is the first conduction type.In the present embodiment, first conduction type is p-type, therefore described
Substrate 10 is P-type semiconductor.In other embodiments, first conduction type may be N-type, therefore, the substrate 10
As N-type semiconductor.The P type substrate 10 can adulterate the elements such as boron, aluminium, indium by silicon and be formed, and be not limited thereto.More in detail
Carefully, the substrate 10 is the semiconductor being lightly doped.In the present embodiment, the P type substrate 10 is to adulterate the p-type of low concentration
The P- substrate 10 of impurity.
Further, buried layer 11 is formed in the substrate 10.The buried layer 11 is at least partly exposed to the substrate 10
Upper surface.In detail, the buried layer 11 is the second conduction type.In the present embodiment, second conduction type is N-type, because
This described buried layer 11 is N-type semiconductor.In other embodiments, second conduction type may be p-type, therefore, described
Buried layer 11 is then P-type semiconductor.
Specifically, in the present embodiment, the n type buried layer 11 can be by adulterating phosphorus, arsenic, antimony etc. in the substrate 10
Element is formed, and is not limited thereto.The doping way includes thermal diffusion and ion implanting.In the present embodiment preferably using from
The mode of son injection.The ion implanting has purity is high, and good evenness can accurately control implantation dosage and depth, temperature compared with
It is low, it is not susceptible to thermal defect, the multiple advantages such as selective area injection can be carried out as exposure mask using photoresist or metal.More
Specifically, the buried layer 11 is formed the following steps are included: covering a layer photoresist layer (figure in the upper surface of the P type substrate 10
Do not show), the photoresist layer is exposed as exposure mask using the mask plate with 11 figure of buried layer later, then carries out
Development is formed and the consistent window (not shown) of 11 figure of buried layer on the photoresist layer；With photoresist layer work
For exposure mask, local doping is carried out to the P type substrate 10 from the window of the photoresist layer by the way of ion implanting, and is made
Obtaining the 10 regional area transoid of P type substrate becomes N-type, that is, forms the n type buried layer 11.
Further, in the substrate 10 and the upper surface grown epitaxial layer 20 of the buried layer 11.In the present embodiment, institute
Stating epitaxial layer 20 is preferably silicon epitaxy layer.In detail, the epitaxial layer 20 is the second conduction type.In the present embodiment, described
Second conduction type is N-type, therefore the epitaxial layer 20 is N-type semiconductor.In other embodiments, second conduction type
It may be p-type, therefore, the epitaxial layer 20 is then P-type semiconductor.The N-type epitaxy layer 20 can by silicon adulterate phosphorus,
The elements such as arsenic, antimony are formed, and are not limited thereto.In more detail, the epitaxial layer 20 is the semiconductor being lightly doped.In the present embodiment
In, the N-type epitaxy layer 20 is to adulterate the N- epitaxial layer 20 of the N-type impurity of low concentration.The purpose being lightly doped is guaranteed outside described
Prolong layer 20 with biggish resistance value so that it can bear biggish voltage, to promote the breakdown potential of the triode
Pressure.
Specifically, the epitaxial layer 20 is grown in the upper surface of the substrate 10 and the buried layer 11 using epitaxy method.
The epitaxy method includes depositing operation, and the depositing operation can be selected from electron beam evaporation, chemical vapor deposition, atomic layer
One of deposition, sputtering.Preferably, in the present embodiment using chemical vapor deposition in the substrate 10 and the buried layer 11
Upper surface form the epitaxial layer 20.
Further, isolated groove 21 is formed in the secondth area B by etching, the isolated groove 21 is through described
The bottom of epitaxial layer 20 and the buried layer 11 and the isolated groove 21 extends in the substrate 10.In the present embodiment, institute
Stating isolated groove 21 includes the first isolated groove 21a and the second isolated groove 21b, the first isolated groove 21a and described the
Two isolated groove 21b are located at the both ends of the buried layer 11.Separation layer 22 is grown in the isolated groove 21 later.It is described
Separation layer 22 includes the first separation layer 22a being filled in the first isolated groove 21a and is filled in second isolating trenches
The second separation layer 22b in slot 21b.The separation layer 22 can be made of oxide, such as silica, can also be by aoxidizing
Object and polysilicon composition.
Further, well region 23 is formed in the secondth area B, the well region 23 is through the epitaxial layer 20 and extends to
In the buried layer 11.Specifically, the well region 23 is located at the isolated groove 21 close to the side of the firstth area A.In detail,
The well region 23 is the second conduction type.In the present embodiment, second conduction type is N-type, therefore the well region 23 is N
Type semiconductor.In other embodiments, second conduction type may be p-type, and therefore, the well region 23 is then p-type half
Conductor.In the present embodiment, the N-type well region 23 can be by further adulterating the elements such as phosphorus, arsenic, antimony to the epitaxial layer 20
It is formed, is not limited thereto.In the present embodiment, the well region 23 includes the first well region 23a and the second well region 23b, and described the
One well region 23a is located at the first isolated groove 21a close to the side of the firstth area A, and the second well region 23b is located at described
Second isolated groove 21b is close to the side of the firstth area A, it will be understood that the first well region 23a and second well region
23b is located at simultaneously between the first isolated groove 21a and the second isolated groove 21b.
Referring to Fig. 4, executing step S02: in one dielectric layer 30 of upper surface growth regulation of the epitaxial layer 20.Described first
Dielectric layer 30 is preferably oxide layer.Further, partial penetration etching is carried out to form 31 institute of window to the first medium layer 30
State the corresponding firstth area A of window 31.In the present embodiment, the window 31 is located at the first well region 23a relatively described
The side of one isolated groove 21a and the side for being located at the relatively described second isolated groove 21b of the second well region 23b, Ke Yili
Solution, the window 31 is between the first well region 23a and the second well region 23b.
Referring to Fig. 5, executing step S03: carrying out local doping to the epitaxial layer 20 by the window 31, and in institute
It states and forms base area 40 in epitaxial layer, the base area 40 is located in the firstth area A.In detail, the base area 40 is first conductive
Type, in the present embodiment, first conduction type are p-type, therefore the base area 40 is P-type semiconductor.In other implementations
In example, first conduction type may be N-type, and therefore, the base area 40 is N-type semiconductor.The p-type base area 40 can
To be formed by adulterating the elements such as boron, aluminium, indium to the epitaxial layer 20, it is not limited thereto.
Specifically, in the present embodiment, the p-type base area 40 can be by adulterating boron, aluminium, indium in the epitaxial layer 20
Equal elements are formed, and are not limited thereto.The doping way includes thermal diffusion and ion implanting.It preferably uses in the present embodiment
The mode of ion implanting carries out local doping to the N-type epitaxy layer 20 from the window 31, and makes the epitaxial layer 20 innings
Portion region transoid becomes p-type, that is, forms the base area 40.
Fig. 6 and Fig. 7 are please referred to, executes step S04: firstly, the upper table in the base area 40 and the first medium layer 30
The first intrinsically polysilicon layer (not shown) that length of looking unfamiliar is made of intrinsic polysilicon.The intrinsic polysilicon is undoped more
Crystal silicon.Specifically, first intrinsically polysilicon layer can be grown by the way of deposition.
Further, to the impurity of described first intrinsic the second conduction type of doping polycrystalline silicon layer, thus by the first
Sign polysilicon layer is converted into doped polysilicon layer 50.Specifically, in the present embodiment, it is preferred to use the mode of ion implanting is to institute
The first intrinsically polysilicon layer is stated to be doped.In the present embodiment, the second conduction type is N-type, then second conduction type
Impurity be N-type impurity.In other embodiments, when second conduction type is p-type, then second conduction type is miscellaneous
Matter is p type impurity.It is highly preferred that the N-type impurity is arsenic ion.Compared to phosphonium ion, the diffusion coefficient of arsenic ion is smaller, this
Sample arsenic ion during subsequent hot injection process, which was not susceptible to diffusion, causes the arsenic ion to break through the base area 40, from
And the triode to be formed is failed.During ion implanting, the implantation dosage of impurity is preferably 1E16-3E16/cm2。
There are also Implantation Energies by the thickness effect of the doped polysilicon layer 50, and the usual doped polysilicon layer 50 is thicker, injects energy
It measures higher.
Further, a part of doped polysilicon layer 50 is removed by photoetching and etching.In detail, removal is located at institute
The doped polysilicon layer 50 and part of stating the upper surface of first medium layer 30 are located at the described of the upper surface of the base area 40
Doped polysilicon layer 50 is formed simultaneously so that the upper surface of the base area 40 is locally exposed positioned at the upper of the base area 40
The emitter polysilicon layer 51 on surface.It is appreciated that the emitter polysilicon layer 51 is that the doping that is not etched away is more
Crystal silicon layer 50 is constituted, and the composition of the emitter polysilicon layer 51 is the impurity that intrinsic polysilicon adulterates the second conduction type.
In the present embodiment, the preferably described emitter polysilicon layer 51 is located at the middle position of the upper surface of the base area 40.It needs
It is bright, it is preferably more to the doping when etching the doped polysilicon layer 50 to form the emitter polysilicon layer 51
Crystal silicon layer 50 carries out over etching, that is, the depth etched is greater than the thickness of the doped polysilicon layer 50, to completely remove the base
Polysilicon of the upper surface in area 40 in addition to the emitter polysilicon layer 51, thus the emitter of the triode avoided the formation of and
Short circuit occurs for base stage, but in the process of the etching not to the emitter region-base contact interface quarter for causing the triode
Deteriorate wound, and then guarantees the stabilization of the amplification coefficient of the triode.
Referring to Fig. 8, executing step S05: carrying out heat under an oxygen-containing atmosphere and drive in.The temperature that the heat drives in is preferably
950-1050℃.During heat drives in, the impurity in the base area 40 continues to spread into the epitaxial layer 20, so that
The range of the base area 40 becomes larger；Meanwhile the impurity of second conduction type in the emitter polysilicon layer 51 is to institute
The diffusion of base area 40 is stated, and makes the regional area transoid of the base area 40, is led to form second be located in the base area 40
The emitter region 60 of electric type；Simultaneously in addition, upper surface and hair under the conditions of high temperature is oxygen-containing, in the exposed base area 40
The outer surface of emitter polysilicon layer 51 grows oxide layer 70.In the present embodiment, the oxide layer 70 is silicon dioxide layer.It is described
The outer surface of emitter polysilicon layer 51 refers to upper surface and the both side surface of the emitter polysilicon layer 51.
Referring to Fig. 9, executing step S06: a part of oxide layer 70 is removed by photoetching and etching, so that the base
The upper surface in area 40 is locally exposed, and retains the portion that the oxide layer 70 is located at the outer surface of the emitter polysilicon layer 51
Point.It should be noted that preferably carrying out over etching, that is, the depth etched to the oxide layer 70 when etching the oxide layer 70
Degree is greater than the thickness of the oxide layer 70, equally in the process of the etching also not to the emitter region-base area for causing the triode
The etching injury of contact interface.
It please refers to Figure 10 and Figure 11, executes step S07: firstly, in the upper of the base area 40 and the first medium layer 30
Surface grows the second intrinsically polysilicon layer (not shown) being made of intrinsic polysilicon.It specifically, can be by the way of deposition
Grow second intrinsically polysilicon layer.
Further, the impurity that the first conduction type is adulterated to second intrinsically polysilicon layer, thus by described second
Sign polysilicon layer is converted into base polysilicon layer 80.Specifically, in the present embodiment, it is preferred to use the mode of ion implanting is to institute
The second intrinsically polysilicon layer is stated to be doped.In the present embodiment, the first conduction type is p-type, then first conduction type
Impurity be p type impurity.In other embodiments, when first conduction type is N-type, then first conduction type is miscellaneous
Matter is N-type impurity.
Further, a part of base polysilicon layer 80 is removed by photoetching and etching.In detail, removal a part
The base polysilicon layer 80 positioned at the upper surface of the first medium layer 30, to make the finally obtained base stage polycrystalline
Silicon layer 80 is located at the side of the relatively described isolated groove 11 of the well region 23.In the present embodiment, the base polysilicon layer 80
Between the first well region 23a and the second well region 23b.
Further, it is heat-treated, so that the impurity of first conduction type in the base polysilicon layer 80
It is spread to the base area 40, and forms base contact area 81, the doping concentration in the base contact area 81 in the base area 40
The doping concentration of the base area 40 is high, and the base contact resistance of triode can be effectively reduced in the base contact area 81.
Figure 12 is please referred to, step S08 is executed: being situated between in the oxide layer 70, the base polysilicon layer 80 and described first
The upper surface of matter layer 30 grows second dielectric layer 90.The effect of the second dielectric layer 90 is to oxide layer 70, the base stage
Polysilicon layer 80 and the first medium layer 30 carry out insulation blocking.In detail, the second dielectric layer 90 is the phosphorus silicon of boracic
Glass (BPSG).In other embodiments, the second dielectric layer 90 can be the phosphorosilicate glass (PSG) of not boracic, can also be with
It is undoped silica glass (USG), can also be depositing silica at low pressure (LPTEOS).
Specifically, the second dielectric layer 90 is formed to include the following steps: first using chemical vapour deposition technique described
The upper surface of oxide layer 70, the base polysilicon layer 80 and the first medium layer 30 grows the second dielectric layer 90；Into
One step carries out planarization process to the upper surface of the second dielectric layer 90.In detail, using chemically mechanical polishing
The mode of (Chemical Mechanical Polishing, CMP) planarizes the upper surface of the second dielectric layer 90
Processing.Chemical Mechanical Polishing Technique organically combines the mechanical abrasive action of abrasive grain with the chemical action of oxidant, can
It realizes the not damaged surface processing of ultraprecise, meets characteristic size in 0.35 μm of global planarizartion requirement below.It is specific at other
In embodiment, planarization process can also be carried out to the upper surface of the second dielectric layer 90 by the way of dry etching.
Please refer to Figure 13, execute step S09: the corresponding emitter polysilicon layer 51 is through the etching second dielectric layer
90 and the oxide layer 70, to form emitter contact hole 101；It is appreciated that the emitter contact hole 101 is through described
Second dielectric layer 90 and the oxide layer 70 and the corresponding emitter polysilicon layer 51.
The corresponding base polysilicon layer 80 is through the second dielectric layer 90 is etched, to form base stage contact hole 102；
It is appreciated that the base stage contact hole 102 is through the second dielectric layer 90 and the corresponding base polysilicon layer 80.
The corresponding well region 23 is through the second dielectric layer 90 and the first medium layer 30 is etched, to form current collection
Pole contact hole 103；It is appreciated that the second dielectric layer 90 and the first medium layer are run through in the collector contact hole 103
30 and the corresponding well region 23.
Figure 14 is please referred to, executes step S10: in the emitter contact hole 101, the base stage contact hole 102, the collection
The upper surface deposited metal layer (not shown) of electrode contact hole 103 and the second dielectric layer 90.Further, the metal is etched
Layer and 112 and of base stage for forming the emitter 111 for connecting the emitter polysilicon layer 51, the connection base polysilicon layer 80
Connect the collector 113 of the well region 23.
Please refer to Figure 14, a kind of triode comprising:
Substrate 1, the substrate 10 of the substrate 1 including the first conduction type, be located at it is in the substrate 10 and at least partly sudden and violent
It is exposed to the buried layer 11 of the second conduction type of the upper surface of the substrate 10 and positioned at the upper of the substrate 10 and the buried layer 11
The epitaxial layer 20 of second conduction type on surface；The second of the first area A and the adjacent firstth area A is provided on the substrate 1
Area B；
Positioned at the secondth area B, through the epitaxial layer 20 and extend to the buried layer 11 the second conduction type trap
Area 23；
Positioned at the base area 40 of the firstth area A and the first conduction type in the epitaxial layer 20；
The emitter region 60 of the second conduction type in the base area 40；
First medium layer 30 positioned at the upper surface of the epitaxial layer；
Window 31 through the first medium layer 30 and the corresponding base area 40；
In the window 31 and the emitter polysilicon layer 51 of the connection emitter region 60；
Oxide layer 70 positioned at the outer surface of the emitter polysilicon layer 51；
In the window 31 and the base polysilicon layer 80 of the connection base area 40；
Second Jie positioned at the oxide layer 70, the upper surface of the base polysilicon layer 80 and the first medium layer 30
Matter layer 90；
Through the emitter of the second dielectric layer 90 and the oxide layer 70 and the connection emitter polysilicon layer 51
111, through the second dielectric layer 90 and the base stage 112 of the connection base polysilicon layer 80, run through the second dielectric layer
90 and the first medium layer 30 and the connection well region 23 collector 113.
Specifically, carrier of the substrate 10 as triode, primarily serves the effect of support.In the present embodiment, institute
Stating substrate 10 is silicon substrate, and silicon is most common, cheap and stable performance semiconductor material, can effectively reduce cost and is promoted
Yield.In other embodiments, the material of the substrate 10 can also be silicon carbide, germanium or germanium silicon etc..In detail, at this
Substrate 10 described in embodiment is the first conduction type.In the present embodiment, first conduction type is p-type, therefore described
Substrate 10 is P-type semiconductor.In other embodiments, first conduction type may be N-type, therefore, the substrate 10
As N-type semiconductor.The P type substrate 10 can adulterate the elements such as boron, aluminium, indium by silicon and be formed, and be not limited thereto.More in detail
Carefully, the substrate 10 is the semiconductor being lightly doped.In the present embodiment, the P type substrate 10 is to adulterate the p-type of low concentration
The P- substrate 10 of impurity.
Further, the buried layer 11 is the second conduction type, and in the present embodiment, second conduction type is N-type, because
This described buried layer 11 is N-type semiconductor.In other embodiments, second conduction type may be p-type, therefore, described
Buried layer 11 is then P-type semiconductor.
Further, in the present embodiment, the epitaxial layer 20 is preferably silicon epitaxy layer.In detail, the epitaxial layer 20 is
Second conduction type.In the present embodiment, second conduction type is N-type, therefore the epitaxial layer 20 is N-type semiconductor.
In other embodiments, second conduction type may be p-type, and therefore, the epitaxial layer 20 is then P-type semiconductor.Institute
Stating N-type epitaxy layer 20 can be formed by elements such as silicon doping phosphorus, arsenic, antimony, be not limited thereto.In more detail, the extension
Layer 20 is the semiconductor being lightly doped.In the present embodiment, the N-type epitaxy layer 20 is outside the N- for the N-type impurity for adulterating low concentration
Prolong layer 20.The purpose being lightly doped is to guarantee that the epitaxial layer 20 has biggish resistance value so that it can bear biggish electricity
Pressure, to promote the breakdown voltage of the triode.
Further, in the present embodiment, the triode further includes through the epitaxial layer 20 and the buried layer 11
And the bottom isolated groove 21 that extends to the substrate 10 and the separation layer 22 in the isolated groove 21.The isolating trenches
Slot 21 is located in the secondth area B, and the isolated groove 21 is located at side of the well region 23 far from the firstth area A.?
In the present embodiment, the isolated groove 21 includes the first isolated groove 21a and the second isolated groove 21b, first isolating trenches
Both ends of the slot 21a and the second isolated groove 21b respectively close to the buried layer 11.The separation layer 22 is described including being filled in
The first separation layer 22a in first isolated groove 21a and the second separation layer 22b being filled in the second isolated groove 21b.
The separation layer 22 can be made of oxide, such as silica, can also be made of oxide and polysilicon.
Further, the well region 23 is the second conduction type, and in the present embodiment, second conduction type is N-type, because
This described well region 23 is N-type semiconductor.In other embodiments, second conduction type may be p-type, therefore, described
Well region 23 is then P-type semiconductor.In the present embodiment, the well region 23 is located at the side of the isolated groove 21.In this implementation
In example, the well region 23 includes that the first well region 23a and the second well region 23b, the first well region 23a is located at first isolating trenches
The side of slot 21a, the second well region 23b are located at the side of the second isolated groove 21b, and the first well region 23a and
The second well region 23b is located at simultaneously between the first isolated groove 21a and the second isolated groove 21b.
Further, the base area 40 is the first conduction type, and in the present embodiment, first conduction type is p-type, because
This described base area 40 is P-type semiconductor.In other embodiments, first conduction type may be N-type, therefore, described
Base area 40 is N-type semiconductor.It the p-type base area 40 can be by adulterating the elements shapes such as boron, aluminium, indium to the epitaxial layer 20
At being not limited thereto.The base area 40 is located at the side of the relatively described isolated groove 21 of the well region 23.In the present embodiment
In, the base area 40 is located at the side of the relatively described first isolated groove 21a of the first well region 23a and is located at second trap
The side of the relatively described second isolated groove 21b of area 23b, it will be understood that the base area 40 is located at the first well region 23a and institute
It states between the second well region 23b.
Further, the triode further include: the base contact area 81 in the base area 40.The base area connects
Touching area 81 is the first conduction type, and the doping concentration of the doping concentration base area 40 in the base contact area 81 is high, institute
Stating base contact area 81 can be effectively reduced the base contact resistance of triode.
Further, the emitter region 60 is the second conduction type, and in the present embodiment, second conduction type is N-type,
Therefore the emitter region 60 is N-type semiconductor.In other embodiments, second conduction type may be p-type, therefore,
The emitter region 60 is P-type semiconductor.
Further, the first medium layer 30 is located at the upper surface of the epitaxial layer 20, and the first medium layer 30 is same
When cover the separation layer 22 and the well region 23.The first medium layer 30 is preferably oxide layer.
Further, the emitter polysilicon layer 51 is located at the upper surface of the emitter region 60.The emitter-polysilicon
The group of layer 51 becomes the impurity that intrinsic polysilicon adulterates the second conduction type.In the present embodiment, the second conduction type is N-type,
Then the impurity of second conduction type is N-type impurity.In other embodiments, when second conduction type is p-type, then institute
The impurity for stating the second conduction type is p type impurity.It is highly preferred that the N-type impurity is arsenic ion.
Further, in the present embodiment, the oxide layer 70 is silicon dioxide layer.Outside the emitter polysilicon layer 51
Surface refers to upper surface and the both side surface of the emitter polysilicon layer 51.
Further, the base polysilicon floor 80 is located at the upper surface in the base contact area 81.The base polysilicon
The group of layer 80 becomes the impurity that intrinsic polysilicon adulterates the first conduction type.In the present embodiment, the first conduction type is p-type,
Then the impurity of first conduction type is p type impurity.In other embodiments, when first conduction type is N-type, then institute
The impurity for stating the first conduction type is N-type impurity.
Further, in the present embodiment, the second dielectric layer 90 is the phosphorosilicate glass (BPSG) of boracic.In other implementations
In example, the second dielectric layer 90 can be the phosphorosilicate glass (PSG) of not boracic, be also possible to undoped silica glass (USG),
It can also be depositing silica at low pressure (LPTEOS).
The foregoing is merely one embodiment of the present of invention, are not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent substitution, improvement and etc. done be should be included within the scope of the present invention.
Claims (10)
1. a kind of production method of triode characterized by comprising
S01: providing substrate, and the substrate includes the substrate of the first conduction type, is located in the substrate and at least partly exposes
In the buried layer of the second conduction type of the upper surface of the substrate and positioned at the second of the upper surface of the substrate and the buried layer
The epitaxial layer of conduction type；Secondth area in the firstth area and adjacent firstth area is provided on the substrate, in secondth area
It is inside formed through the epitaxial layer and extends to the well region of the second conduction type of the buried layer；
S02: in one dielectric layer of upper surface growth regulation of the epitaxial layer, the first medium layer is carried out through etching to be formed
The window in corresponding firstth area；
S03: the base of the first conduction type is doped and formed in the epitaxial layer to the epitaxial layer by the window
Area, the base area are located in firstth area；
S04: the doped polysilicon layer of the impurity of the second conduction type of doping is formed in the upper surface of the base area；Removal a part
The doped polysilicon layer keeps the upper surface of the base area locally exposed to form the emitter positioned at the upper surface of the base area
Polysilicon layer；
S05: carrying out heat under an oxygen-containing atmosphere and drive in, the impurity of second conduction type in the emitter polysilicon layer to
The base area spreads and forms emitter region in the base area, and the upper surface in the exposed base area and the transmitting simultaneously
The outer surface of pole polysilicon layer grows oxide layer；
S06: etching the oxide layer and only retains the part that the oxide layer is located at the outer surface of the emitter polysilicon layer；
S07: the base polysilicon layer of the impurity of the first conduction type of doping is formed in the upper surface of the base area；
S08: second dielectric layer is grown in the upper surface of the oxide layer, the base polysilicon layer and the first medium layer；
S09: the emitter formed through the second dielectric layer and the oxide layer and the corresponding emitter polysilicon layer connects
Contact hole, through the base stage contact hole of the second dielectric layer and the corresponding base polysilicon layer, run through the second dielectric layer
With the collector contact hole of the first medium layer and the corresponding well region；
S10: the emitter for connecting the emitter polysilicon layer, the base stage of the connection base polysilicon layer and connection institute are formed
State the collector of well region.
2. the production method of triode according to claim 1, which is characterized in that S01 further includes in secondth area
It is formed through the epitaxial layer and the buried layer and bottom extends to the isolated groove of the substrate, the isolated groove is located at institute
State side of the well region far from firstth area；Separation layer is grown in the isolated groove.
3. the production method of triode according to claim 1, which is characterized in that when second conduction type is N-type
When, the impurity of the second conduction type described in S04 is arsenic.
4. the production method of triode according to claim 1, which is characterized in that form the DOPOS doped polycrystalline silicon in S04
The step of layer includes: to grow the first intrinsically polysilicon layer being made of intrinsic polysilicon in the upper surface of the base area；Described
The impurity of the second conduction type is injected in first intrinsically polysilicon layer and forms the doped polysilicon layer.
5. the production method of triode according to claim 4, which is characterized in that the impurity of second conduction type
Implantation dosage is 1E16-3E16/cm2。
6. the production method of triode according to claim 1, which is characterized in that the temperature that heat described in S05 drives in is
950-1050℃。
7. the production method of triode according to claim 1, which is characterized in that S07 further include be heat-treated so that
The impurity of first conduction type in the base polysilicon layer spreads to the base area and is formed in the base area
Base contact area.
8. triode according to claim 1 characterized by comprising
Substrate, the substrate include the substrate of the first conduction type, in the substrate and are at least partly exposed to the lining
The buried layer of second conduction type of the upper surface at bottom and the second conduction type positioned at the upper surface of the substrate and the buried layer
Epitaxial layer；Secondth area in the firstth area and adjacent firstth area is provided on the substrate；
Positioned at secondth area, through the epitaxial layer and extend to the buried layer the second conduction type well region；
Positioned at firstth area and the base area of the first conduction type in the epitaxial layer；
The emitter region of the second conduction type in the base area；
First medium layer positioned at the upper surface of the epitaxial layer；
Window through the first medium layer and the corresponding base area；
In the window and the emitter polysilicon layer of the connection emitter region；
Oxide layer positioned at the outer surface of the emitter polysilicon layer；
In the window and the base polysilicon layer of the connection base area；
Second dielectric layer positioned at the oxide layer, the upper surface of the base polysilicon layer and the first medium layer；
Through the emitter of the second dielectric layer and the oxide layer and the connection emitter polysilicon layer, through described the
The base stage of second medium layer and the connection base polysilicon layer runs through the second dielectric layer and the first medium layer and connection
The collector contact hole of the well region.
9. triode according to claim 8, which is characterized in that further include:
Positioned at secondth area, through the epitaxial layer and the buried layer and bottom extends to the isolated groove of the substrate, institute
It states isolated groove and is located at side of the well region far from firstth area；
Separation layer in the isolated groove.
10. triode according to claim 8, which is characterized in that further include:
In the base area and the base contact area of the first conduction type of the connection base polysilicon floor.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112151603A (en) * | 2020-09-28 | 2020-12-29 | 上海华虹宏力半导体制造有限公司 | Triode and forming method thereof |
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| CN112151603A (en) * | 2020-09-28 | 2020-12-29 | 上海华虹宏力半导体制造有限公司 | Triode and forming method thereof |
| CN112151603B (en) * | 2020-09-28 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | Triode and forming method thereof |
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