CN112151603B - Triode and forming method thereof - Google Patents
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- CN112151603B CN112151603B CN202011039072.9A CN202011039072A CN112151603B CN 112151603 B CN112151603 B CN 112151603B CN 202011039072 A CN202011039072 A CN 202011039072A CN 112151603 B CN112151603 B CN 112151603B
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 164
- 239000002184 metal Substances 0.000 claims abstract description 164
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000012535 impurity Substances 0.000 claims description 141
- 238000000151 deposition Methods 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 238000009713 electroplating Methods 0.000 claims description 4
- 230000003321 amplification Effects 0.000 abstract description 3
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- -1 silicon dioxide Chemical compound 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
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Abstract
The application discloses a triode and a forming method thereof, wherein the triode comprises: a substrate in which a collector region, an emitter region, and a base region are formed; the dielectric layer is formed on the substrate, a first metal wire, a second metal wire and a third metal wire are formed in the dielectric layer, the bottom end of the first metal wire is connected with the collector region, the bottom end of the second metal wire is connected with the emitter region, and the bottom end of the third metal wire is connected with the base region; the feature size of the second metal wire is smaller than that of the first metal wire, the feature size of the second metal wire is smaller than that of the third metal wire, and the feature size of the second metal wire is smaller than 0.18 micrometers. The characteristic size of the metal wire connected with the emitting area in the triode is reduced to be below 0.18 microns, so that the emitting efficiency of the emitting area is increased, and the amplification factor of the triode is improved on the basis of not changing the structure of the triode.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a triode and a forming method thereof.
Background
With the development of semiconductor technology, the requirement on the integration level of the semiconductor is higher and higher, and the chip structure of the semiconductor is also more and more complex. Transistors are widely used in integrated circuits due to their device characteristics, and parasitic transistors are provided as required even in complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) circuits.
In the related art, in the layout of an integrated circuit, especially a CMOS integrated circuit, the performance of the CMOS needs to be considered preferentially, and the performance of the CMOS needs to be improved by taking up a certain space, so that it is difficult to have enough space to improve the electrical parameters of the transistor.
Disclosure of Invention
The application provides a triode and a forming method thereof, which can solve the problem that the beta value of the triode provided in the related art is lower because the triode is difficult to change the structure of the triode in enough space to improve the electrical parameters of the triode.
In one aspect, an embodiment of the present application provides a triode, including:
a substrate, wherein a collector region, an emitter region and a base region are formed in the substrate;
the dielectric layer is formed on the substrate, a first metal wire, a second metal wire and a third metal wire are formed in the dielectric layer, the bottom end of the first metal wire is connected with the collector region, the bottom end of the second metal wire is connected with the emitter region, and the bottom end of the third metal wire is connected with the base region;
the feature size (critical dimension, CD) of the second metal line is smaller than the feature size of the first metal line, the feature size of the second metal line is smaller than the feature size of the third metal line, and the feature size of the second metal line is smaller than 0.18 micrometers (mum).
Optionally, a deep well doping region is further formed in the substrate, and the emitter region and the base region are formed in the deep well doping region;
the substrate is doped with first type impurities, the deep well doped region is doped with second type impurities, the collector region and the emitter region are doped with the first type impurities, and the base region is doped with the second type impurities;
when the first type impurity is a P (positive) type impurity, the second type impurity is an N (negative) type impurity; when the first type impurity is an N-type impurity, the second type impurity is a P-type impurity.
Optionally, a well doping region and a deep well doping region are further formed in the substrate, the collector region and the emitter region are formed in the well doping region, and the well doping region and the base region are formed in the deep well doping region;
the substrate is doped with first type impurities, the deep well doped region is doped with second type impurities, the well doped region is doped with the first type impurities, the collector region is doped with the first type impurities, and the emitter region and the base region are doped with the second type impurities;
when the first type of impurity is a P-type impurity, the second type of impurity is an N-type impurity; when the first type impurity is an N-type impurity, the second type impurity is a P-type impurity.
Optionally, the first, second and third metal lines comprise tungsten (W).
Optionally, the first, second and third metal lines include aluminum (Al).
Optionally, the first, second and third metal lines include copper (Cu).
In another aspect, an embodiment of the present application provides a method for forming a triode, including:
forming a dielectric layer on a substrate, wherein a collector region, an emitter region and a base region are formed in the substrate;
etching the dielectric layer, and forming a first through hole, a second through hole and a third through hole in the dielectric layer, wherein the first through hole is formed on the collector region and exposes the collector region, the second through hole is formed on the emitter region and exposes the emitter region, the third through hole is formed on the base region and exposes the base region, the characteristic size of the second through hole is smaller than that of the first through hole, and the characteristic size of the second through hole is smaller than that of the third through hole;
forming a metal layer on the dielectric layer, wherein the metal layer fills the first through hole, the second through hole and the third through hole;
and carrying out planarization treatment on the metal layer, removing the metal layer in other areas except the first through hole, the second through hole and the third through hole, wherein the metal layer in the first through hole forms a first metal connecting wire, the metal layer in the second through hole forms a second metal connecting wire, the metal layer in the third through hole forms a third metal connecting wire, and the characteristic size of the second metal connecting wire is smaller than 0.18 micrometer.
Optionally, a deep well doping region is further formed in the substrate, and the emitter region and the base region are formed in the deep well doping region;
the substrate is doped with first type impurities, the deep well doped region is doped with second type impurities, the collector region and the emitter region are doped with the first type impurities, and the base region is doped with the second type impurities;
when the first type of impurity is a P-type impurity, the second type of impurity is an N-type impurity; when the first type impurity is an N-type impurity, the second type impurity is a P-type impurity.
Optionally, a well doping region and a deep well doping region are further formed in the substrate, the collector region and the emitter region are formed in the well doping region, and the well doping region and the base region are formed in the deep well doping region;
the substrate is doped with first type impurities, the deep well doped region is doped with second type impurities, the well doped region is doped with the first type impurities, the collector region is doped with the first type impurities, and the emitter region and the base region are doped with the second type impurities;
when the first type of impurity is a P-type impurity, the second type of impurity is an N-type impurity; when the first type impurity is an N-type impurity, the second type impurity is a P-type impurity.
Optionally, the forming a metal layer on the dielectric layer includes:
the metal layer is formed by depositing tungsten on the dielectric layer by a chemical vapor deposition (chemical vapor deposition, CVD) process.
Optionally, the forming a metal layer on the dielectric layer includes:
the metal layer is formed by depositing aluminum on the dielectric layer by a physical vapor deposition (physical vapor deposition, PVD) process.
Optionally, the forming a metal layer on the dielectric layer includes:
and growing copper on the dielectric layer through an electroplating process to form the metal layer.
Optionally, the planarizing the metal layer includes:
the planarization process is performed on the metal layer by a chemical mechanical polishing (chemical mechanical polishing, CMP) process.
The technical scheme of the application at least comprises the following advantages:
the characteristic size of the metal connecting wire connected with the emitting area in the triode is reduced to be below 0.18 microns, so that the emitting efficiency of the emitting area is increased, and the amplification factor of the triode is improved on the basis that the structure of the triode is not changed.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for forming a transistor according to an exemplary embodiment of the present application;
fig. 2 to 5 are schematic views illustrating formation of a transistor according to an exemplary embodiment of the present application;
fig. 3 to 9 are schematic views illustrating the formation of a transistor according to an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Referring to fig. 1, a flowchart of a method for forming a transistor according to an exemplary embodiment of the present application is shown; referring to fig. 2 to 5, schematic diagrams of transistor formation according to an exemplary embodiment of the present application are shown; referring to fig. 6 to 9, schematic diagrams of transistor formation according to another exemplary embodiment of the present application are shown.
As shown in fig. 1, the method comprises:
and 101, forming a dielectric layer on a substrate, wherein a collector region, an emitter region and a base region are formed in the substrate.
Referring to fig. 2 and 6, cross-sectional schematic views of forming a dielectric layer on a substrate are shown.
As shown in fig. 2, a collector region 101, an emitter region 102, and a base region 103 are formed in a substrate 110. Optionally, a deep well doped region 104 is also formed in the substrate 110, and the emitter region 102 and the base region 103 are formed in the deep well doped region 104. The substrate 110 is doped with a first type of impurity, the deep well doped region 104 is doped with a second type of impurity, the collector region 101 and the emitter region 102 are doped with the first type of impurity, and the base region 103 is doped with the second type of impurity. Illustratively, as shown in FIG. 2, the dielectric layer 120 may be formed by depositing silicon oxide on the substrate 110 by a CVD process.
As shown in fig. 6, a collector region 201, an emitter region 202, and a base region 203 are formed in a substrate 210. Optionally, a deep well doped region 104 is also formed in the substrate 110, and the emitter region 102 and the base region 103 are formed in the deep well doped region 104. The substrate 110 is doped with a first type of impurity, the deep well doped region 104 is doped with a second type of impurity, the collector region 101 and the emitter region 102 are doped with the first type of impurity, and the base region 103 is doped with the second type of impurity. Illustratively, as shown in FIG. 6, a dielectric layer 220 may be formed by depositing silicon oxide on a substrate 210 by a CVD process.
In the embodiment of the application, when the first type of impurity is a P-type impurity, the second type of impurity is an N-type impurity; when the first type of impurity is an N-type impurity, the second type of impurity is a P-type impurity.
Step 102, etching the dielectric layer, and forming a first through hole, a second through hole and a third through hole in the dielectric layer, wherein the first through hole is formed on the collector region and exposes the collector region, the second through hole is formed on the emitter region and exposes the emitter region, the third through hole is formed on the base region and exposes the base region, the feature size of the second through hole is smaller than that of the first through hole, and the feature size of the second through hole is smaller than that of the third through hole.
Referring to fig. 3 and 7, cross-sectional views of etching a dielectric layer to form a via are shown.
Illustratively, as shown in fig. 3, in step 102, "etching the dielectric layer to form the first via, the second via, and the third via in the dielectric layer" includes, but is not limited to: covering the photoresist on the dielectric layer 120 except for a first target area, wherein the first target area is an area corresponding to the first through hole 121, the second through hole 122 and the third through hole 123 through a photoetching process; etching is carried out to remove the dielectric layer 120 of the first target area, so that the collector region 101, the emitter region 102 and the base region 103 are exposed, and a first through hole 121, a second through hole 122 and a third through hole 123 are formed; and removing the photoresist. Wherein, the feature size of the second through hole 122 is smaller than that of the first through hole 121, and the feature size of the second through hole 122 is smaller than that of the third through hole 123.
Illustratively, as shown in fig. 7, in step 102, "etching the dielectric layer to form the first via, the second via, and the third via in the dielectric layer" includes, but is not limited to: covering the photoresist on the dielectric layer 220 except for a second target area, wherein the second target area is an area corresponding to the first through hole 221, the second through hole 222 and the third through hole 223 through a photoetching process; etching is carried out to remove the dielectric layer 220 of the second target area, so that the collector region 201, the emitter region 202 and the base region 203 are exposed, and a first through hole 221, a second through hole 222 and a third through hole 223 are formed; and removing the photoresist. Wherein, the feature size of the second through hole 222 is smaller than the feature size of the first through hole 221, and the feature size of the second through hole 222 is smaller than the feature size of the third through hole 223.
And 103, forming a metal layer on the dielectric layer, wherein the metal layer fills the first through hole, the second through hole and the third through hole.
Referring to fig. 4 and 8, cross-sectional schematic views of forming a metal layer on a dielectric layer are shown.
Illustratively, as shown in FIG. 4, the metal layer 130 may be formed on the dielectric layer 120 by any one of the following methods: depositing tungsten on the dielectric layer 120 by a CVD process to form a metal layer 130; or, depositing aluminum on the dielectric layer 120 by PVD process to form the metal layer 130; alternatively, the metal layer 130 is formed by growing copper on the dielectric layer 120 through an electroplating process.
Illustratively, as shown in FIG. 8, the metal layer 230 may be formed on the dielectric layer 220 by any one of the following methods: depositing tungsten on the dielectric layer 220 by a CVD process to form a metal layer 230; or, depositing aluminum on the dielectric layer 220 by PVD process to form a metal layer 230; alternatively, the metal layer 230 is formed by growing copper on the dielectric layer 220 through an electroplating process.
And 104, carrying out planarization treatment on the metal layer, removing the metal layer in other areas except the first through hole, the second through hole and the third through hole, wherein the metal layer in the first through hole forms a first metal connecting wire, the metal layer in the second through hole forms a second metal connecting wire, the metal layer in the third through hole forms a third metal connecting wire, and the characteristic size of the second metal connecting wire is smaller than 0.18 microns.
Referring to fig. 5 and 9, schematic cross-sectional views of a metal layer after planarization are shown.
For example, as shown in fig. 5, the metal layer 130 may be planarized by a CMP process, the metal layer 130 in other regions except the first through hole 121, the second through hole 122 and the third through hole 123 is removed, the remaining metal layer in the first through hole 121 forms the first metal wire 131, the metal layer in the second through hole 122 forms the second metal wire 132, and the metal layer in the third through hole 123 forms the third metal wire 133, wherein the feature size of the second metal wire 132 is smaller than the feature size of the first metal wire 131, the feature size of the second metal wire 132 is smaller than the feature size of the third metal wire 133, and the feature size of the second metal wire 132 is smaller than 0.18 μm.
For example, as shown in fig. 6, the metal layer 230 may be planarized by a CMP process, the metal layer 230 in other regions except the first via 221, the second via 222, and the third via 223 may be removed, the remaining metal layer in the first via 221 may form a first metal wire 231, the metal layer in the second via 222 may form a second metal wire 232, and the metal layer in the third via 223 may form a third metal wire 233, wherein a feature size of the second metal wire 232 is smaller than a feature size of the first metal wire 231, a feature size of the second metal wire 232 is smaller than a feature size of the third metal wire 233, and a feature size of the second metal wire 232 is smaller than 0.18 μm.
According to the formula(wherein Δp is the unbalanced carrier concentration, D p Is the hole diffusion coefficient, L p For the diffusion distance r 0 Radius of contact surface between metal wire and substrate), the contact surface between metal wire and substrate can be regarded as sphere, radial movement can cause carrier dispersion, resulting in concentration gradient, thus enhancing diffusion efficiency, especially when r 0 ＜＜L p When the diffusion current caused by the geometric shape is far more than that caused by the recombination, the dispersion of the carriers in the emitter region can be reduced by reducing the size of the metal wire connected with the emitter region, and therefore, the emission efficiency of the emitter region can be improved.
In summary, in the embodiment of the present application, the characteristic size of the metal wire connected to the emitter region in the triode is reduced to below 0.18 μm, so that the emission efficiency of the emitter region is increased, and the amplification factor of the triode is improved without changing the structure of the triode.
Referring to fig. 5, which is a schematic cross-sectional view of a transistor according to an exemplary embodiment of the present application, the transistor may be manufactured by the method of the embodiment of fig. 1, which includes:
a substrate 110 in which a collector region 101, an emitter region 102, a base region 103, and a deep well doping region 104 are formed, the emitter region 102 and the base region 103 being formed in the deep well doping region 104, the substrate 110 being doped with a first type of impurity, the deep well doping region 104 being doped with a second type of impurity, the collector region 101 and the emitter region 102 being doped with the first type of impurity, the base region being doped with the second type of impurity.
The dielectric layer 120 is formed on the substrate 110, in which a first metal wire 131, a second metal wire 132 and a third metal wire 133 are formed, wherein a bottom end of the first metal wire 131 is connected to the collector region 101, a bottom end of the second metal wire 132 is connected to the emitter region 102, and a bottom end of the third metal wire 133 is connected to the base region 103. Optionally, dielectric layer 120 includes silicon oxide (e.g., silicon dioxide, siO 2 ) The method comprises the steps of carrying out a first treatment on the surface of the Optionally, the first metal wire 131, the second metal wire 132 and the third metal wire 133 include tungsten; or, the first metal wire 131, the second metal wire 132, and the third metal wire 133 include aluminum; or, the first metal wire 131, the second metal wire 132, and the third metal wire 133 include copper.
The feature size of the second metal line 132 is smaller than that of the first metal line 131, the feature size of the second metal line 132 is smaller than that of the third metal line 133, and the feature size of the second metal line is smaller than 0.18 μm.
In the embodiment of the application, when the first type of impurity is a P-type impurity, the second type of impurity is an N-type impurity; when the first type of impurity is an N-type impurity, the second type of impurity is a P-type impurity.
Referring to fig. 9, which is a schematic cross-sectional view of a transistor according to an exemplary embodiment of the present application, the transistor may be manufactured by the method of the embodiment of fig. 1, which includes:
a substrate 210, in which a collector region 201, an emitter region 202, a base region 203, a deep well doped region 204, and a well doped region 205 are formed, the collector region 201 and the emitter region 202 are formed in the well doped region 205, the well doped region 205 and the base region 203 are formed in the deep well doped region 204, the substrate 210 is doped with a first type of impurity, the deep well doped region 204 is doped with a second type of impurity, the well doped region 205 is doped with the first type of impurity, the collector region 201 is doped with the first type of impurity, and the emitter region 202 and the base region 203 are doped with the second type of impurity.
The dielectric layer 220 is formed on the substrate 210, in which a first metal wire 231, a second metal wire 232 and a third metal wire 233 are formed, the bottom end of the first metal wire 231 is connected with the collector region 201, the bottom end of the second metal wire 232 is connected with the emitter region 202, and the bottom end of the third metal wire 233 is connected with the base region 203. Optionally, the dielectric layer 220 includes silicon oxide (e.g., silicon dioxide 2; optionally, the first, second, and third metal lines 231, 232, and 233 include tungsten; or the first, second, and third metal lines 231, 232, and 233 include aluminum; or the first, second, and third metal lines 231, 232, and 233 include copper).
The feature size of the second metal line 232 is smaller than that of the first metal line 231, the feature size of the second metal line 232 is smaller than that of the third metal line 233, and the feature size of the second metal line is smaller than 0.18 μm.
In the embodiment of the application, when the first type of impurity is a P-type impurity, the second type of impurity is an N-type impurity; when the first type of impurity is an N-type impurity, the second type of impurity is a P-type impurity.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (13)
1. A transistor, comprising:
a substrate, wherein a collector region, an emitter region and a base region are formed in the substrate;
the dielectric layer is formed on the substrate, a first metal wire, a second metal wire and a third metal wire are formed in the dielectric layer, the bottom end of the first metal wire is connected with the collector region, the bottom end of the second metal wire is connected with the emitter region, and the bottom end of the third metal wire is connected with the base region;
the characteristic dimension of the second metal wire is smaller than that of the first metal wire, the characteristic dimension of the second metal wire is smaller than that of the third metal wire, and the characteristic dimension of the second metal wire is smaller than 0.18 micrometers.
2. The transistor of claim 1, wherein a deep well doped region is further formed in the substrate, the emitter region and the base region being formed in the deep well doped region;
the substrate is doped with first type impurities, the deep well doped region is doped with second type impurities, the collector region and the emitter region are doped with the first type impurities, and the base region is doped with the second type impurities;
when the first type of impurity is a P-type impurity, the second type of impurity is an N-type impurity; when the first type impurity is an N-type impurity, the second type impurity is a P-type impurity.
3. The transistor of claim 1, wherein the substrate further has a well doped region and a deep well doped region formed therein, the collector region and the emitter region being formed in the well doped region, the well doped region and the base region being formed in the deep well doped region;
the substrate is doped with first type impurities, the deep well doped region is doped with second type impurities, the well doped region is doped with the first type impurities, the collector region is doped with the first type impurities, and the emitter region and the base region are doped with the second type impurities;
when the first type of impurity is a P-type impurity, the second type of impurity is an N-type impurity; when the first type impurity is an N-type impurity, the second type impurity is a P-type impurity.
4. A transistor according to any of claims 1 to 3, wherein the first, second and third metal lines comprise tungsten.
5. A transistor according to any one of claims 1 to 3, wherein the first, second and third metal lines comprise aluminum.
6. A transistor according to any of claims 1 to 3, wherein the first, second and third metal lines comprise copper.
7. A method of forming a transistor, comprising:
forming a dielectric layer on a substrate, wherein a collector region, an emitter region and a base region are formed in the substrate;
etching the dielectric layer, and forming a first through hole, a second through hole and a third through hole in the dielectric layer, wherein the first through hole is formed on the collector region and exposes the collector region, the second through hole is formed on the emitter region and exposes the emitter region, the third through hole is formed on the base region and exposes the base region, the characteristic size of the second through hole is smaller than that of the first through hole, and the characteristic size of the second through hole is smaller than that of the third through hole;
forming a metal layer on the dielectric layer, wherein the metal layer fills the first through hole, the second through hole and the third through hole;
and carrying out planarization treatment on the metal layer, removing the metal layer in other areas except the first through hole, the second through hole and the third through hole, wherein the metal layer in the first through hole forms a first metal connecting wire, the metal layer in the second through hole forms a second metal connecting wire, the metal layer in the third through hole forms a third metal connecting wire, and the characteristic size of the second metal connecting wire is smaller than 0.18 micrometer.
8. The method of claim 7, wherein the substrate further has a deep well doped region formed therein, the emitter region and the base region being formed in the deep well doped region;
the substrate is doped with first type impurities, the deep well doped region is doped with second type impurities, the collector region and the emitter region are doped with the first type impurities, and the base region is doped with the second type impurities;
when the first type of impurity is a P-type impurity, the second type of impurity is an N-type impurity; when the first type impurity is an N-type impurity, the second type impurity is a P-type impurity.
9. The method of claim 7, wherein the substrate further has a well doped region and a deep well doped region formed therein, the collector region and the emitter region being formed therein, the well doped region and the base region being formed therein;
the substrate is doped with first type impurities, the deep well doped region is doped with second type impurities, the well doped region is doped with the first type impurities, the collector region is doped with the first type impurities, and the emitter region and the base region are doped with the second type impurities;
when the first type of impurity is a P-type impurity, the second type of impurity is an N-type impurity; when the first type impurity is an N-type impurity, the second type impurity is a P-type impurity.
10. The method of any of claims 7 to 9, wherein forming a metal layer on the dielectric layer comprises:
and depositing tungsten on the dielectric layer through a CVD process to form the metal layer.
11. The method of any of claims 7 to 9, wherein forming a metal layer on the dielectric layer comprises:
and depositing aluminum on the dielectric layer through a PVD process to form the metal layer.
12. The method of any of claims 7 to 9, wherein forming a metal layer on the dielectric layer comprises:
and growing copper on the dielectric layer through an electroplating process to form the metal layer.
13. The method according to any one of claims 7 to 9, wherein the planarizing the metal layer comprises:
and carrying out planarization treatment on the metal layer through a CMP process.
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