CN111540711A - Method for manufacturing unidirectional negative resistance ESD protection device and unidirectional negative resistance ESD protection device - Google Patents
Method for manufacturing unidirectional negative resistance ESD protection device and unidirectional negative resistance ESD protection device Download PDFInfo
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Abstract
The invention provides a method for manufacturing a unidirectional negative resistance ESD protection device and the unidirectional negative resistance ESD protection device, wherein the method comprises the following steps: epitaxially growing an epitaxial layer on the front surface of the substrate; forming a first well region in the epitaxial layer, wherein the first well region is in contact with the front surface of the substrate, and carrying out high-temperature annealing on the first well region; forming other areas outside the first well region in the epitaxial layer, synchronously forming a second well region and a third well region, and carrying out high-temperature annealing on the second well region and the third well region; forming a first doped region in the first well region; forming a second doped region in the second well region, forming a third doped region in the third well region, and performing high-temperature annealing on the second doped region and the third doped region; forming a contact hole on the interlayer dielectric layer formed on the surfaces of the annealed epitaxial layer, the first doped region, the second doped region and the third doped region; sputtering metal on the contact hole to form a first electrode and a second electrode above the contact hole; and forming a third electrode on the back surface of the substrate. The surge protection capability can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a unidirectional negative resistance electrostatic Discharge (ESD) protection device and the unidirectional negative resistance ESD protection device.
Background
With the rapid development of electronic products, ESD protection devices are widely used in electronic products to overcome the static electricity generated during the manufacturing, packaging, testing, transportation and use of electronic products. Statistically, among the functional failures of Integrated Circuits (ICs) of electronic products, the failure of the ESD protection device due to the electrostatic surge is one of the important factors. Taking a battery module of a consumer electronic product as an example, the battery module is impacted by a large surge current during the insertion and extraction process, so the ESD Protection device in the battery module needs to be capable of adapting to surge Protection of different voltages at a power supply Voltage (VBAT) end and a USB Voltage (VBUS) end, for example, the Voltage at the VBAT end is generally 4.5V, the VBUS end Voltage is matched with an Over Voltage Protection (OVP) scheme, and the Voltage varies from 7V to 30V. Particularly, with the increase of the demand for high-speed fast charging, the operating voltage of the electronic product is gradually switched from the conventional 7V and 12V to 18V, 22V, 24V or even higher voltage, so that the ESD protection device not only needs to bypass the large surge in the breakdown direction and the forward conduction direction to the ground, but also needs to ensure that the rear-stage IC is not impacted by the surge due to the surge residual voltage of the ESD protection device, so that how to design the ESD protection device with smaller and thinner cost and meeting different actual surge requirements in the circuit by packaging the surge capability becomes a technical problem to be solved urgently.
The existing ESD protection device generally adopts a unidirectional negative resistance ESD protection device, fig. 1 is a schematic structural diagram of the unidirectional negative resistance ESD protection device, and as shown in fig. 1, an N + region is formed on a P substrate single crystal through double-sided lithography, so as to form a vertical base region-opened bipolar transistor; and a P + region is formed on the back surface, a back metal is formed to be in short circuit with the N + region, and an equivalent circuit of the device is that a base-opened region bipolar transistor and a diode are connected in parallel to form a unidirectional negative resistance ESD protection device. However, the unidirectional negative resistance ESD protection device needs to perform double-sided lithography, and has the problem of alignment accuracy between front-side lithography and back-side lithography, so that surge current and residual voltage between batches are inconsistent, the surge protection capability is not high, the requirement of high-voltage surge protection cannot be met, and the surge protection requirement of consumer products is difficult to meet.
Disclosure of Invention
In view of the above, the present invention provides a method for manufacturing a unidirectional negative resistance ESD protection device and a unidirectional negative resistance ESD protection device, so as to improve surge protection capability.
In a first aspect, an embodiment of the present invention provides a method for manufacturing a unidirectional negative resistance ESD protection device, including:
epitaxially growing an epitaxial layer on the front surface of the substrate;
forming a first well region in the epitaxial layer, wherein the first well region is in contact with the front surface of the substrate, and carrying out high-temperature annealing on the first well region;
forming other areas outside the first well region in the epitaxial layer, synchronously forming a second well region and a third well region, and carrying out high-temperature annealing on the second well region and the third well region;
forming a first doped region in the first well region;
forming a second doped region in the second well region, forming a third doped region in the third well region, and performing high-temperature annealing on the second doped region and the third doped region;
forming a contact hole on the interlayer dielectric layer formed on the surfaces of the annealed epitaxial layer, the first doped region, the second doped region and the third doped region;
sputtering metal on the contact hole to form a first electrode and a second electrode above the contact hole respectively;
and forming a third electrode on the back surface of the substrate.
With reference to the first aspect, an embodiment of the present invention provides a first possible implementation manner of the first aspect, where doping types of the substrate, the epitaxial layer, the first well region, the second well region, the third well region, and the first doping region are a first doping type; the doping types of the second doping area and the third doping area are a second doping type opposite to the first doping type.
With reference to the first possible implementation manner of the first aspect, an embodiment of the present invention provides a second possible implementation manner of the first aspect, where the first doping type is an N type, and the second doping type is a P type; or the first doping type is P type, and the second doping type is N type.
With reference to the first aspect, the first possible implementation manner of the first aspect, or the second possible implementation manner, an embodiment of the present invention provides a third possible implementation manner of the first aspect, wherein a doping concentration of the first well region is greater than a doping concentration of the epitaxial layer; the doping concentration of the second well region is the same as that of the third well region; the doping concentration of the second doping area is the same as that of the third doping area; the doping concentration of the first doping region is greater than that of the first well region.
In a second aspect, an embodiment of the present invention further provides a unidirectional negative resistance ESD protection device, including: a substrate, an epitaxial layer, a first well region, a second well region, a third well region, a first doped region, a second doped region, a third doped region, a first electrode, a second electrode, a third electrode,
the epitaxial layer is positioned above the front surface of the substrate;
the first well region is positioned in the epitaxial layer and connected with the substrate;
the second well region and the third well region are positioned in the epitaxial layer, and the first well region, the second well region and the third well region are arranged at intervals;
the first doped region is positioned in the first well region, the second doped region is positioned in the second well region, and the third doped region is positioned in the third well region;
the first electrode is positioned above the contact hole of the second doping region, the second electrode is positioned above the contact holes from the first doping region to the contact hole of the third doping region, and the contact hole of the first doping region, the contact hole of the second doping region and the contact hole of the third doping region are respectively formed on an interlayer dielectric layer formed on the surfaces of the annealed epitaxial layer, the first doping region, the second doping region and the third doping region through process treatment;
the third electrode is located on the back surface of the substrate.
With reference to the second aspect, an embodiment of the present invention provides a first possible implementation manner of the second aspect, where the second doping region forms an emitter region of a lateral open base region NPN transistor, the first well region, the epitaxial layer, and the second well region form a base region of the lateral open base region NPN transistor, the third doping region forms a collector region of the lateral open base region NPN transistor, and the unidirectional negative resistance ESD protection device is obtained by plastic-packaging the open base region NPN transistor.
With reference to the second aspect or the first possible implementation manner of the second aspect, an embodiment of the present invention provides a second possible implementation manner of the second aspect, where the unidirectional negative resistance ESD protection device further includes:
and the interlayer dielectric layer is positioned on the surfaces of the epitaxial layer, the first doped region, the second doped region and the third doped region.
With reference to the second aspect or the first possible implementation manner of the second aspect, an embodiment of the present invention provides a third possible implementation manner of the second aspect, where the unidirectional negative resistance ESD protection device further includes: a fourth well region and a fifth well region, wherein,
the fourth well region is positioned between the second doped region and the first well region, and the fifth well region is positioned between the third doped region and the third well region;
the doping concentration of the fourth well region is lower than that of the second doping region, and the doping concentration of the fifth well region is lower than that of the third doping region.
According to the method for manufacturing the unidirectional negative resistance ESD protection device and the unidirectional negative resistance ESD protection device, an epitaxial layer is epitaxially grown on the front surface of a substrate; forming a first well region in the epitaxial layer, wherein the first well region is in contact with the front surface of the substrate, and carrying out high-temperature annealing on the first well region; forming other areas outside the first well region in the epitaxial layer, synchronously forming a second well region and a third well region, and carrying out high-temperature annealing on the second well region and the third well region; forming a first doped region in the first well region; forming a second doped region in the second well region, forming a third doped region in the third well region, and performing high-temperature annealing on the second doped region and the third doped region; forming a contact hole on the interlayer dielectric layer formed on the surfaces of the annealed epitaxial layer, the first doped region, the second doped region and the third doped region; sputtering metal on the contact hole to form a first electrode and a second electrode above the contact hole respectively; and forming a third electrode on the back surface of the substrate. Therefore, an emitter region-base region PN junction is formed by the first doping region and the first well region, a collector region-base region PN junction is formed by the second doping region and the second well region, and the two PN junctions are matched by doping concentration, so that bidirectional low-voltage ESD protection can be realized in a punch-through breakdown mode, bidirectional high-voltage ESD protection can be realized in an avalanche breakdown mode, and the surge protection capability of the unidirectional negative resistance ESD protection device is effectively improved.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 shows a schematic diagram of a prior art unidirectional negative resistance ESD protection device;
FIG. 2a is a schematic diagram of a unidirectional negative resistance ESD protection device according to an embodiment of the present invention;
FIG. 2b is a schematic diagram of a unidirectional negative resistance ESD protection device according to another embodiment of the present invention;
FIG. 3 is a flow chart illustrating a method for fabricating a unidirectional negative resistance ESD protection device according to an embodiment of the present invention;
FIG. 4a is a schematic diagram of the structure obtained from the step 302;
FIG. 4b is a schematic diagram of the structure obtained from the step 303;
FIG. 4c is a schematic diagram of the structure obtained from the step 304;
FIG. 4d is a schematic diagram of the structure obtained from the step 305 according to the embodiment of the present invention;
FIG. 4e is a schematic diagram of the structure obtained from the step 307;
fig. 4f shows a schematic structural diagram obtained by processing in step 308 according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Embodiments of the present invention provide a method for manufacturing a unidirectional negative resistance ESD protection device and a unidirectional negative resistance ESD protection device, which are described below with reference to embodiments.
Fig. 2a shows a schematic structural diagram of a unidirectional negative resistance ESD protection device provided by an embodiment of the present invention. As shown in fig. 2a, the unidirectional negative resistance ESD protection device comprises: substrate 100, epitaxial layer 101, first well region 102, second well region 103, third well region 104, first doped region 105, second doped region 106, third doped region 107, first electrode 108, second electrode 109, third electrode 110, wherein,
the first well region 102 is positioned in the epitaxial layer 101 and connected with the substrate;
the second well region 103 and the third well region 104 are located in the epitaxial layer 101, and the first well region 102, the second well region 103 and the third well region 104 are arranged alternately;
the first doped region 105 is located in the first well region 102, the second doped region 106 is located in the second well region 103, and the third doped region 107 is located in the third well region 104;
the first electrode 108 is positioned above the second doping region contact hole, the second electrode 109 is positioned above the first doping region contact hole and the third doping region contact hole, and the first doping region contact hole, the second doping region contact hole and the third doping region contact hole are respectively formed on interlayer dielectric layers formed on the surfaces of the annealed epitaxial layer 101, the first doping region 105, the second doping region 106 and the third doping region 107 through process treatment;
the third electrode 110 is located on the back surface of the substrate 100.
In the embodiment of the present invention, as an optional embodiment, the doping types of the substrate 100, the epitaxial layer 101, the first well region 102, the second well region 103, the third well region 104, and the first doping region 105 are a first doping type;
the doping types of the second doping region 106 and the third doping region 107 are a second doping type opposite to the first doping type;
the doping concentration of the first well region 102 is greater than that of the epitaxial layer 101;
the doping concentration of the second well region 103 is the same as that of the third well region 104;
the doping concentration of the second doped region 106 is the same as the doping concentration of the third doped region 107;
the doping concentration of the first doping region 105 is greater than the doping concentration of the first well region 102.
In the embodiment of the present invention, as an optional embodiment, the first doping type is an N type, and the second doping type is a P type; as another alternative, the first doping type is P-type and the second doping type is N-type. In the following description, the doping type of the substrate 100 is exemplified as P-type doping.
In the embodiment of the present invention, as an optional embodiment, the substrate 100 is heavily doped, the epitaxial layer 101 is lightly doped, the first well region 102, the second well region 103, and the third well region 104 are lightly doped, and the first doped region 105, the second doped region 106, and the third doped region 107 are heavily doped.
In the embodiment of the invention, the second doping region 106 forms an emitter region of a lateral base region-opened NPN transistor, the first well region 102, the epitaxial layer 101, and the second well region 103 form a base region of the lateral base region-opened NPN transistor, the third doping region 107 forms a collector region of the lateral base region-opened NPN transistor, and the unidirectional negative resistance ESD protection device is obtained by plastic-packaging the base region-opened NPN transistor.
In the embodiment of the invention, the doping concentration matching of the emitter region-base region and the collector region-base region is set by utilizing the characteristic of the lateral base region-opened NPN transistor, namely, the first doping region 104 and the first well region 102 are utilized to form an emitter region-base region PN junction, the second doping region 105 and the second well region 103 are utilized to form a collector region-base region PN junction, and the two PN junctions (the doping region-well region and the collector region-well region) are matched by utilizing the doping concentration, so that the bidirectional low-voltage ESD protection can be realized by a punch-through breakdown mode, and the bidirectional high-voltage ESD protection can be realized by an avalanche breakdown mode.
In the embodiment of the present invention, when the ESD pulse or surge received by the first electrode 108 is positive (the potential of the first electrode 108 is positive, the potential of the third electrode 110 is negative, and the first electrode 108 and the third electrode 110 form a reverse breakdown direction of the unidirectional negative resistance electrostatic discharge protection device), the forward ESD pulse or surge flows through the laterally open base region NPN transistor, wherein,
the direction from the second electrode 109, the first doped region 105, the first well region 102 to the substrate 100 forms a breakdown voltage direction of the unidirectional negative resistance ESD protection device, the breakdown voltage direction is a negative resistance characteristic direction of the unidirectional negative resistance ESD protection device, namely a first branch of reverse static and surge discharge, and the direction from the substrate 100, the first well region 102, the first doped region 105 to the second electrode 109 forms a second branch of forward static and surge discharge;
the substrate 100, the epitaxial layer 101, the second well region 103 and the second doped region 106 form a forward characteristic direction of the unidirectional negative resistance ESD protection device, that is, a first branch of forward static and surge discharge, and the second doped region 106, the second well region 103, the epitaxial layer 101 and the substrate 100 form a second branch of reverse static and surge discharge.
When the ESD pulse or surge received by the first electrode 108 is negative (the potential of the first electrode 108 is negative, and the potential of the third electrode 110 is positive), a forward diode is formed between the third electrode 110 and the first electrode 108, and a forward conduction direction is formed, that is: the substrate 100, the epitaxial layer 101, the direction from the second well region 103 to the second doped region 106 form a positive characteristic direction of a positive conduction (positive static electricity) direction of the unidirectional negative resistance ESD protection device and a first branch circuit for discharging negative ESD and surge; the substrate 100, the first well region 102, the first doped region 105 and the second electrode 109 form a second branch for discharging negative ESD and surge in the positive electrostatic direction.
In this embodiment of the present invention, as an optional embodiment, the unidirectional negative resistance ESD protection device further includes:
an interlayer dielectric layer (not shown) is formed on the surfaces of the epitaxial layer 101, the first doped region 105, the second doped region 106 and the third doped region 107.
In the embodiment of the present invention, the interlayer dielectric layer is a silicon dioxide layer formed on the surfaces of the epitaxial layer 101, the first doped region 105, the second doped region 106 and the third doped region 107 after annealing, or is an SI layer formed on the surface of the silicon dioxide layer by a Chemical Vapor Deposition (CVD) process3N4And (3) a layer.
Fig. 2b is a schematic diagram illustrating a structure of a unidirectional negative resistance ESD protection device according to another embodiment of the present invention. As shown in fig. 2b, compared to fig. 2a, the method further includes: a fourth well region 211, and a fifth well region 212, wherein,
the fourth well region 211 is located between the second doped region 106 and the first well region 102, and the fifth well region 212 is located between the third doped region 107 and the third well region 104;
the doping concentration of the fourth well region 211 is lower than that of the second doping region 106, and the doping concentration of the fifth well region 212 is lower than that of the third doping region 107.
In this embodiment, as an optional embodiment, the doping types of the fourth well region 211 and the fifth well region are both N-type doping, and the doping concentration is light doping.
In the embodiment of the present invention, by adding the fourth well region 211 and the fifth well region 212, the second doping region 106 and the fourth well region 211 form an emitter region of the lateral open base region NPN transistor, the second well region 103, the epitaxial layer 101, and the third well region 104 form a base region of the lateral open base region NPN transistor, and the fifth well region 212 and the third doping region 107 form a collector region of the lateral open base region NPN transistor. Because the emitter region and the base region are added with the fourth well region 211, the collector region and the base region are added with the fifth well region 212, and the doping concentrations of the fourth well region 211 and the fifth well region 212 are low, the junction depletion regions of the emitter region-base region and the collector region-base region cannot be widened to the second doping region 106 and the third doping region 107, reverse breakdown occurs in vivo, and the breakdown mechanism is avalanche breakdown, so that the withstand voltage of the ESD protection device of the embodiment is larger than that of the unidirectional negative resistance ESD protection device shown in fig. 2a, when the first electrode 108 receives forward ESD and surge, higher reverse breakdown voltage can be borne, and the ESD protection device can be applied to ESD and surge protection in a circuit with higher working voltage.
In the embodiment of the present invention, the second electrode 109 is attached to the substrate 100; the substrate 100, the epitaxial layer 101 to the first doping area 105 form an ESD and surge discharge channel, a one-way negative resistance function can be realized, double-sided lithography precision registration errors can be effectively avoided, the surge capacity uniformity is improved, large surge capacity and low residual voltage are realized, when a rechargeable IC chip is protected, an OVP device is matched, the ultralow effect of positive surge clamping voltage and negative surge clamping voltage can be achieved, a good protection effect is provided for various rear-end IC chips, and the electrostatic and surge protection device can be widely applied to electrostatic and surge protection of interfaces such as consumer electronics, automotive electronics and industrial control.
Fig. 3 is a flow chart illustrating a method for manufacturing a unidirectional negative resistance ESD protection device according to an embodiment of the present invention. As shown in fig. 3, the method includes:
in the embodiment of the present invention, as an optional embodiment, the doping type of the substrate 100 is P-type doping. The range of resistivity of the substrate 100 includes, but is not limited to: 0.1-0.001 omega cm. In some preferred embodiments, the substrate 100 is selected to have a low resistivity, for example, the substrate 100 is selected to have a resistivity of 0.004-0.008 Ω · cm, and in still other preferred embodiments, the substrate 100 is selected to have a resistivity of less than 0.006 Ω · cm, and the lower resistivity is effective to reduce the dynamic resistance of the ESD protection device.
In the embodiment of the present invention, as an alternative embodiment, the substrate 100 is a P-type substrate sheet, and the epitaxial layer 101 is grown on the P-type substrate sheet at a high temperature by using an epitaxial furnace. The epitaxial layer 101 is a P-type epitaxial layer, has a resistivity in the range of 0.01-10 Ω · cm, and has a thickness of 5-15 μm.
fig. 4a shows a schematic structural diagram obtained by the processing of step 302 according to the embodiment of the present invention. As shown in fig. 4a, in the embodiment of the present invention, the first well region 102 is formed in the epitaxial layer 101 by a process including, but not limited to: and photoetching and etching. The first well region 102 is formed in the epitaxial layer 101 by conventional processes such as photolithography and etching, the doping type of the first well region 102 is P-type, and the doping impurities include, but are not limited to, boron. Taking boron as an example of a doping impurity, the ion implantation dosage of (boron) is 1E14/cm2-1E15/cm2The implantation energy is 50-120 KeV.
In this embodiment of the present invention, as an alternative embodiment, the first well region 102 is located on one side, for example, the left side or the right side, of the epitaxial layer 101. After the first well region 102 is formed, a high temperature anneal is performed on the first well region 102. As an alternative embodiment, the annealing temperature is 1100-1200 ℃, and the annealing time is 1.0-3.0 h.
fig. 4b shows a schematic structural diagram obtained by processing in step 303 according to the embodiment of the present invention. As shown in fig. 4b, in the embodiment of the present invention, the second well region 103 and the third well region 104 are formed simultaneously in the epitaxial layer 101 by performing photolithography and etching on other regions outside the first well region 102, and the doping types of the second well region 103 and the third well region 104 are P-type. As an alternative embodiment, the dopant impurity may be boron and the ion implantation dose is 1E13/cm2-1E15/cm2The implantation energy is 50-120 Kev.
In the embodiment of the invention, after the second well region 103 and the third well region 104 are formed, high temperature annealing is performed on the second well region 103 and the third well region. As an alternative embodiment, the annealing temperature is 1000-1100 ℃, and the annealing time is 0.5-2 h.
fig. 4c shows a schematic structural diagram obtained by processing in step 304 according to the embodiment of the present invention. As shown in fig. 4c, in the embodiment of the invention, the first doped region 105 is formed in the first well region 102 by conventional processes such as photolithography and etching, the doping type of the first doped region 105 is P-type, the doping impurity may be boron, and the ion implantation dosage is 1E15/cm2-8e15/cm2The implantation energy is 40-80 KeV.
fig. 4d shows a schematic structural diagram obtained by processing in step 305 according to the embodiment of the present invention. As shown in fig. 4d, in the embodiment of the invention, the second doped region 106 and the third doped region 107 are formed in the second well region 103 and the third well region 104 respectively by conventional processes such as photolithography and etching, the doping types of the second doped region 106 and the third doped region 107 are both N-type, the doping may be phosphorus, and the ion implantation dosage is 1E15/cm2-1E16/cm2The implantation capacity is 40-80 KeV.
In the embodiment of the present invention, after the second doped region 106 and the third doped region 107 are formed, a high temperature annealing process is performed on the second doped region 106 and the third doped region 107. As an alternative embodiment, the annealing temperature is 950-1050 ℃, and the annealing time is 0.5-1 h.
In the embodiment of the present invention, as an optional embodiment, the doping types of the substrate 100, the epitaxial layer 101, the first well region 102, the second well region 103, the third well region 104, and the first doping region 105 are a first doping type; the doping type of the second doping region 106 and the third doping region 107 is a second doping type opposite to the first doping type.
In the embodiment of the present invention, as an optional embodiment, the first doping type is an N type, and the second doping type is a P type; or the first doping type is P type, and the second doping type is N type.
In the embodiment of the present invention, the doping concentration of the first well region 102 is greater than the doping concentration of the epitaxial layer 101; the doping concentration of the second well region 103 is the same as that of the third well region 104; the doping concentration of the second doped region 106 is the same as the doping concentration of the third doped region 107; the doping concentration of the first doping region 105 is greater than the doping concentration of the first well region 102.
In the embodiment of the present invention, as an optional embodiment, the substrate 100 is heavily doped, the epitaxial layer 101 is lightly doped, the first well region 102, the second well region 103, and the third well region 104 are lightly doped, and the first doped region 105, the second doped region 106, and the third doped region 107 are heavily doped.
In the embodiment of the invention, the second doping region 106 forms an emitter region of a lateral base region-opened NPN transistor, the first well region 102, the epitaxial layer 101, and the second well region 103 form a base region of the lateral base region-opened NPN transistor, the third doping region 107 forms a collector region of the lateral base region-opened NPN transistor, and the base region-opened NPN transistor is plastically packaged subsequently to obtain the unidirectional negative resistance ESD protection device.
in the embodiment of the invention, the interlayer dielectric layer (not shown) is a silicon dioxide layer formed after annealing, or SI formed by a Chemical Vapor Deposition (CVD) process on the surface of the silicon dioxide layer3N4And (3) a layer.
In the embodiment of the present invention, a contact hole (not shown in the figure) is formed on the interlayer dielectric layer by conventional processes such as photolithography and etching, and the contact hole includes: the first doping region contact hole, the second doping region contact hole and the third doping region contact hole.
fig. 4e shows a schematic structural diagram obtained by processing in step 307 according to the embodiment of the present invention. As shown in fig. 4e, in the embodiment of the present invention, an aluminum layer with a thickness of 2-5um is formed by an evaporation or sputtering process, and conventional processes such as photolithography and etching are performed on the aluminum layer formed on the surface, so that the first electrode 108 is formed on the metal above the contact hole of the second doped region; a common second electrode 109 is formed over the third doped region contact and the metal over the first doped region contact.
In the embodiment of the invention, interlayer dielectric layers are formed on the surfaces of the epitaxial layer 101, the first doped region 105, the second doped region 106 and the third doped region 107; photoetching and etching the interlayer dielectric layer to form contact holes comprising a first doping area contact hole, a second doping area contact hole and a third doping area contact hole; metal (aluminum) is sputtered at the contact holes to form a first electrode 108 over the second doped region contact holes, and a common second electrode 109 is formed over the first doped region contact holes and the third doped region contact holes.
In step 308, a third electrode 110 is formed on the back side of the substrate 100.
Fig. 4f shows a schematic structural diagram obtained by processing in step 308 according to the embodiment of the present invention. In the embodiment of the present invention, as shown in fig. 4f, after performing lapping and silicon etching on the back surface of the substrate 100, a metallization process, such as evaporating metal, is performed, so that the metal under the back surface of the substrate 100 forms the third electrode 110.
It is noted that, in the embodiments of the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (8)
1. A method of fabricating a unidirectional negative resistance electrostatic discharge (ESD) protection device, comprising:
epitaxially growing an epitaxial layer on the front surface of the substrate;
forming a first well region in the epitaxial layer, wherein the first well region is in contact with the front surface of the substrate, and carrying out high-temperature annealing on the first well region;
forming other areas outside the first well region in the epitaxial layer, synchronously forming a second well region and a third well region, and carrying out high-temperature annealing on the second well region and the third well region;
forming a first doped region in the first well region;
forming a second doped region in the second well region, forming a third doped region in the third well region, and performing high-temperature annealing on the second doped region and the third doped region;
forming a contact hole on the interlayer dielectric layer formed on the surfaces of the annealed epitaxial layer, the first doped region, the second doped region and the third doped region;
sputtering metal on the contact hole to form a first electrode and a second electrode above the contact hole respectively;
and forming a third electrode on the back surface of the substrate.
2. The method of claim 1, wherein the substrate, the epitaxial layer, the first well region, the second well region, the third well region, and the first doped region have a first doping type; the doping types of the second doping area and the third doping area are a second doping type opposite to the first doping type.
3. The method of claim 2, wherein the first doping type is N-type and the second doping type is P-type; or the first doping type is P type, and the second doping type is N type.
4. The method according to any of claims 1 to 3, wherein the doping concentration of the first well region is greater than the doping concentration of the epitaxial layer; the doping concentration of the second well region is the same as that of the third well region; the doping concentration of the second doping area is the same as that of the third doping area; the doping concentration of the first doping region is greater than that of the first well region.
5. A unidirectional negative resistance ESD protection device, comprising: a substrate, an epitaxial layer, a first well region, a second well region, a third well region, a first doped region, a second doped region, a third doped region, a first electrode, a second electrode, a third electrode,
the epitaxial layer is positioned above the front surface of the substrate;
the first well region is positioned in the epitaxial layer and connected with the substrate;
the second well region and the third well region are positioned in the epitaxial layer, and the first well region, the second well region and the third well region are arranged at intervals;
the first doped region is positioned in the first well region, the second doped region is positioned in the second well region, and the third doped region is positioned in the third well region;
the first electrode is positioned above the contact hole of the second doping region, the second electrode is positioned above the contact holes from the first doping region to the contact hole of the third doping region, and the contact hole of the first doping region, the contact hole of the second doping region and the contact hole of the third doping region are respectively formed on an interlayer dielectric layer formed on the surfaces of the annealed epitaxial layer, the first doping region, the second doping region and the third doping region through process treatment;
the third electrode is located on the back surface of the substrate.
6. The unidirectional negative resistance ESD protection device according to claim 5, wherein the second doped region forms an emitter region of a lateral open base region NPN transistor, the first well region, the epitaxial layer, and the second well region form a base region of the lateral open base region NPN transistor, the third doped region forms a collector region of the lateral open base region NPN transistor, and the unidirectional negative resistance ESD protection device is obtained by plastic-packaging the open base region NPN transistor.
7. A unidirectional negative resistance ESD protection device according to claim 5 or 6, further comprising:
and the interlayer dielectric layer is positioned on the surfaces of the epitaxial layer, the first doped region, the second doped region and the third doped region.
8. A unidirectional negative resistance ESD protection device according to claim 5 or 6, further comprising: a fourth well region and a fifth well region, wherein,
the fourth well region is positioned between the second doped region and the first well region, and the fifth well region is positioned between the third doped region and the third well region;
the doping concentration of the fourth well region is lower than that of the second doping region, and the doping concentration of the fifth well region is lower than that of the third doping region.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151603A (en) * | 2020-09-28 | 2020-12-29 | 上海华虹宏力半导体制造有限公司 | Triode and forming method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020043687A1 (en) * | 2000-10-18 | 2002-04-18 | Nobuaki Tsuji | Semiconductor input protection circuit |
| CN204441279U (en) * | 2015-04-03 | 2015-07-01 | 杭州士兰集成电路有限公司 | Bi-directional symmetrical ESD protective device |
| CN105489657A (en) * | 2016-02-24 | 2016-04-13 | 江苏捷捷微电子股份有限公司 | One-way low-voltage TVS device and manufacturing method thereof |
| US20170345811A1 (en) * | 2016-05-27 | 2017-11-30 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Method for manufacturing esd protection device |
| CN109065634A (en) * | 2018-07-24 | 2018-12-21 | 深圳市南硕明泰科技有限公司 | A kind of current protection chip and preparation method thereof |
| CN211654822U (en) * | 2020-05-09 | 2020-10-09 | 捷捷半导体有限公司 | Unidirectional negative resistance electrostatic discharge protection device |
| CN116519157A (en) * | 2023-05-16 | 2023-08-01 | 上海类比半导体技术有限公司 | Temperature sensor, manufacturing method thereof, semiconductor device and chip |
-
2020
- 2020-05-09 CN CN202010385095.9A patent/CN111540711B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020043687A1 (en) * | 2000-10-18 | 2002-04-18 | Nobuaki Tsuji | Semiconductor input protection circuit |
| CN204441279U (en) * | 2015-04-03 | 2015-07-01 | 杭州士兰集成电路有限公司 | Bi-directional symmetrical ESD protective device |
| CN105489657A (en) * | 2016-02-24 | 2016-04-13 | 江苏捷捷微电子股份有限公司 | One-way low-voltage TVS device and manufacturing method thereof |
| US20170345811A1 (en) * | 2016-05-27 | 2017-11-30 | Silergy Semiconductor Technology (Hangzhou) Ltd. | Method for manufacturing esd protection device |
| CN109065634A (en) * | 2018-07-24 | 2018-12-21 | 深圳市南硕明泰科技有限公司 | A kind of current protection chip and preparation method thereof |
| CN211654822U (en) * | 2020-05-09 | 2020-10-09 | 捷捷半导体有限公司 | Unidirectional negative resistance electrostatic discharge protection device |
| CN116519157A (en) * | 2023-05-16 | 2023-08-01 | 上海类比半导体技术有限公司 | Temperature sensor, manufacturing method thereof, semiconductor device and chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151603A (en) * | 2020-09-28 | 2020-12-29 | 上海华虹宏力半导体制造有限公司 | Triode and forming method thereof |
| CN112151603B (en) * | 2020-09-28 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | Triode and forming method thereof |
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