CN111540711B - Method for manufacturing unidirectional negative resistance ESD protection device and unidirectional negative resistance ESD protection device - Google Patents
Method for manufacturing unidirectional negative resistance ESD protection device and unidirectional negative resistance ESD protection device Download PDFInfo
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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Abstract
The invention provides a method for manufacturing a unidirectional negative resistance ESD protection device and the unidirectional negative resistance ESD protection device, wherein the method comprises the following steps: epitaxially growing an epitaxial layer on the front side of the substrate; forming a first well region in the epitaxial layer, wherein the first well region is contacted with the front surface of the substrate, and performing high-temperature annealing on the first well region; forming other areas outside the first well region in the epitaxial layer, synchronously forming a second well region and a third well region, and performing high-temperature annealing on the second well region and the third well region; forming a first doped region in the first well region; forming a second doped region in the second well region, forming a third doped region in the third well region, and performing high-temperature annealing on the second doped region and the third doped region; forming a contact hole on an interlayer dielectric layer formed on the surfaces of the annealed epitaxial layer, the first doped region, the second doped region and the third doped region; sputtering metal on the contact hole to form a first electrode and a second electrode above the contact hole; a third electrode is formed on the back side of the substrate. The surge protection capability can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a unidirectional negative resistance electrostatic discharge (ESD, electro STATIC DISCHARGE) protection device and the unidirectional negative resistance ESD protection device.
Background
With the rapid development of electronic products, ESD protection devices are widely used in electronic products to overcome static electricity generated during manufacturing, packaging, testing, transportation and use of the electronic products. It is counted that in the failure of the integrated circuit (IC, INTEGRATED CIRCUITS) function of an electronic product, the failure of the ESD protection device due to electrostatic surge is one of the important factors. Taking a battery module of a consumer electronic product as an example, the battery module receives impact of large surge current in the plugging process, so that an ESD protection device in the battery module needs to be capable of adapting to surge protection of different voltages of a power supply Voltage (VBAT) end and a USB Voltage (VBUS) end, for example, the voltage of the VBAT end is generally 4.5V, the voltage of the VBUS end is matched with an overvoltage protection (OVP, over Voltage Protection) scheme, and the voltage is different from 7V to 30V. Especially, with the increase of high-speed quick charge demands, the working voltage of the electronic product is gradually switched from traditional 7V and 12V to 18V, 22V and 24V or even higher voltage, so that the ESD protection device not only needs to bypass a large surge in a breakdown direction and a forward conduction direction to the ground, but also needs to ensure that a later-stage IC is not impacted by the surge, so that the ESD protection device which has smaller design cost and thinner and has the surge capacity meeting different actual surge demands in a circuit is a technical problem to be solved.
In the prior art, a unidirectional negative resistance ESD protection device is generally adopted, and FIG. 1 is a schematic structural diagram of the unidirectional negative resistance ESD protection device, as shown in FIG. 1, an N+ region is formed on a P substrate monocrystal through double-sided photoetching, so that a bipolar transistor with a vertical open base region is formed; the back surface forms a P+ region, back surface metal and the N+ region are formed for short circuit, and an equivalent circuit is that an open base region bipolar transistor and a diode are connected in parallel to form a unidirectional negative resistance ESD protection device. However, the unidirectional negative resistance ESD protection device has the problems of alignment precision of front side lithography and back side lithography due to the need of double-side lithography, so that surge current and residual voltage capability between batches are inconsistent, surge protection capability is not high, the requirement of high-voltage surge protection cannot be met, and the surge protection requirement of consumer products is difficult to meet.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method for manufacturing a unidirectional negative resistance ESD protection device and a unidirectional negative resistance ESD protection device, so as to improve the surge protection capability.
In a first aspect, embodiments of the present invention provide a method of manufacturing a unidirectional negative resistance ESD protection device, comprising:
epitaxially growing an epitaxial layer on the front side of the substrate;
Forming a first well region in the epitaxial layer, wherein the first well region is contacted with the front surface of the substrate, and performing high-temperature annealing on the first well region;
Forming other areas outside the first well region in the epitaxial layer, synchronously forming a second well region and a third well region, and performing high-temperature annealing on the second well region and the third well region;
Forming a first doped region in the first well region;
Forming a second doped region in the second well region, forming a third doped region in the third well region, and performing high-temperature annealing on the second doped region and the third doped region;
Forming a contact hole on an interlayer dielectric layer formed on the surfaces of the annealed epitaxial layer, the first doped region, the second doped region and the third doped region;
sputtering metal on the contact hole to form a first electrode and a second electrode above the contact hole respectively;
a third electrode is formed on the back side of the substrate.
With reference to the first aspect, the embodiment of the present invention provides a first possible implementation manner of the first aspect, where a doping type of the substrate, the epitaxial layer, the first well region, the second well region, the third well region, and the first doped region is a first doping type; the doping type of the second doping region and the third doping region is a second doping type opposite to the first doping type.
With reference to the first possible implementation manner of the first aspect, the embodiment of the present invention provides a second possible implementation manner of the first aspect, where the first doping type is N-type, and the second doping type is P-type; or the first doping type is P type, and the second doping type is N type.
With reference to the first aspect, the first possible implementation manner of the first aspect, or the second possible implementation manner of the first aspect, the embodiment of the present invention provides a third possible implementation manner of the first aspect, wherein a doping concentration of the first well region is greater than a doping concentration of the epitaxial layer; the doping concentration of the second well region is the same as that of the third well region; the doping concentration of the second doping region is the same as that of the third doping region; the doping concentration of the first doping region is greater than the doping concentration of the first well region.
In a second aspect, an embodiment of the present invention further provides a unidirectional negative resistance ESD protection device, including: the substrate, the epitaxial layer, the first well region, the second well region, the third well region, the first doped region, the second doped region, the third doped region, the first electrode, the second electrode and the third electrode, wherein,
The epitaxial layer is located above the front surface of the substrate;
The first well region is positioned in the epitaxial layer and connected with the substrate;
The second well region and the third well region are positioned in the epitaxial layer, and the first well region, the second well region and the third well region are arranged alternately;
the first doped region is positioned in the first well region, the second doped region is positioned in the second well region, and the third doped region is positioned in the third well region;
The first electrode is positioned above the contact hole of the second doped region, the second electrode is positioned above the contact holes of the first doped region to the contact hole of the third doped region, and the contact holes of the first doped region, the second doped region and the contact holes of the third doped region are respectively formed on an interlayer dielectric layer formed on the surfaces of the annealed epitaxial layer, the annealed first doped region, the annealed second doped region and the annealed third doped region through technological treatment;
The third electrode is positioned on the back surface of the substrate.
With reference to the second aspect, an embodiment of the present invention provides a first possible implementation manner of the second aspect, where the second doped region forms an emitter region of the laterally open base NPN transistor, the first well region, the epitaxial layer, and the second well region form a base region of the laterally open base NPN transistor, and the third doped region forms a collector region of the laterally open base NPN transistor, and the laterally open base NPN transistor is encapsulated to obtain a unidirectional negative resistance ESD protection device.
With reference to the second aspect or the first possible implementation manner of the second aspect, the embodiment of the present invention provides a second possible implementation manner of the second aspect, wherein the unidirectional negative resistance ESD protection device further includes:
the interlayer dielectric layer is positioned on the surfaces of the epitaxial layer, the first doped region, the second doped region and the third doped region.
With reference to the second aspect or the first possible implementation manner of the second aspect, the embodiment of the present invention provides a third possible implementation manner of the second aspect, wherein the unidirectional negative resistance ESD protection device further includes: a fourth well region and a fifth well region, wherein,
The fourth well region is positioned between the second doped region and the second well region, and the fifth well region is positioned between the third doped region and the third well region;
the doping concentration of the fourth well region is lower than that of the second doping region, and the doping concentration of the fifth well region is lower than that of the third doping region.
According to the method for manufacturing the unidirectional negative resistance ESD protection device and the unidirectional negative resistance ESD protection device, the epitaxial layer is epitaxially grown on the front side of the substrate; forming a first well region in the epitaxial layer, wherein the first well region is contacted with the front surface of the substrate, and performing high-temperature annealing on the first well region; forming other areas outside the first well region in the epitaxial layer, synchronously forming a second well region and a third well region, and performing high-temperature annealing on the second well region and the third well region; forming a first doped region in the first well region; forming a second doped region in the second well region, forming a third doped region in the third well region, and performing high-temperature annealing on the second doped region and the third doped region; forming a contact hole on an interlayer dielectric layer formed on the surfaces of the annealed epitaxial layer, the first doped region, the second doped region and the third doped region; sputtering metal on the contact hole to form a first electrode and a second electrode above the contact hole respectively; a third electrode is formed on the back side of the substrate. In this way, an emitter region-base region PN junction is formed by the first doped region and the first well region, a collector region-base region PN junction is formed by the second doped region and the second well region, and the two PN junctions are matched by doping concentration, so that bidirectional low-voltage ESD protection can be realized through a punch-through breakdown mode, bidirectional high-voltage ESD protection can be realized through an avalanche breakdown mode, and the surge protection capability of the unidirectional negative-resistance ESD protection device is effectively improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a schematic structure diagram of a conventional unidirectional negative resistance ESD protection device;
Fig. 2a shows a schematic structural diagram of a unidirectional negative resistance ESD protection device according to an embodiment of the present invention;
Fig. 2b is a schematic diagram of a unidirectional negative resistance ESD protection device according to another embodiment of the invention;
Fig. 3 is a schematic flow chart of a method for manufacturing a unidirectional negative resistance ESD protection device according to an embodiment of the present invention;
FIG. 4a shows a schematic diagram of the structure of the embodiment of the present invention after the processing of step 302;
FIG. 4b shows a schematic diagram of the structure of the embodiment of the present invention after the processing of step 303;
FIG. 4c shows a schematic diagram of the structure of the embodiment of the present invention after the processing of step 304;
FIG. 4d shows a schematic diagram of the structure of the embodiment of the present invention after the processing of step 305;
FIG. 4e shows a schematic diagram of the structure of the embodiment of the present invention after the processing of step 307;
FIG. 4f shows a schematic diagram of the structure of the embodiment of the present invention after the processing of step 308.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
Embodiments of the present invention provide a method for manufacturing a unidirectional negative resistance ESD protection device and a unidirectional negative resistance ESD protection device, and are described below by way of embodiments.
Fig. 2a shows a schematic structural diagram of a unidirectional negative resistance ESD protection device according to an embodiment of the invention. As shown in fig. 2a, the unidirectional negative resistance ESD protection device comprises: substrate 100, epitaxial layer 101, first well region 102, second well region 103, third well region 104, first doped region 105, second doped region 106, third doped region 107, first electrode 108, second electrode 109, third electrode 110, wherein,
Epitaxial layer 101 is located over the front side of substrate 100;
The first well region 102 is located in the epitaxial layer 101 and connected to the substrate;
The second well region 103 and the third well region 104 are located in the epitaxial layer 101, and the first well region 102, the second well region 103 and the third well region 104 are arranged alternately;
The first doped region 105 is located in the first well region 102, the second doped region 106 is located in the second well region 103, and the third doped region 107 is located in the third well region 104;
The first electrode 108 is located above the second doped region contact hole, the second electrode 109 is located above the first doped region contact hole to the third doped region contact hole, and the first doped region contact hole, the second doped region contact hole and the third doped region contact hole are respectively formed on interlayer dielectric layers formed on the surfaces of the annealed epitaxial layer 101, the annealed first doped region 105, the annealed second doped region 106 and the annealed third doped region 107 through process treatment;
the third electrode 110 is located on the back surface of the substrate 100.
In the embodiment of the present invention, as an optional embodiment, the doping types of the substrate 100, the epitaxial layer 101, the first well region 102, the second well region 103, the third well region 104, and the first doped region 105 are the first doping type;
the doping type of the second doping region 106 and the third doping region 107 is a second doping type opposite to the first doping type;
The doping concentration of the first well region 102 is greater than the doping concentration of the epitaxial layer 101;
The doping concentration of the second well region 103 is the same as the doping concentration of the third well region 104;
The doping concentration of the second doped region 106 is the same as the doping concentration of the third doped region 107;
the doping concentration of the first doped region 105 is greater than the doping concentration of the first well region 102.
In the embodiment of the present invention, as an optional embodiment, the first doping type is N-type, and the second doping type is P-type; as another alternative embodiment, the first doping type is P-type and the second doping type is N-type. In the following description, the substrate 100 is illustrated with a P-type doping as an example.
In this embodiment, as an alternative embodiment, the substrate 100 is heavily doped, the epitaxial layer 101 is lightly doped, the first well region 102, the second well region 103, and the third well region 104 are lightly doped, and the first doped region 105, the second doped region 106, and the third doped region 107 are heavily doped.
In the embodiment of the invention, the second doped region 106 forms an emitter region of the lateral open base region NPN transistor, the first well region 102, the epitaxial layer 101, and the second well region 103 form a base region of the lateral open base region NPN transistor, the third doped region 107 forms a collector region of the lateral open base region NPN transistor, and the unidirectional negative resistance ESD protection device is obtained by plastically packaging the base region NPN transistor.
In the embodiment of the invention, the characteristic of the NPN transistor with the transverse open base region is utilized to set the doping concentration collocation of the emitter region-base region and the collector region-base region, namely, the second doped region 106 and the second well region 103 are utilized to form an emitter region-base region PN junction, the third doped region 107 and the third well region 104 are utilized to form a collector region-base region PN junction, and the doping concentration collocation is utilized for the two PN junctions (the doped region-well region and the collector region-well region), so that the bidirectional low-voltage ESD protection can be realized through a punch-through breakdown mode, and the bidirectional high-voltage ESD protection can be realized through an avalanche breakdown mode.
In the embodiment of the present invention, when the ESD pulse or surge received by the first electrode 108 is positive (the potential of the first electrode 108 is positive, the potential of the third electrode 110 is negative, the first electrode 108 and the third electrode 110 form the reverse breakdown direction of the unidirectional negative resistance electrostatic discharge protection device), the forward ESD pulse or surge flows through the NPN transistor with the laterally opened base region,
The direction from the second electrode 109, the first doped region 105, and the first well region 102 to the substrate 100 forms a breakdown voltage direction of the unidirectional negative resistance ESD protection device, where the breakdown voltage direction is a negative resistance characteristic direction of the unidirectional negative resistance ESD protection device, that is, a first branch of reverse static electricity and surge discharging, and the direction from the substrate 100, the first well region 102, and the first doped region 105 to the second electrode 109 forms a second branch of forward static electricity and surge discharging;
The substrate 100, the epitaxial layer 101, the second well region 103 and the second doped region 106 form a first branch of forward static electricity and surge discharge in the forward characteristic direction of the unidirectional negative resistance ESD protection device, and the second doped region 106, the second well region 103, the epitaxial layer 101 and the substrate 100 form a second branch of reverse static electricity and surge discharge.
When the ESD pulse or surge received by the first electrode 108 is negative (the potential of the first electrode 108 is negative, and the potential of the third electrode 110 is positive), a forward diode is formed between the third electrode 110 and the first electrode 108, and a forward conduction direction is formed, that is: the directions from the substrate 100, the epitaxial layer 101 and the second well region 103 to the second doped region 106 form a positive characteristic direction of a positive conduction (positive static electricity) direction of the unidirectional negative resistance ESD protection device and a first branch for discharging negative ESD and surge; the direction of the substrate 100, the first well region 102, the first doped region 105 to the second electrode 109 constitutes a second branch of discharging negative ESD, surge in the positive electrostatic direction.
In an embodiment of the present invention, as an optional embodiment, the unidirectional negative resistance ESD protection device further includes:
An interlayer dielectric layer (not shown) is located on the surface of the epitaxial layer 101, the first doped region 105, the second doped region 106 and the third doped region 107.
In the embodiment of the present invention, the interlayer dielectric layer is a silicon dioxide layer formed on the surface of the epitaxial layer 101, the first doped region 105, the second doped region 106 and the third doped region 107 after annealing, or an SI 3N4 layer formed on the surface of silicon dioxide by a chemical vapor deposition (CVD, chemical Vapor Deposition) process.
Fig. 2b is a schematic diagram of a unidirectional negative resistance ESD protection device according to another embodiment of the invention. As shown in fig. 2b, with respect to fig. 2a, further includes: a fourth well region 211, and a fifth well region 212, wherein,
The fourth well region 211 is located between the second doped region 106 and the second well region 103, and the fifth well region 212 is located between the third doped region 107 and the third well region 104;
The doping concentration of the fourth well region 211 is lower than the doping concentration of the second doped region 106, and the doping concentration of the fifth well region 212 is lower than the doping concentration of the third doped region 107.
In the embodiment of the present invention, as an alternative embodiment, the doping types of the fourth well region 211 and the fifth well region are both N-type doping, and the doping concentration is light doping.
In the embodiment of the present invention, by adding the fourth well region 211 and the fifth well region 212, the second doped region 106 and the fourth well region 211 form an emitter region of the NPN transistor with the laterally opened base region, the second well region 103, the epitaxial layer 101, and the third well region 104 form a base region of the NPN transistor with the laterally opened base region, and the fifth well region 212 and the third doped region 107 form a collector region of the NPN transistor with the laterally opened base region. Because the emitter region and the base region are added with the fourth well region 211, the collector region and the base region are added with the fifth well region 212, and the doping concentration of the fourth well region 211 and the fifth well region 212 is lower, the junction depletion regions of the emitter region-base region and the collector region-base region cannot be widened to the second doped region 106 and the third doped region 107, reverse breakdown occurs in vivo, and the breakdown mechanism is avalanche breakdown, so that the withstand voltage of the ESD protection device of the embodiment is greater than that of the unidirectional negative resistance ESD protection device shown in fig. 2a, and the ESD protection device can bear higher reverse breakdown voltage when the first electrode 108 receives forward ESD and surge, and can be applied to ESD protection and surge protection in a circuit with higher working voltage.
In an embodiment of the invention, the second electrode 109 is attached to the substrate 100; the substrate 100 and the epitaxial layer 101 form an ESD and surge discharging channel to the first doped region 105, so that a unidirectional negative resistance function can be realized, double-sided photoetching precision alignment errors can be effectively avoided, surge capacity uniformity is improved, large surge capacity and low residual voltage are realized, when a charged IC chip is protected, an OVP device is matched, the effect of ultralow positive surge clamping voltage and negative surge clamping voltage can be achieved, a good protection effect is provided for various IC chips at the rear end, and the device can be widely applied to static electricity and surge protection of interfaces such as consumer electronics, automobile electronics and industrial control.
Fig. 3 is a flow chart of a method for manufacturing a unidirectional negative resistance ESD protection device according to an embodiment of the invention. As shown in fig. 3, the method includes:
Step 301, epitaxially growing an epitaxial layer 101 on the front surface of the substrate 100;
in an embodiment of the present invention, as an alternative embodiment, the doping type of the substrate 100 is P-type doping. Wherein the range of resistivity of the substrate 100 includes, but is not limited to: 0.1-0.001 Ω & cm. In some preferred embodiments, a low resistivity substrate 100 is selected, for example, the resistivity of the selected substrate 100 is 0.004-0.008 Ω cm, and in still other preferred embodiments, the resistivity of the selected substrate 100 is less than 0.006 Ω cm, and the lower resistivity can effectively reduce the dynamic resistance of the ESD protection device.
In an embodiment of the present invention, as an alternative embodiment, the substrate 100 is a P-type substrate slice, and the epitaxial layer 101 is grown on the P-type substrate slice at a high temperature by using an epitaxial furnace. The epitaxial layer 101 is a P-type epitaxial layer having a resistivity in the range of 0.01 to 10Ω·cm and a thickness of 5 to 15 μm.
Step 302, forming a first well region 102 in the epitaxial layer 101, wherein the first well region 102 is in contact with the front surface of the substrate 100, and performing high-temperature annealing on the first well region 102;
FIG. 4a shows a schematic structural diagram of the embodiment of the present invention after the processing of step 302. As shown in fig. 4a, in the embodiment of the present invention, the first well region 102 is formed in the epitaxial layer 101 by a process, wherein the process includes, but is not limited to: and (5) photoetching and etching. The first well region 102 is formed in the epitaxial layer 101 by a conventional process such as photolithography, etching, etc., and the doping type of the first well region 102 is P-type, and the doping impurities include, but are not limited to, boron. Taking doped impurities as boron for example, the (boron) ion implantation dose is 1E14/cm 2-1E15/cm2, and the implantation energy is 50-120KeV.
In this embodiment, as an alternative embodiment, the first well region 102 is located on one side of the epitaxial layer 101, for example, on the left or right side. After forming the first well region 102, the first well region 102 is subjected to high temperature annealing. As an alternative embodiment, the annealing temperature is 1100-1200 ℃ and the annealing time is 1.0-3.0 h.
Step 303, forming other regions outside the first well region 102 in the epitaxial layer 101, forming the second well region 103 and the third well region 104 simultaneously, and performing high-temperature annealing on the second well region 103 and the third well region 104;
fig. 4b shows a schematic structural diagram of the embodiment of the present invention after the processing of step 303. In the embodiment of the present invention, as shown in fig. 4b, the second well region 103 and the third well region 104 are formed simultaneously in the epitaxial layer 101 by photolithography and etching other regions outside the first well region 102, and the doping types of the second well region 103 and the third well region 104 are P-type. As an alternative embodiment, the dopant impurity may be boron with an ion implantation dose of 1E13/cm 2-1E15/cm2 and an implantation energy of 50-120Kev.
In the embodiment of the present invention, after forming the second well region 103 and the third well region 104, the second well region 103 and the third well region are annealed at a high temperature. As an alternative embodiment, the annealing temperature is 1000-1100 ℃ and the annealing time is 0.5-2 h.
Step 304, forming a first doped region 105 in the first well region 102;
Fig. 4c shows a schematic structural diagram of the embodiment of the present invention after the processing of step 304. As shown in fig. 4c, in the embodiment of the present invention, the first doped region 105 is formed in the first well region 102 by conventional processes such as photolithography and etching, the doping type of the first doped region 105 is P-type, the doping impurity may be boron, the ion implantation dose is 1E15/cm 2-8e15/cm2, and the implantation energy is 40-80KeV.
Step 305, forming a second doped region 106 in the second well region 103, and forming a third doped region 107 in the third well region 104, and performing high temperature annealing on the second doped region 106 and the third doped region 107;
Fig. 4d shows a schematic structural diagram of the embodiment of the present invention after the processing of step 305. In the embodiment of the present invention, as shown in fig. 4d, in the second well region 103 and the third well region 104, the second doped region 106 and the third doped region 107 are formed by conventional processes such as photolithography and etching, respectively, the doping types of the second doped region 106 and the third doped region 107 are N-type, the doping may be phosphorus, the ion implantation dose is 1E15/cm 2-1E16/cm2, and the implantation capability is 40-80KeV.
In the embodiment of the present invention, after the second doped region 106 and the third doped region 107 are formed, the second doped region 106 and the third doped region 107 are annealed at a high temperature. As an alternative embodiment, the annealing temperature is 950-1050 ℃ and the annealing time is 0.5-1 h.
In the embodiment of the present invention, as an optional embodiment, the doping types of the substrate 100, the epitaxial layer 101, the first well region 102, the second well region 103, the third well region 104, and the first doped region 105 are the first doping type; the doping type of the second doping region 106 and the third doping region 107 is a second doping type opposite to the first doping type.
In the embodiment of the present invention, as an optional embodiment, the first doping type is N-type, and the second doping type is P-type; or the first doping type is P type, and the second doping type is N type.
In the embodiment of the present invention, the doping concentration of the first well region 102 is greater than the doping concentration of the epitaxial layer 101; the doping concentration of the second well region 103 is the same as the doping concentration of the third well region 104; the doping concentration of the second doped region 106 is the same as the doping concentration of the third doped region 107; the doping concentration of the first doped region 105 is greater than the doping concentration of the first well region 102.
In this embodiment, as an alternative embodiment, the substrate 100 is heavily doped, the epitaxial layer 101 is lightly doped, the first well region 102, the second well region 103, and the third well region 104 are lightly doped, and the first doped region 105, the second doped region 106, and the third doped region 107 are heavily doped.
In the embodiment of the invention, the second doped region 106 forms an emitter region of the lateral open base region NPN transistor, the first well region 102, the epitaxial layer 101, and the second well region 103 form a base region of the lateral open base region NPN transistor, the third doped region 107 forms a collector region of the lateral open base region NPN transistor, and the lateral open base region NPN transistor is subsequently encapsulated to obtain a unidirectional negative resistance ESD protection device.
Step 306, forming contact holes on the interlayer dielectric layers formed on the surfaces of the annealed epitaxial layer 101, the first doped region 105, the second doped region 106 and the third doped region 107;
In the embodiment of the present invention, the interlayer dielectric layer (not shown in the figure) is a silicon dioxide layer formed after annealing, or an SI 3N4 layer formed on the silicon dioxide surface by a chemical vapor deposition (CVD, chemical Vapor Deposition) process.
In the embodiment of the present invention, a contact hole (not shown in the figure) is formed on the interlayer dielectric layer through conventional processes such as photolithography and etching, where the contact hole includes: the first doped region contact hole, the second doped region contact hole and the third doped region contact hole.
Step 307, sputtering metal on the contact hole to form a first electrode 108 and a second electrode 109 respectively above the contact hole;
Fig. 4e shows a schematic structural diagram of the embodiment of the present invention after the processing of step 307. As shown in fig. 4e, in the embodiment of the present invention, an aluminum layer with a thickness of 2-5um is formed by evaporation or sputtering, and conventional processes such as photolithography and etching are performed on the aluminum layer formed on the surface, so that the first electrode 108 is formed on the metal above the contact hole of the second doped region; a common second electrode 109 is formed over the third doped region contact hole with the metal over the first doped region contact hole.
In the embodiment of the invention, an interlayer dielectric layer is formed on the surfaces of the epitaxial layer 101, the first doped region 105, the second doped region 106 and the third doped region 107; photoetching and etching the interlayer dielectric layer to form a contact hole comprising a first doped region contact hole, a second doped region contact hole and a third doped region contact hole; metal (aluminum) is sputtered in the contact hole, thereby forming a first electrode 108 over the second doped region contact hole, and a common second electrode 109 is formed over the first doped region contact hole and the third doped region contact hole.
In step 308, a third electrode 110 is formed on the back side of the substrate 100.
FIG. 4f shows a schematic diagram of the structure of the embodiment of the present invention after the processing of step 308. As shown in fig. 4f, in the embodiment of the present invention, after lapping the back surface of the substrate 100 and etching silicon, the metal is evaporated through a metallization process, for example, so that the metal under the back surface of the substrate 100 forms the third electrode 110.
It should be noted that in embodiments of the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the invention as described above, these embodiments are not exhaustive of all details, nor are they intended to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (5)
1. A method of manufacturing a unidirectional negative resistance electrostatic discharge, ESD, protection device, comprising:
epitaxially growing an epitaxial layer on the front side of the substrate;
Forming a first well region in the epitaxial layer, wherein the first well region is contacted with the front surface of the substrate, and performing high-temperature annealing on the first well region;
Forming other areas outside the first well region in the epitaxial layer, synchronously forming a second well region and a third well region, and performing high-temperature annealing on the second well region and the third well region;
Forming a first doped region in the first well region;
Forming a second doped region in the second well region, forming a third doped region in the third well region, and performing high-temperature annealing on the second doped region and the third doped region;
Forming a contact hole on an interlayer dielectric layer formed on the surfaces of the annealed epitaxial layer, the first doped region, the second doped region and the third doped region;
sputtering metal on the contact hole to form a first electrode and a second electrode above the contact hole respectively;
forming a third electrode on the back surface of the substrate;
The doping types of the substrate, the epitaxial layer, the first well region, the second well region, the third well region and the first doping region are first doping types; the doping types of the second doping region and the third doping region are second doping types opposite to the first doping types;
the doping concentration of the first well region is larger than that of the epitaxial layer; the doping concentration of the second well region is the same as that of the third well region; the doping concentration of the second doping region is the same as that of the third doping region; the doping concentration of the first doping region is greater than that of the first well region;
The second doping region forms an emitter region of the lateral open base region NPN transistor, the first well region, the epitaxial layer and the second well region form a base region of the lateral open base region NPN transistor, the third doping region forms a collector region of the lateral open base region NPN transistor, and the unidirectional negative resistance ESD protection device is obtained by plastically packaging the base region NPN transistor.
2. The method of claim 1, wherein the first doping type is N-type and the second doping type is P-type; or the first doping type is P type, and the second doping type is N type.
3. A unidirectional negative resistance ESD protection device comprising: the substrate, the epitaxial layer, the first well region, the second well region, the third well region, the first doped region, the second doped region, the third doped region, the first electrode, the second electrode and the third electrode, wherein,
The epitaxial layer is located above the front surface of the substrate;
The first well region is positioned in the epitaxial layer and connected with the substrate;
The second well region and the third well region are positioned in the epitaxial layer, and the first well region, the second well region and the third well region are arranged alternately;
the first doped region is positioned in the first well region, the second doped region is positioned in the second well region, and the third doped region is positioned in the third well region;
The first electrode is positioned above the contact hole of the second doped region, the second electrode is positioned above the contact holes of the first doped region to the contact hole of the third doped region, and the contact holes of the first doped region, the second doped region and the contact holes of the third doped region are respectively formed on an interlayer dielectric layer formed on the surfaces of the annealed epitaxial layer, the annealed first doped region, the annealed second doped region and the annealed third doped region through technological treatment;
The third electrode is positioned on the back surface of the substrate;
The doping types of the substrate, the epitaxial layer, the first well region, the second well region, the third well region and the first doping region are first doping types; the doping types of the second doping region and the third doping region are second doping types opposite to the first doping types;
the doping concentration of the first well region is larger than that of the epitaxial layer; the doping concentration of the second well region is the same as that of the third well region; the doping concentration of the second doping region is the same as that of the third doping region; the doping concentration of the first doping region is greater than that of the first well region;
The second doping region forms an emitter region of the lateral open base region NPN transistor, the first well region, the epitaxial layer and the second well region form a base region of the lateral open base region NPN transistor, the third doping region forms a collector region of the lateral open base region NPN transistor, and the unidirectional negative resistance ESD protection device is obtained by plastically packaging the base region NPN transistor.
4. A unidirectional negative resistance ESD protection device as claimed in claim 3, further comprising:
the interlayer dielectric layer is positioned on the surfaces of the epitaxial layer, the first doped region, the second doped region and the third doped region.
5. The unidirectional negative resistance ESD protection device of claim 3 or 4, further comprising: a fourth well region and a fifth well region, wherein,
The fourth well region is positioned between the second doped region and the second well region, and the fifth well region is positioned between the third doped region and the third well region;
the doping concentration of the fourth well region is lower than that of the second doping region, and the doping concentration of the fifth well region is lower than that of the third doping region.
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