CN107293533B - Transient voltage suppressor and method of manufacturing the same - Google Patents
Transient voltage suppressor and method of manufacturing the same Download PDFInfo
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- CN107293533B CN107293533B CN201710600903.7A CN201710600903A CN107293533B CN 107293533 B CN107293533 B CN 107293533B CN 201710600903 A CN201710600903 A CN 201710600903A CN 107293533 B CN107293533 B CN 107293533B
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- 230000001052 transient effect Effects 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 61
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims description 18
- 238000004806 packaging method and process Methods 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 230000002829 reductive effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 79
- 239000002019 doping agent Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- PMRMTSSYYVAROU-UHFFFAOYSA-N [Ti].[Ni].[Au] Chemical compound [Ti].[Ni].[Au] PMRMTSSYYVAROU-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- MZFIXCCGFYSQSS-UHFFFAOYSA-N silver titanium Chemical compound [Ti].[Ag] MZFIXCCGFYSQSS-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- -1 aluminum silicon copper Chemical compound 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000005018 casein Substances 0.000 description 1
- BECPQYXYKAMYBN-UHFFFAOYSA-N casein, tech. Chemical class NCCCCC(C(O)=O)N=C(O)C(CC(O)=O)N=C(O)C(CCC(O)=N)N=C(O)C(CC(C)C)N=C(O)C(CCC(O)=O)N=C(O)C(CC(O)=O)N=C(O)C(CCC(O)=O)N=C(O)C(C(C)O)N=C(O)C(CCC(O)=N)N=C(O)C(CCC(O)=N)N=C(O)C(CCC(O)=N)N=C(O)C(CCC(O)=O)N=C(O)C(CCC(O)=O)N=C(O)C(COP(O)(O)=O)N=C(O)C(CCC(O)=N)N=C(O)C(N)CC1=CC=CC=C1 BECPQYXYKAMYBN-UHFFFAOYSA-N 0.000 description 1
- 235000021240 caseins Nutrition 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The application discloses a transient voltage suppressor and a manufacturing method thereof, wherein the transient voltage suppressor comprises a semiconductor substrate; an epitaxial layer on the first surface of the semiconductor substrate; an isolation region extending from a surface of the epitaxial layer through the epitaxial layer into the semiconductor substrate for defining first and second isolation islands in the epitaxial layer; doped regions extending from a surface of the epitaxial layer into the epitaxial layer in the first and second isolation islands, respectively; a first electrode for electrically connecting the doped regions to each other; and a second electrode for electrically connecting the isolation region and a portion of the epitaxial layer located at the second isolation island to each other. According to the transient voltage suppressor, one of two parallel longitudinal NPN structures is short-circuited into a PN structure through a metal electrode, so that the PN structure becomes a transient voltage suppressor with unidirectional low clamping voltage, and the chip size and the packaging cost are reduced.
Description
Technical Field
The present application relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a transient voltage suppressor and a method of manufacturing the same.
Background
A transient voltage suppressor (Transient Voltage Suppressor, TVS) is a device for protecting integrated circuits from overvoltage damage. The integrated circuits are designed to operate over a normal range of voltages. However, unpredictable, uncontrollable high voltages resulting from accidents such as electrostatic discharge (Electronic Static Discharge, ESD), electrical transients and lightning can cause damage to the circuit. When such high voltages are generated, TVS devices are required to protect the integrated circuit, circumventing these conditions which may damage the integrated circuit.
Unidirectional TVS devices are widely used to protect integrated circuits for such applications. Such devices are limited in their manner of operation. The unidirectional TVS device is reverse biased when cycled instantaneously (i.e., positive voltage peak). The device operates in avalanche mode, introducing transient currents to ground. The transients are embedded at the clamping energy level provided by the TVS device, ensuring protection of the integrated circuit. When the transient negative cycle (i.e., negative voltage peak), the unidirectional TVS device is forward biased and current is conducted in the forward direction.
When the unidirectional TVS device is designed, the single junction voltage can be controlled only by adjusting the resistivity of the substrate, but when the voltage is expected to be further reduced below 6V, the conventional single junction diode cannot meet the application environment of low leakage current below 6V because the breakdown of the single junction diode will be mainly zener breakdown and the leakage current is uncontrollable.
In order to meet the requirement of low leakage current of a TVS device under low clamping voltage, a person skilled in the art tends to use an NPN triode structure to reduce Vce by a method of heightening beta, or adopts a method of parallel packaging of a common diode and a bidirectional low-clamping TVS device to realize low working voltage and low clamping voltage, but the TVS device obtained by adopting the NPN triode structure is of a bidirectional structure and cannot meet the application environment of some unidirectional TVS devices, and the second method is adopted, although the function of the unidirectional low-clamping TVS device can be realized, the packaging cost is greatly increased due to the fact that the method is realized by a multi-chip combined packaging method.
Disclosure of Invention
Accordingly, the present application is directed to a unidirectional-conduction transient voltage suppressor and a method for manufacturing the same, which can be applied to low-clamp voltage electronic devices and has low packaging cost.
In order to solve the above technical problem, according to a first aspect of the present application, there is provided a transient voltage suppressor comprising: a semiconductor substrate of a first doping type; an epitaxial layer of a second doping type on the first surface of the semiconductor substrate, wherein the first doping type is different from the second doping type; an isolation region of a first doping type extending from a surface of the epitaxial layer through the epitaxial layer into the semiconductor substrate for defining first and second isolation islands in the epitaxial layer; a doped region of a first doping type extending from a surface of the epitaxial layer into the epitaxial layer in the first and second isolation islands, respectively; a first electrode for electrically connecting the doped regions to each other; and a second electrode for electrically connecting the isolation region and a portion of the epitaxial layer located at the second isolation island to each other.
Preferably, an insulating layer is further included on the epitaxial layer.
Preferably, the semiconductor device further comprises a third electrode, wherein the third electrode is positioned on the second surface of the semiconductor substrate, and the first surface and the second surface are opposite to each other.
Preferably, the second isolated island surrounds the first isolated island.
Preferably, the first doping type is N-type or P-type, and the second doping type is the other of N-type or P-type.
According to a second aspect of the present application, there is provided a method of manufacturing a transient voltage suppressor comprising: forming an epitaxial layer of a second doping type on the first surface of the semiconductor substrate of the first doping type, wherein the first doping type is different from the second doping type; forming an isolation region of a first doping type extending from a surface of the epitaxial layer through the epitaxial layer into the semiconductor substrate for defining first and second isolation islands in the epitaxial layer; forming a doped region of a first doping type, the doped region extending from a surface of the epitaxial layer into the epitaxial layer in the first and second isolation islands, respectively; and forming a first electrode electrically connecting the doped regions to each other and a second electrode electrically connecting the isolation region and a portion of the epitaxial layer located in the second isolation island to each other.
Preferably, after the step of forming the doped region of the first doping type, further comprises: forming an insulating layer on the epitaxial layer; and forming a plurality of openings on the insulating layer, wherein the doped region, the part of the epitaxial layer, which is positioned on the second isolation island, and part of the isolation island are respectively exposed outside through the openings.
Preferably, a third electrode is formed on a second surface of the semiconductor substrate, the first surface and the second surface being opposite to each other.
Preferably, the second isolated island surrounds the first isolated island.
Preferably, the first doping type is N-type or P-type, and the second doping type is the other of N-type or P-type.
After the technical scheme of the application is adopted, the following beneficial effects can be obtained:
one of the two parallel longitudinal NPN structures is short-circuited into a PN structure through a metal electrode, so that the PN structure becomes a transient voltage suppressor of unidirectional low clamping voltage, and the chip size and the packaging cost are reduced.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the application with reference to the accompanying drawings, in which:
fig. 1 shows a block diagram of a transient voltage suppressor according to a first embodiment of the present application.
Fig. 2a to 2f show cross-sectional views of various stages of a method of manufacturing a transient voltage suppressor according to a first embodiment of the application.
Detailed Description
The present application is described below based on examples, but the present application is not limited to only these examples. In the following detailed description of embodiments of the application, certain specific details are set forth in order to provide a thorough understanding of the application. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the application.
Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings. The flowcharts, block diagrams in the figures illustrate the possible architecture, functionality, and operation of systems, methods, devices according to embodiments of the present application, and the order of the blocks in the figures are merely for better illustrating the processes and steps of the embodiments, and should not be taken as limiting the application itself.
The application will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.
If, for the purposes of describing a situation directly on top of another layer, another region, the expression "a directly on top of B" or "a directly on top of B and adjoining it" will be used herein. In the present application, "a is directly in B" means that a is in B and a is directly adjacent to B, instead of a being in the doped region formed in B.
In the present application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed.
Numerous specific details of the application, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.
Fig. 1 shows a block diagram of a transient voltage suppressor according to a first embodiment of the present application. In the following description, the doping type of the semiconductor material will be described as being specifically one of P-type and N-type. It will be appreciated that semiconductor devices of the same function can also be obtained if the doping type of the respective semiconductor material is reversed.
As shown in fig. 1, TVS device 100 includes a semiconductor substrate 101, an epitaxial layer 102 on a first surface of semiconductor substrate 101, an isolation region 103 in epitaxial layer 102, and a doped region 104 in epitaxial layer 102.
The semiconductor substrate 101 is, for example, a heavily doped N-type semiconductor substrate, and the epitaxial layer 102 is, for example, a P-type epitaxial layer. To form a P-type or N-type semiconductor layer or region, a corresponding type of dopant may be incorporated into the semiconductor layer or region. For example, the P-type dopant includes boron and the N-type dopant includes phosphorus or arsenic or antimony.
In this embodiment, the semiconductor substrate 101 is a heavily doped N-type substrate having a resistivity of not more than 0.02 Ω·cm. The epitaxial layer 102 is a P-type epitaxial layer 102 having a resistivity of not less than 0.01Ω·cm and a thickness of not less than 2 μm.
The isolation region 103 is, for example, a heavily doped N-type doped region, and the isolation region 103 extends from the surface of the epitaxial layer 102 to the semiconductor substrate 101, thereby defining a plurality of isolation islands in the epitaxial layer 102. In this embodiment, the second isolated island surrounds the first isolated island. One skilled in the art can control the concentration of isolation region 103 according to device requirements, e.g., not less than E19cm -3 。
The doped region 104 is, for example, not less than E19cm -3 Is located in each of the isolated islands extending from the surface of epitaxial layer 102 into epitaxial layer 102.
Further, TVS device 100 further includes insulating layer 105, first electrode 106, second electrode 107, and third electrode 108.
An insulating layer 105 is located on the epitaxial layer 102, a first electrode 106 electrically connects the doped regions 104 through an opening in the insulating layer 105, a second electrode 107 electrically connects a portion of the isolation region 103 and a portion of the epitaxial layer 102 located on the second isolation island to each other through an opening in the insulating layer 105, and a third electrode 108 is located on a second surface of the semiconductor substrate 101, the second surface being opposite to the first surface. The insulating layer 105 is made of silicon oxide or silicon nitride, and the first electrode 106, the second electrode 107, and the third electrode 108 are made of a metal or an alloy selected from gold, silver, copper, aluminum silicon copper, titanium silver, titanium nickel gold, or the like.
In TVS device 100 shown in fig. 1, semiconductor substrate 101, epitaxial layer 102 and doped region 104 located in the portion of the first isolation island form a stack of a first NPN structure, semiconductor substrate 101, epitaxial layer 102 and doped region 104 located in the portion of the second isolation island form a stack of a second NPN structure, and first electrode 106 connects the two NPN structures in parallel. Wherein the second NPN structure stack functions substantially the same as the PN structure stack because the second electrode 107 shorts the portion of the epitaxial layer 102 located in the second isolation island to the isolation region 103. When the PN structure is turned on, the flow direction of the current is shown as a broken line in fig. 1, that is, the current flows from the first electrode 106, the doped region 104, the portion of the epitaxial layer 102 located in the second isolation island, the second electrode 107, the isolation region 103 to the semiconductor substrate 101.
Fig. 2a to 2f show cross-sectional views of various stages of a method of manufacturing a transient voltage suppressor according to a first embodiment of the application.
As shown in fig. 2a, a P-type epitaxial layer 102 is formed on a first surface of a heavily doped N-type semiconductor substrate 101.
To form a P-type or N-type semiconductor layer or region, the semiconductor layer and region may be doped with a corresponding type of dopant, e.g., a P-type dopant including boron and an N-type dopant including phosphorus or arsenic or antimony. In this embodiment, the semiconductor substrate 101 is a heavily doped N-type substrate having a resistivity of not more than 0.02 Ω·cm.
Epitaxial layer 102 may be formed using known deposition processes. For example, the deposition process may be one selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering. In this embodiment, the epitaxial layer 102 is a P-type epitaxial layer having a resistivity of not less than 0.01Ω·cm, and a thickness of not less than 2 μm.
As shown in fig. 2b, isolation regions 103 are then formed in the epitaxial layer 102 by thermal diffusion.
Isolation regions 103 extend from the surface of epitaxial layer 102 to semiconductor substrate 101, thereby defining a plurality of isolation islands in epitaxial layer 102, in this caseIn an embodiment, the second isolated island surrounds the first isolated island. The concentration of the isolation region 103 will affect the on-resistance of the rectifying device, and those skilled in the art can control the concentration of the isolation region 103 according to the device requirement, but too low concentration of the isolation region 103 will severely restrict the current capability of the rectifying device, and should be controlled to be not less than E19cm -3 On the order of magnitude.
As shown in fig. 2c, subsequently, heavily doped N-type doped regions 104 are formed in the first and second isolation islands, and an insulating layer 105 is formed on the epitaxial layer 102.
In this embodiment, the doped region 104 is formed by phosphorus diffusion to a concentration not less than E19cm -3 Which extend from the surface of epitaxial layer 102 into epitaxial layer 102 in respective isolated islands.
The insulating layer 105 may be formed using sputtering or thermal oxidation. For example, the insulating layer 105 is a silicon oxide layer formed by thermal oxidation, and in a subsequent doping step, the insulating layer 105 serves as a protective layer and will serve as an interlayer insulating layer 105 of the final device.
As shown in fig. 2d, a plurality of openings are then formed in the insulating layer 105 by photolithography, the doped region 104, the portion of the epitaxial layer 102 located in the second isolation island and the portion of the isolation region 103 being exposed through the openings, wherein the portion of the epitaxial layer 102 located in the second isolation island and the portion of the isolation region 103 are adjacent to each other.
As shown in fig. 2e, a first electrode 106 and a second electrode 107 are formed, the second electrode 107 electrically connects the portion of the epitaxial layer 102 located in the second isolation island and the portion of the isolation region 103 via the opening in the insulating layer 105, the stack of the NPN structure formed by the doped region 104, the portion of the epitaxial layer 102 located in the second isolation island and the semiconductor substrate 101 is changed into a stack of the PN structure, and the first electrode 106 electrically connects the doped regions 104 via the opening in the insulating layer 105, thereby realizing parallel connection of the NPN structure and the PN structure.
As shown in fig. 2f, the chip is then thinned and back-side metallized, forming a third electrode 108 on the second surface of the semiconductor substrate 101 as a ground terminal.
In this embodiment, gold is used as the third electrode 108. One skilled in the art can select different metals or metal alloys as the backside metal layer, such as gold, silver, copper, titanium silver, titanium nickel gold, etc., depending on the packaging form.
It can be seen that the device according to the present application can produce a transient voltage suppressor of unidirectional low clamping voltage in a simple step. One of the two parallel longitudinal NPN structures is short-circuited into a PN structure through a metal electrode, so that the PN structure becomes a transient voltage suppressor of unidirectional low clamping voltage, and the chip size and the packaging cost are reduced.
It should be understood by those skilled in the art that the spacing between the bottom of the doped region 104 and the first surface of the semiconductor substrate 101, the spacing between the doped region 104 and the isolation region 103, and the doping concentration of each doped region may be reasonably designed to control the amplification factor of the NPN structure to obtain a desired low clamping voltage transient voltage suppressor.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.
Claims (6)
1. A transient voltage suppressor, comprising:
a semiconductor substrate of a first doping type;
an epitaxial layer of a second doping type on the first surface of the semiconductor substrate, wherein the first doping type is different from the second doping type;
an isolation region of a first doping type extending from a surface of the epitaxial layer through the epitaxial layer into the semiconductor substrate for defining first and second isolation islands in the epitaxial layer, and the second isolation island surrounding the first isolation island;
a doped region of a first doping type extending from a surface of the epitaxial layer into the epitaxial layer in the first and second isolation islands, respectively;
a first electrode for electrically connecting the doped regions to each other; and
a second electrode for electrically connecting the isolation region and a portion of the epitaxial layer located at the second isolation island to each other;
and a third electrode positioned on a second surface of the semiconductor substrate, the first surface and the second surface being opposite to each other.
2. The transient voltage suppressor of claim 1, further comprising an insulating layer on said epitaxial layer.
3. The transient voltage suppressor of claim 1, wherein said first doping type is either N-type or P-type and said second doping type is the other of either N-type or P-type.
4. A method of manufacturing a transient voltage suppressor comprising:
forming an epitaxial layer of a second doping type on the first surface of the semiconductor substrate of the first doping type, wherein the first doping type is different from the second doping type;
forming an isolation region of a first doping type extending from a surface of the epitaxial layer through the epitaxial layer into the semiconductor substrate for defining first and second isolation islands in the epitaxial layer, and the second isolation island surrounding the first isolation island;
forming a doped region of a first doping type, the doped region extending from a surface of the epitaxial layer into the epitaxial layer in the first and second isolation islands, respectively; and
forming a first electrode electrically connecting the doped regions to each other and a second electrode electrically connecting the isolation region and a portion of the epitaxial layer located in the second isolation island to each other;
a third electrode is formed on a second surface of the semiconductor substrate, the first surface and the second surface being opposite to each other.
5. The method of manufacturing a transient voltage suppressor of claim 4, further comprising, after the step of forming a doped region of said first doping type:
forming an insulating layer on the epitaxial layer; and
and forming a plurality of openings on the insulating layer, wherein the doped region, the part of the epitaxial layer, which is positioned on the second isolation island, and part of the isolation island are respectively exposed outside through the openings.
6. The method of claim 4, wherein the first doping type is N-type or P-type and the second doping type is the other of N-type or P-type.
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| CN201710600903.7A CN107293533B (en) | 2017-07-21 | 2017-07-21 | Transient voltage suppressor and method of manufacturing the same |
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| US10573635B2 (en) * | 2018-07-23 | 2020-02-25 | Amazing Microelectronics Corp. | Transient voltage suppression device with improved electrostatic discharge (ESD) robustness |
| CN109192724B (en) * | 2018-09-18 | 2020-08-28 | 南京溧水高新创业投资管理有限公司 | Semiconductor device and method for manufacturing the same |
| CN109659232A (en) * | 2018-12-11 | 2019-04-19 | 江南大学 | A kind of plane bidirectional trigger diode and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856318A (en) * | 2011-06-28 | 2013-01-02 | 万国半导体股份有限公司 | Uni-directional transient voltage suppressor |
| CN105185783A (en) * | 2015-08-20 | 2015-12-23 | 北京燕东微电子有限公司 | Capacitive diode assembly and manufacturing method of the capacitive diode assembly |
| CN105185782A (en) * | 2015-08-20 | 2015-12-23 | 北京燕东微电子有限公司 | Capacitive diode assembly and manufacturing method of the capacitive diode assembly |
| CN106449634A (en) * | 2016-09-23 | 2017-02-22 | 矽力杰半导体技术(杭州)有限公司 | Transient voltage suppressor and manufacturing method therefor |
| CN207068844U (en) * | 2017-07-21 | 2018-03-02 | 北京燕东微电子有限公司 | Transient voltage suppressor |
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| CN102856318A (en) * | 2011-06-28 | 2013-01-02 | 万国半导体股份有限公司 | Uni-directional transient voltage suppressor |
| CN105185783A (en) * | 2015-08-20 | 2015-12-23 | 北京燕东微电子有限公司 | Capacitive diode assembly and manufacturing method of the capacitive diode assembly |
| CN105185782A (en) * | 2015-08-20 | 2015-12-23 | 北京燕东微电子有限公司 | Capacitive diode assembly and manufacturing method of the capacitive diode assembly |
| CN106449634A (en) * | 2016-09-23 | 2017-02-22 | 矽力杰半导体技术(杭州)有限公司 | Transient voltage suppressor and manufacturing method therefor |
| CN207068844U (en) * | 2017-07-21 | 2018-03-02 | 北京燕东微电子有限公司 | Transient voltage suppressor |
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