CN108198813B - Transient voltage suppressor and method of manufacturing the same - Google Patents
Transient voltage suppressor and method of manufacturing the same Download PDFInfo
- Publication number
- CN108198813B CN108198813B CN201810146821.4A CN201810146821A CN108198813B CN 108198813 B CN108198813 B CN 108198813B CN 201810146821 A CN201810146821 A CN 201810146821A CN 108198813 B CN108198813 B CN 108198813B
- Authority
- CN
- China
- Prior art keywords
- epitaxial layer
- layer
- isolation
- semiconductor substrate
- well region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001052 transient effect Effects 0.000 title claims abstract description 101
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000002955 isolation Methods 0.000 claims abstract description 167
- 239000004065 semiconductor Substances 0.000 claims abstract description 104
- 239000000758 substrate Substances 0.000 claims abstract description 94
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims 1
- 230000002457 bidirectional effect Effects 0.000 abstract description 12
- 230000001629 suppression Effects 0.000 abstract description 6
- 239000002019 doping agent Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 17
- 238000010586 diagram Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 8
- 230000002441 reversible effect Effects 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- PMRMTSSYYVAROU-UHFFFAOYSA-N [Ti].[Ni].[Au] Chemical compound [Ti].[Ni].[Au] PMRMTSSYYVAROU-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- -1 aluminum silicon copper Chemical compound 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- MZFIXCCGFYSQSS-UHFFFAOYSA-N silver titanium Chemical compound [Ti].[Ag] MZFIXCCGFYSQSS-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a transient voltage suppressor and a manufacturing method thereof, wherein the transient voltage suppressor comprises: a second epitaxial layer on the semiconductor substrate and the first surface thereof; a first buried layer extending into the semiconductor substrate; a second buried layer in which the first portion extends into the semiconductor substrate and the second portion extends into the first buried layer; a first isolation region extending into the second epitaxial layer to define a first isolation island and a second isolation island; a second isolation region extending into the second epitaxial layer, the first portion defining a third isolation island within the first isolation island, the second portion being connected to the first portion of the second buried layer; the first well region extends into the third isolation island in part and is connected with the first buried layer through the first isolation region in the other part; and a second well region extending into the second isolation island and electrically connected to the first portion of the first well region. The transient voltage suppressor provided by the invention has the function of bidirectional transient voltage suppression, has low capacitance and small volume, is simple to manufacture, and can respectively lead out electrodes from the front surface and the back surface.
Description
Technical Field
The invention relates to the technical field of semiconductor microelectronics, in particular to a transient voltage suppressor and a manufacturing method thereof.
Background
The transient voltage suppressor (Transient Voltage Suppressor, TVS) is a high performance circuit protection device that is currently in general use, and has a shape that is not different from a conventional diode, but is designed with a specific structure and process that enables it to absorb up to thousands of watts of surge power. The transient voltage suppressor operates by: under reverse application conditions, when the transient voltage suppressor is subjected to a high-energy large pulse, the working impedance of the transient voltage suppressor is quickly reduced to a very low conduction value, so that a large current is allowed to flow, and the voltage is clamped at a preset level, and the response time is only 10 generally -12 Second, therefore, the precise components in the electronic circuit can be effectively protected from being damaged by various surge pulses。
Compared with a unidirectional transient voltage suppressor which can only protect a circuit in a single direction, the bidirectional transient voltage suppressor meets the characteristic of conforming to a basically symmetrical conventional electrical I-V curve in the forward direction and the reverse direction, so that in practical application, the two directions of the circuit can be protected at the same time, and the application range is wider.
The market of consumer electronics is rapidly developing, the performance of electronic products represented by mobile phones and mobile terminals is continuously improved, the mobile phones or mobile terminals and the like have higher requirements on reaction speed and transmission speed, and the ultralow capacitance smaller than 1pF is a hard index which needs to be met by the transient voltage suppressor.
Prior art bi-directional transient voltage suppressors are typically constructed of a longitudinal NPN or PNP structure. Fig. 1a is a schematic diagram of a prior art bi-directional transient voltage suppressor having a longitudinal PNP structure, and fig. 1b is a schematic diagram of a prior art bi-directional transient voltage suppressor having a longitudinal NPN structure. Although the transient voltage suppressor shown in fig. 1a and 1b can achieve larger power and better voltage symmetry, and has low cost and simple process, the bidirectional transient voltage suppressor with the structure has larger capacitance and can not meet the requirements of the current market on the transient voltage suppressor.
Fig. 2a shows a schematic diagram of a prior art bi-directional transient voltage suppressor packaged in series with two sets of unidirectional low capacitance chips. To implement a bi-directional transient voltage suppressor, two separate sets of unidirectional transient voltage suppressors of exactly the same performance may be connected in series in the manner shown in fig. 3 to implement a bi-directional transient voltage suppressor with a smaller capacitance. However, the two-way transient voltage suppressors need to be packaged in series, so that the cost is high, and for smaller packages, the two sets of one-way transient voltage suppressors cannot be packaged at the same time, and the difficulty in the process is increased.
Fig. 2b shows a schematic diagram of a two-channel unidirectional low capacitance transient voltage suppressor of the prior art. As shown in fig. 2b, since the two channel ends of the two-channel unidirectional low-capacitance transient voltage suppressor are completely symmetrical, the two channel ends of the two-channel unidirectional low-capacitance transient voltage suppressor can be directly led out to realize bidirectional low-capacitance transient voltage suppression. However, in this application, since two channel ends of the two-channel unidirectional low-capacitance transient voltage suppressor must be simultaneously led out from the front surface, the chip area may be increased, which is not suitable for a smaller package; meanwhile, since two channel ends of the two-channel unidirectional transient voltage suppressor must be wired to draw out the two channel ends during the packaging process, the manufacturing cost is increased.
Fig. 2c shows a schematic diagram of a prior art bi-directional tvs integrated with multiple independent rectifying diodes and a common tvs package. As shown in fig. 2c, 2 chips need to be placed on the base island in the bi-directional transient voltage suppressor, so that the probability of occurrence of packaging defects is easily increased, and the cost of chip mounting is high; in the packaging process, two channel ends are required to be respectively provided with a metal wire, so that the cost is increased; meanwhile, because the integrated package of a plurality of chips requires a larger space, the whole bidirectional transient voltage suppressor has a larger size and is not suitable for a smaller package.
Thus, there is a need for a new bi-directional transient voltage suppressor that incorporates a low capacitance design and is capable of extracting electrodes from both sides.
Disclosure of Invention
In order to solve the problems in the prior art, the present invention provides a transient voltage suppressor and a manufacturing method thereof, so as to meet the market requirements of low cost, low capacitance, bidirectional transient voltage suppression, small-volume packaging, and a structure capable of respectively extracting electrodes from the front and back surfaces.
According to an aspect of the present invention, there is provided a transient voltage suppressor, comprising: a semiconductor substrate of a first doping type, which is led out as a second electrode; a second epitaxial layer of the first doping type disposed over the first surface of the semiconductor substrate; a first buried layer of a second doping type extending from a first surface of the semiconductor substrate into the semiconductor substrate, the first buried layer comprising a first portion and a second portion; a second buried layer of a first doping type, comprising a first portion extending inwardly of the semiconductor substrate from a first surface of the semiconductor substrate and a second portion extending inwardly of the first buried layer from the first portion of the first buried layer; a first isolation region of a second doping type extending from the upper surface of the second epitaxial layer into the second epitaxial layer, a portion of the first isolation region being connected to a first portion of the first buried layer to define a first isolation island within the second epitaxial layer, another portion of the first isolation region being connected to a second portion of the first buried layer to define a second isolation island within the second epitaxial layer; a second isolation region of the first doping type extending from the upper surface of the second epitaxial layer into the second epitaxial layer, a portion of the second isolation region being connected to a second portion of the second buried layer to define a third isolation island of the second epitaxial layer within the first isolation island, another portion of the second isolation region being connected to the first portion of the second buried layer; a first well region of a second doping type, the first well region including a first portion and a second portion, the first portion of the first well region extending from the upper surface of the second epitaxial layer into the third isolation island, the second portion of the first well region extending from the upper surface of the second epitaxial layer into the second epitaxial layer and electrically connecting the first portion of the first buried layer and the second portion of the first buried layer through the first isolation region, the second portion of the first well region being in contact with the second portion of the second isolation region; and a second well region of the first doping type extending from the upper surface of the second epitaxial layer into the second isolation island, the second well region being electrically connected to the first portion of the first well region and being extracted as a first electrode.
Preferably, the first portion of the second buried layer is located between the first portion and the second portion of the first buried layer.
Preferably, the second isolation region extends from the upper surface of the second epitaxial layer into the second epitaxial layer along the contact surface between the first isolation island and the first isolation region to form the third isolation island.
Preferably, the transient voltage suppressor further comprises a metal layer disposed on a second surface of the semiconductor substrate, the first surface and the second surface of the semiconductor substrate being opposite to each other.
Preferably, the transient voltage suppressor further comprises: the insulating layer is positioned on the upper surface of the second epitaxial layer, and contact holes are formed in the first part of the first well region and the corresponding positions of the second well region; and the electrode lead is used for electrically connecting the first part of the first well region with the second well region through the contact hole so as to lead out the first electrode.
Preferably, the first surface of the semiconductor substrate is pre-grown with a first epitaxial layer of a first doping type, and the first epitaxial layer serves as a sacrificial layer.
Preferably, the resistivity of the semiconductor substrate is less than 0.02 Ω·cm, and the resistivity of the first epitaxial layer is not less than 0.1 Ω·cm.
Preferably, the doping concentration of the second epitaxial layer is smaller than the doping concentration of the first epitaxial layer.
Preferably, the thickness of the first epitaxial layer is not less than 3 μm and the thickness of the second epitaxial layer is not less than 5 μm.
Preferably, the implantation dosage of the first buried layer is not less than E14cm -2 The doping concentration of the second buried layer is not less than E19cm -3 The doping concentration of the first isolation region is not less than E18cm -3 The doping concentration of the second isolation region is not less than E18cm -3 The doping concentration of the first well region is not less than E19cm -3 The implantation dosage of the second well region is not less than E14cm -2 On the order of magnitude.
Preferably, the first doping type is N-type or P-type, and the second doping type is the other of N-type or P-type.
According to another aspect of the present invention, there is also provided a method of manufacturing a transient voltage suppressor, including: providing a semiconductor substrate; forming a first buried layer of a second doping type, the first buried layer extending from a first surface of the semiconductor substrate into the semiconductor substrate, the first buried layer including a first portion and a second portion; forming a second buried layer of a first doping type, the second buried layer including a first portion and a second portion, the first portion of the second buried layer extending from the first surface of the semiconductor substrate into the semiconductor substrate, the second portion of the second buried layer extending from the first portion of the first buried layer into the first buried layer; forming a second epitaxial layer of the first doping type over the first surface of the semiconductor substrate of the first doping type; forming a first isolation region of a second doping type, the first isolation region extending from the upper surface of the second epitaxial layer into the second epitaxial layer, a portion of the first isolation region being connected to a first portion of the first buried layer to define a first isolation island within the second epitaxial layer, another portion of the first isolation region being connected to a second portion of the first buried layer to define a second isolation island within the second epitaxial layer; forming a second isolation region of the first doping type, the second isolation region extending from the upper surface of the second epitaxial layer into the second epitaxial layer, a portion of the second isolation region being connected to a second portion of the second buried layer to define a third isolation island of the second epitaxial layer within the first isolation island, another portion of the second isolation region being connected to the first portion of the second buried layer; forming a first well region of a second doping type, the first well region including a first portion and a second portion, the first portion of the first well region extending from the upper surface of the second epitaxial layer into the third isolation island, the second portion of the first well region extending from the upper surface of the second epitaxial layer into the second epitaxial layer and electrically connecting the first portion of the first buried layer and the second portion of the first buried layer through the first isolation region, the second portion of the first well region being in contact with the second portion of the second isolation region; and forming a second well region of the first doping type extending from the upper surface of the second epitaxial layer into the second isolation island, the second well region being electrically connected to the first portion of the first well region; extracting a first portion of the first well region and the second well region as the first electrode; and extracting the semiconductor substrate as a second electrode.
Preferably, the first portion of the second buried layer is formed between the first portion and the second portion of the first buried layer.
Preferably, the second isolation region extends from the upper surface of the second epitaxial layer into the second epitaxial layer, and the step of defining a third isolation island of the second epitaxial layer within the first isolation island with the second portion of the second buried layer includes: the second isolation region extends from a top surface of the second epitaxial layer into the second epitaxial layer along a contact surface between the first isolation island and the first isolation region to form the third isolation island.
Preferably, the step of extracting the semiconductor substrate as the second electrode includes: a metal layer is formed on a second surface of the semiconductor substrate, the first surface and the second surface of the semiconductor substrate being opposite to each other.
Preferably, before the step of forming the metal layer on the second surface of the semiconductor substrate, the method further includes: the semiconductor substrate is thinned from a second surface of the semiconductor substrate.
Preferably, the step of extracting the first portion of the first well region and the second well region as the first electrode comprises: forming an insulating layer on the upper surface of the second epitaxial layer; contact holes are formed in the insulating layer and corresponding positions of the first part of the first well region and the second well region; and electrically connecting the first portion of the first well region and the second well region through the contact hole to lead out the first electrode.
Preferably, the step of providing the semiconductor substrate comprises: and a first epitaxial layer of a first doping type is grown on the first surface of the semiconductor substrate in advance, and the first epitaxial layer is used as a sacrificial layer.
Preferably, the doping concentration of the second epitaxial layer is smaller than the doping concentration of the first epitaxial layer.
Preferably, the first doping type is N-type or P-type, and the second doping type is the other of N-type or P-type.
After the technical scheme of the invention is adopted, the following beneficial effects can be obtained: 1. the low capacitance performance and the bidirectional transient voltage protection function can be realized; 2. the first electrode and the second electrode can be respectively led out from the front surface and the back surface; 3. the semiconductor substrate, the first epitaxial layer and the second epitaxial layer with the same doping type are selected, so that the manufacturing difficulty of the epitaxial layer is reduced, and the stability of the parameters and the performance of the device is ensured; 4. different from the conventional integration scheme that a single chip is used for completing the design and manufacture of a core device on the upper surface of an epitaxial layer, the transient voltage suppressor provided by the invention utilizes the three-dimensional space of the chip to a great extent, and the power device with larger occupied area is manufactured inside the chip, and only some devices with stricter requirements on design rules are placed on the upper surface of the epitaxial layer to complete the manufacture, so that the chip area utilization rate is higher, the integration level is higher, the chip size is further compressed, the packaging cost is reduced, and the industrial advantage is achieved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.
Fig. 1a shows a schematic diagram of a prior art bi-directional transient voltage suppressor having a longitudinal PNP structure.
Fig. 1b shows a schematic diagram of a prior art bi-directional transient voltage suppressor having a longitudinal NPN structure.
Fig. 2a shows a schematic diagram of a prior art bi-directional transient voltage suppressor packaged in series with two sets of unidirectional low capacitance chips.
Fig. 2b shows a schematic diagram of a two-channel unidirectional low capacitance transient voltage suppressor of the prior art.
Fig. 2c shows a schematic diagram of a prior art bi-directional transient voltage suppressor packaged with multiple independent rectifying diodes and a common transient suppression diode.
Fig. 3 shows a circuit diagram of a transient voltage suppressor provided by a first embodiment of the invention.
Fig. 4 shows a schematic view of the volt-ampere characteristic of the transient voltage suppressor of fig. 3.
Fig. 5 shows a partial block diagram of the transient voltage suppressor of fig. 3.
Fig. 6a to 6j show schematic cross-sectional views of various stages of a method of manufacturing a transient voltage suppressor according to a first embodiment of the invention.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of embodiments of the invention, certain specific details are set forth in order to provide a thorough understanding of the invention. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the invention.
Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings. The flowcharts, block diagrams in the figures illustrate the possible architecture, functionality, and operation of systems, methods, devices according to embodiments of the present invention, and the order of the blocks in the figures are merely for better illustrating the processes and steps of the embodiments, and should not be taken as limiting the invention itself.
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.
If, for the purposes of describing a situation directly on top of another layer, another region, the expression "a directly on top of B" or "a directly on top of B and adjoining it" will be used herein. In this application, "a is directly in B" means that a is in B and a is directly adjacent to B, rather than a being in the doped region formed in B.
In this application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed.
Numerous specific details of the invention, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 3 shows a circuit diagram of a transient voltage suppressor provided by a first embodiment of the invention.
The TVS device 100 according to the first embodiment of the present invention is a bidirectional TVS device, and has a bidirectional suppression equivalent circuit therein as shown in fig. 3, where the bidirectional suppression equivalent circuit includes a first rectifying diode D1, a second rectifying diode D2, a third rectifying diode D3, a first transient voltage suppressing diode T1, and a second transient voltage suppressing diode T2, where the anode of the first rectifying diode D1 is connected to the cathode of the second rectifying diode D2 to serve as a first electrode P1 (e.g., located on the front surface of the package of the TVS device 100), the cathode of the second transient voltage suppressing diode T2 is connected to the cathode of the third rectifying diode D3 to serve as a second electrode P2 (e.g., located on the back surface of the package of the TVS device 100), the anode of the second transient voltage suppressing diode T2 is connected to the anode of the second rectifying diode D2, and the anode of the third rectifying diode D3 is connected to the anode of the first transient voltage suppressing diode T1, and the cathode of the first transient voltage suppressing diode T1 is connected to the cathode of the first rectifying diode D1.
Fig. 4 shows a schematic view of the volt-ampere characteristic of the transient voltage suppressor of fig. 3. Wherein the abscissa represents the voltage between the first and second electrodes of the transient voltage suppressor and the ordinate represents the current flowing from the first electrode to the second electrode through the transient voltage suppressor 100.
As can be seen from fig. 4, when the reverse voltage between the first electrode P1 and the second electrode P2 of the transient voltage suppressor 100 exceeds a certain threshold value, the transient voltage suppressor 100 can instantaneously conduct a large current so that the voltage of the second electrode is clamped to a predetermined level; when the forward voltage between the first electrode P1 and the second electrode P2 of the transient voltage suppressor 100 exceeds a certain threshold, the transient voltage suppressor 100 can instantaneously conduct a large current so that the voltage of the first electrode is clamped to a predetermined level.
Specifically, as can be seen in conjunction with fig. 3, when a surge occurs: the second rectifying diode D2 is turned on if a negative voltage is applied between the first electrode P1 and the second electrode P2, the second tvs diode T2 is subjected to a reverse voltage, and if the reverse voltage has a value higher than a breakdown voltage of the second tvs diode T2, an operating impedance of the second tvs diode T2 can be immediately lowered to a very low value to allow a large current to pass and simultaneously clamp a voltage of the second electrode P2 to a predetermined level, thereby protecting an electronic component connected between the first electrode P1 and the second electrode P2; if a positive voltage is applied between the first electrode P1 and the second electrode P2, the first rectifying diode D1 and the third rectifying diode D3 are turned on, the first transient voltage suppressing diode T1 is subjected to a reverse voltage, and if the reverse voltage has a value higher than the breakdown voltage of the first transient voltage suppressing diode T1, the operating impedance of the first transient voltage suppressing diode T1 can be immediately reduced to a very low value to allow a large current to pass, and simultaneously the voltage of the first electrode P1 is clamped to a predetermined level to protect an electronic component connected between the first electrode P1 and the second electrode P2, thereby realizing a bidirectional transient voltage suppressing function.
Fig. 5 shows a partial block diagram of the transient voltage suppressor of fig. 3.
In the following description, the doping type of the semiconductor material will be described as being specifically one of P-type and N-type. It will be appreciated that semiconductor devices of the same function can also be obtained if the doping type of the respective semiconductor material is reversed.
As shown in fig. 5, the tvs 100 includes a first electrode P1, a second electrode P2, a semiconductor substrate 101, a first epitaxial layer on a first surface of the semiconductor substrate 101, a first buried layer 103, a second buried layer 104, a second epitaxial layer 105 on the first epitaxial layer, a first isolation region 106, a second isolation region 107, a first well region 108, and a second well region 109.
The semiconductor substrate 101 is, for example, a heavily doped N-type semiconductor substrate, and in order to form a P-type or N-type semiconductor layer or region, a corresponding type of dopant may be doped in the semiconductor layer or region. For example, the P-type dopant includes boron and the N-type dopant includes phosphorus or arsenic or antimony.
In this embodiment, the semiconductor substrate 101 is a heavily doped N-type substrate having a resistivity of less than 0.02 Ω·cm, and the dopant is arsenic (As). The second electrode P2 is located, for example, on a second surface of the semiconductor substrate 101, the first surface and the second surface of the semiconductor substrate 101 being opposite to each other.
The first epitaxial layer is a lightly doped N-type epitaxial layer grown on the first surface of the semiconductor substrate 101, having a resistivity of not less than 0.1 Ω·cm and a thickness of not less than 3 μm, and is used as a sacrificial layer on the first surface of the semiconductor substrate 101, which will eventually be back-diffused and compensated for by the semiconductor substrate 101, so that a description of the first epitaxial layer will be omitted in the following partial description.
The first buried layer 103 is, for example, a P-type buried layer. Implanting a dose of not less than E14cm from the first surface of the semiconductor substrate 101 through the sacrificial layer -2 An order of magnitude dopant (e.g., boron) and annealed to form the first buried layer 103. The first buried layer 103 includes a first portion and a second portion.
The second buried layer 104 has a doping concentration of not less than E19cm -3 Order of magnitude ofIs a heavily doped region of N type. The second buried layer 104 includes a first portion and a second portion, the first portion of the second buried layer 104 extending from the first epitaxial layer into the semiconductor substrate 101, the second portion of the second buried layer 104 being formed in the first portion of the first buried layer 103 to form a PN junction with the first portion of the first buried layer 103. In the tvs 100, the first portion of the second buried layer 104 forms a low-resistance conductive path with the semiconductor substrate 101.
The second epitaxial layer 105 is, for example, an N-type lightly doped region grown over the first surface of the N-type heavily doped semiconductor substrate 101, which covers the second buried layer 104, the first buried layer 103, and the first epitaxial layer, and has a resistivity of not less than 5Ω·cm, and a thickness of not less than 5 μm. The resistivity and thickness of the second epitaxial layer 105 will determine the electrical performance of the tvs 100, and can be freely adjusted by those skilled in the art according to the application requirements in practical implementation.
The first isolation region 106 is, for example, a P-type isolation region with a doping concentration not less than E18cm -3 The dopant is, for example, boron. The first isolation region 106 extends from the upper surface of the second epitaxial layer 105 into the second epitaxial layer 105, and further extends along with the subsequent high temperature process in the direction of the semiconductor substrate 101, and finally passes through the second epitaxial layer 105 in the tvs 100 to connect with the first buried layer 103. The first isolation region 106 includes a first portion and a second portion, the first portion of the first isolation region 106 being connected to the first portion of the first buried layer 103 to define a first isolation island in the second epitaxial layer 105; a second portion of the first isolation region 106 is connected to a second portion of the first buried layer 103 to define a second isolation island in the second epitaxial layer 105.
The second isolation region 107 is an N-type isolation region with a doping concentration not less than E18cm -3 An N-type heavily doped region of the order of magnitude, the dopant being, for example, phosphorus. The second isolation region 107 includes a first portion and a second portion, the first portion of the second isolation region 107 extending from the upper surface of the second epitaxial layer into the first isolation island and being connected to the second portion of the second buried layer 104, thereby further defining a third isolation island of the second epitaxial layer within the first isolation island, the third isolation island passing through the second isolationThe first portion of the region is connected to the second portion of the second buried layer 104; the second portion of the second isolation region 107 extends from the surface of the second epitaxial layer 105 and through the second epitaxial layer 105 to connect with the first portion of the second buried layer 104, such that the second portion of the second isolation region 107, the first portion of the second buried layer 104, and the semiconductor substrate 101 form a low-resistance conductive path through the second epitaxial layer 105. Wherein, to form the third isolation island, the first portion of the second isolation region 107 at least partially overlaps with the inner side surface of the first portion of the first isolation region, i.e. the first portion of the second isolation region 107 extends from the upper surface of the second epitaxial layer to the second portion of the second buried layer along the contact surface between the first portion of the first isolation region and the first isolation island to form the third isolation island.
The first well region 108 is, for example, a P-type well region with a doping concentration not less than E18cm -3 An order of magnitude P-type heavily doped region, the dopant being, for example, boron. The first well region 108 includes a first portion and a second portion, the first portion of the first well region 108 extending from the second epitaxial layer 105 into the third isolation island; the second portion of the first well region 108 extends from the surface of the second epitaxial layer 105 into the second epitaxial layer 105 by a depth to connect the first portion and the second portion of the first isolation region 106, so that the first portion of the first well region 108 connects the first portion of the first buried layer 103 and the second portion of the first buried layer 103 through the first isolation region, and the second portion of the first well region 108 contacts the second portion of the second isolation region 107 to form a PN junction.
The second well region 109 is, for example, an N-well region with an implantation dose of not less than E14cm -2 The dopant is, for example, phosphorus. The second well region 109 extends from the surface of the second epitaxial layer 105 into the second isolation island.
Preferably, the tvs 100 further includes an insulating layer covering the surface of the second epi layer 105 and having contact holes at corresponding positions of the first portion of the first well region 108 and the second well region 109, so that the first electrode P1 (for example, an electrode lead) can electrically connect the first portion of the first well region 108 and the second well region 109 through the contact holes and be drawn out.
The insulating layer is made of silicon oxide or silicon nitride, and the first electrode P1 and the second electrode P2 are made of a metal or alloy selected from gold, silver, copper, aluminum silicon copper, titanium silver, titanium nickel gold, or the like.
In the transient voltage suppressor 100 shown in fig. 5, corresponding to fig. 3, the semiconductor substrate 101 is connected to the second electrode P2 as the cathode of the third rectifying diode D3, the first buried layer 103 is the anode of the third rectifying diode D3, the first portion of the first buried layer 103 is the anode of the first transient voltage suppressing diode T1, and the second portion of the second buried layer 104 is the cathode of the first transient voltage suppressing diode T1.
A first portion of the first well region 108 extends from the second epitaxial layer 105 into a third isolation island to serve as an anode of the first rectifying diode D1, the third isolation island serving as a cathode of the first rectifying diode D1 being connected to a second portion of the second buried layer 104 serving as a cathode of the first transient voltage suppressing diode T1 through the first portion of the second isolation region 107.
The second portion of the second isolation region 107, the first portion of the second buried layer 104 and the semiconductor substrate 101 form a low-resistance conductive path penetrating the second epitaxial layer 105 to serve as a cathode of the second tvs T2 together, and the second portion of the first well region 108 serves as an anode of the second tvs T2, so that the second portion of the first well region 108 and the second portion of the second isolation region 107 form the second tvs T2 of the subsurface diode structure. Due to the concentration effect, the breakdown interface of the PN junction of the second tvs T2 only includes the interface region between the second portion of the first well region 108 and the second portion of the second isolation region 107 (because the doping concentration of the second epitaxial layer 105 is low, surface breakdown is avoided in the interface region between the second portion of the first well region 108 and the second epitaxial layer 105).
The second portion of the first isolation region 106 and the second portion of the first buried layer 103 together form an anode of the second rectifying diode D2, and the second well region 109 extends from the surface of the second epitaxial layer 105 into the second isolation island to serve as a cathode of the second rectifying diode D2. Since the second portion of the first well region 108 connects the first portion and the second portion for the first isolation region 106, the anode of the second rectifying diode D2 is connected to the anode of the second tvs diode T2.
The first electrode P1 electrically connects and leads out the second well region 109 and the first portion of the first well region 108, thereby realizing a connection between the anode of the first rectifying diode D1 and the cathode of the second rectifying diode D2.
Fig. 6a to 6j show schematic cross-sectional views of various stages of a method of manufacturing a transient voltage suppressor according to a first embodiment of the invention.
As shown in fig. 6a, an N-type first epitaxial layer is formed on a first surface of an N-type semiconductor substrate 101 as a sacrificial layer on the first surface of the semiconductor substrate 101.
To form a P-type or N-type semiconductor layer or region, the semiconductor layer and region may be doped with a corresponding type of dopant, e.g., a P-type dopant including boron and an N-type dopant including phosphorus or arsenic or antimony. In this embodiment, the semiconductor substrate 101 is a heavily doped N-type substrate having a resistivity of less than 0.02 Ω·cm, and the dopant is arsenic (As).
The thickness of the first epitaxial layer is not less than 3 μm and the resistivity is not less than 0.1 Ω·cm, and eventually the first epitaxial layer will be back-diffused by the semiconductor substrate 101 and be depleted.
The first epitaxial layer may be formed using known deposition processes. For example, the deposition process may be one selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering.
As shown in fig. 6b, a first buried layer of P-type is formed in the semiconductor substrate 101 via the first epitaxial layer. The first buried layer includes at least a first portion 103a and a second portion 103b.
For example, a dose of not less than E14cm is implanted from the first surface of the semiconductor substrate 101 through the first epitaxial layer -2 An order of magnitude dopant (e.g., boron) and annealed to form a first buried layer in the semiconductor substrate 101. In practical implementation, a person skilled in the art can freely adjust the doping concentration and the junction depth of the first buried layer according to the application requirement.
As shown in fig. 6c, an N-type second buried layer is formed. The second buried layer has a small doping concentrationAt E19cm -3 An order of magnitude N-type heavily doped region comprising a first portion 104a and a second portion 104b. A first portion 104a of the second buried layer extends from the first epitaxial layer into the semiconductor substrate 101, and a second portion 104b of the second buried layer is formed in the first portion 103a of the first buried layer to form a PN junction with the first portion 103a of the first buried layer. The first portion 104a of the second buried layer forms a low-resistance conductive path with the semiconductor substrate 101.
As shown in fig. 6d, an N-type second epitaxial layer 105 is formed to cover the first epitaxial layer, the first buried layer, and the second buried layer. The second epitaxial layer 105 is, for example, an N-type lightly doped region having a resistivity of not less than 5Ω·cm and a thickness of not less than 5 μm. The resistivity and thickness of the second epitaxial layer 105 will determine the operating voltage and electrical performance of the tvs 100, and can be freely adjusted by those skilled in the art according to the application requirements in practical implementation.
The second epitaxial layer 105 may be formed using known deposition processes. For example, the deposition process may be one selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering.
As shown in fig. 6e, a P-type first isolation region is formed, which extends from the upper surface of the second epitaxial layer 105 into the second epitaxial layer 105, and further extends along with the subsequent high temperature process in the direction of the semiconductor substrate 101, and finally passes through the second epitaxial layer 105 to connect with the first buried layer.
The doping concentration of the first isolation region is not less than E18cm -3 The dopant is, for example, boron.
The first isolation region includes a first portion 106a and a second portion 106b, wherein the first portion 106a of the first isolation region is connected to the first portion 103a of the first buried layer to define a first isolation island 105a in the second epitaxial layer 105, and the second portion 106b of the first isolation region is connected to the second portion 103b of the first buried layer to define a second isolation island 105b in the second epitaxial layer 105.
As shown in fig. 6f, a second isolation region of N-type is formed. The second isolation region has a doping concentration of not less than E18cm -3 An N-type heavily doped region of the order of magnitude, the dopant being, for example, phosphorus.
The second isolation region includes a first portion 107a and a second portion 107b, the first portion 107a of the second isolation region extending from the upper surface of the second epitaxial layer 105 into the first isolation island 105a and being connected to the second portion 104b of the second buried layer, thereby further defining a third isolation island 105c of the second epitaxial layer 105 within the second isolation island, the third isolation island 105c being electrically connected to the second portion 104b of the second buried layer through the first portion 107a of the second isolation region; the second portion 107b of the second isolation region extends from the upper surface of the second epitaxial layer 105 and through the second epitaxial layer 105 to connect with the first portion 104a of the second buried layer, such that the second portion 107b of the second isolation region, the first portion 104a of the second buried layer, and the semiconductor substrate 101 form a low resistance conductive path through the second epitaxial layer 105. Wherein, to form the third isolation island 105c, the first portion 107a of the second isolation region at least partially overlaps with an inner side surface of the first portion 106a of the first isolation region, i.e., the first portion 107a of the second isolation region extends from an upper surface of the second epitaxial layer 105 to the second portion 104b of the second buried layer along a contact surface between the first portion 106a of the first isolation region and the first isolation island 105a to form the third isolation island 105c.
As shown in fig. 6g, a P-type first well region is formed. The first well region has a doping concentration of not less than E18cm -3 An order of magnitude P-type heavily doped region, the dopant being, for example, boron.
The first well region includes a first portion 108a and a second portion 108b, the first portion 108a of the first well region extending from the upper surface of the second epitaxial layer 105 into the third isolation island 105 c; the second portion 108b of the first well region extends from the surface of the second epitaxial layer 105 into the second epitaxial layer 105 by a depth to connect the first portion 106a and the second portion 106b of the first isolation region, such that the first portion 108a of the first well region connects the first portion 103a of the first buried layer and the second portion 103b of the first buried layer through the first isolation region, and the second portion 108b of the first well region contacts the second portion 107b of the second isolation region to form a PN junction.
As shown in fig. 6h, an N-type second well region 109 is formed. The second well region 109 is for example implanted with a dose not less than E14cm -2 Order of magnitude N-type heavily dopedThe impurity region, the dopant is, for example, phosphorus. The second well region 109 extends from the upper surface of the second epitaxial layer 105 into the second isolation island 105 b.
As shown in fig. 6i, the second well region 109 and the first portion 108a of the first well region are electrically connected with an electrode lead to form a first electrode P1 of the transient voltage suppressor 100, and the semiconductor substrate 101 is connected with a second electrode P2.
As shown in fig. 6j, the second electrode P2 is formed on, for example, a second surface of the semiconductor substrate 101, the first surface of the semiconductor substrate 101 being opposite to the second surface of the semiconductor substrate 101.
Preferably, the thickness of the semiconductor substrate 101 is thinned from the second surface of the semiconductor substrate 101 toward the inside of the semiconductor substrate 101 before connecting the semiconductor substrate 101 with the second electrode P2, so as to reduce the package volume of the tvs 100.
Preferably, the tvs 100 further includes an insulating layer covering the upper surface of the second epi layer 105 and having contact holes at corresponding positions of the first portion 108a of the first well region and the second well region 109, so that the first electrode P1 can electrically connect and draw out the second well region 109 and the first portion 108a of the first well region through the contact holes.
The insulating layer is made of silicon oxide or silicon nitride, and the first electrode P1 and the second electrode P2 are made of a metal or alloy selected from gold, silver, copper, aluminum silicon copper, titanium silver, titanium nickel gold, or the like.
It can be seen that the transient voltage suppressor provided by the embodiment of the invention can be prepared by simple steps, can realize the performance of low capacitance and the function of bidirectional transient voltage protection, and can respectively lead out the first electrode and the second electrode from the front surface and the back surface. By selecting the semiconductor substrate, the first epitaxial layer and the second epitaxial layer with the same doping type, the manufacturing difficulty of the epitaxial layer is reduced, and therefore stability of device parameters and performance is guaranteed. And different from the conventional integration scheme that a single chip finishes the design and manufacture of a core device on the upper surface of an epitaxial layer, the transient voltage suppressor provided by the invention utilizes the three-dimensional space of the chip to a great extent, manufactures a power device with larger occupied area inside the chip, only places some devices with stricter requirements on design rules on the upper surface of the epitaxial layer to finish the manufacture, has higher utilization rate of the chip area and higher integration level, further compresses the chip size, reduces the packaging cost and has industrialized advantages.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (18)
1. A transient voltage suppressor comprising:
a semiconductor substrate of a first doping type, which is led out as a second electrode;
a second epitaxial layer of the first doping type disposed over the first surface of the semiconductor substrate;
a first buried layer of a second doping type extending from a first surface of the semiconductor substrate into the semiconductor substrate, the first buried layer comprising a first portion and a second portion;
a second buried layer of a first doping type, comprising a first portion and a second portion, the first portion of the second buried layer extending from the first surface of the semiconductor substrate into the semiconductor substrate and being located between the first portion and the second portion of the first buried layer; a second portion of the second buried layer extends from the first portion of the first buried layer into the first buried layer;
a first isolation region of a second doping type extending from the upper surface of the second epitaxial layer into the second epitaxial layer, a portion of the first isolation region being connected to a first portion of the first buried layer to define a first isolation island within the second epitaxial layer, another portion of the first isolation region being connected to a second portion of the first buried layer to define a second isolation island within the second epitaxial layer;
A second isolation region of the first doping type extending from the upper surface of the second epitaxial layer into the second epitaxial layer, a portion of the second isolation region being connected to a second portion of the second buried layer to define a third isolation island of the second epitaxial layer within the first isolation island, another portion of the second isolation region being connected to the first portion of the second buried layer;
a first well region of a second doping type, the first well region including a first portion and a second portion, the first portion of the first well region extending from the upper surface of the second epitaxial layer into the third isolation island, the second portion of the first well region extending from the upper surface of the second epitaxial layer into the second epitaxial layer and electrically connecting the first portion of the first buried layer and the second portion of the first buried layer through the first isolation region, the second portion of the first well region being in contact with the second portion of the second isolation region; and
and a second well region of the first doping type extending from the upper surface of the second epitaxial layer into the second isolation island, the second well region being electrically connected to the first portion of the first well region and being extracted as a first electrode.
2. The transient voltage suppressor of claim 1, wherein said second isolation region extends from a top surface of said second epitaxial layer into said second epitaxial layer along a contact surface between said first isolation island and said first isolation region to form said third isolation island.
3. The transient voltage suppressor of claim 1, wherein said transient voltage suppressor further comprises a metal layer,
the metal layer is arranged on a second surface of the semiconductor substrate, and the first surface and the second surface of the semiconductor substrate are opposite to each other.
4. The transient voltage suppressor of claim 1, wherein said transient voltage suppressor further comprises:
the insulating layer is positioned on the upper surface of the second epitaxial layer, and contact holes are formed in the first part of the first well region and the corresponding positions of the second well region;
and the electrode lead is used for electrically connecting the first part of the first well region with the second well region through the contact hole so as to lead out the first electrode.
5. The transient voltage suppressor of claim 1, wherein the first surface of the semiconductor substrate is pre-grown with a first epitaxial layer of a first doping type, the first epitaxial layer acting as a sacrificial layer.
6. The transient voltage suppressor of claim 5, wherein the semiconductor substrate has a resistivity of less than 0.02 Ω -cm and the first epitaxial layer has a resistivity of not less than 0.1 Ω -cm.
7. The transient voltage suppressor of claim 5, wherein the doping concentration of the second epitaxial layer is less than the doping concentration of the first epitaxial layer.
8. The transient voltage suppressor of claim 5, wherein the thickness of the first epitaxial layer is no less than 3 μm and the thickness of the second epitaxial layer is no less than 5 μm.
9. The transient voltage suppressor of claim 1, wherein an implant dose of said first buried layer is not less than E14cm -2 The doping concentration of the second buried layer is not less than E19cm -3 The doping concentration of the first isolation region is not less than E18cm -3 The doping concentration of the second isolation region is not less than E18cm -3 The doping concentration of the first well region is not less than E19cm -3 The implantation dosage of the second well region is not less than E14cm -2 On the order of magnitude.
10. The transient voltage suppressor of claim 1, wherein the first doping type is either N-type or P-type and the second doping type is the other of either N-type or P-type.
11. A method of manufacturing a transient voltage suppressor, comprising:
providing a semiconductor substrate;
forming a first buried layer of a second doping type, the first buried layer extending from a first surface of the semiconductor substrate into the semiconductor substrate, the first buried layer including a first portion and a second portion;
forming a second buried layer of a first doping type, the second buried layer comprising a first portion and a second portion, the first portion of the second buried layer extending from the first surface of the semiconductor substrate into the semiconductor substrate and being located between the first portion and the second portion of the first buried layer; a second portion of the second buried layer extends from the first portion of the first buried layer into the first buried layer;
forming a second epitaxial layer of the first doping type over the first surface of the semiconductor substrate of the first doping type;
forming a first isolation region of a second doping type, the first isolation region extending from the upper surface of the second epitaxial layer into the second epitaxial layer, a portion of the first isolation region being connected to a first portion of the first buried layer to define a first isolation island within the second epitaxial layer, another portion of the first isolation region being connected to a second portion of the first buried layer to define a second isolation island within the second epitaxial layer;
Forming a second isolation region of the first doping type, the second isolation region extending from the upper surface of the second epitaxial layer into the second epitaxial layer, a portion of the second isolation region being connected to a second portion of the second buried layer to define a third isolation island of the second epitaxial layer within the first isolation island, another portion of the second isolation region being connected to the first portion of the second buried layer;
forming a first well region of a second doping type, the first well region including a first portion and a second portion, the first portion of the first well region extending from the upper surface of the second epitaxial layer into the third isolation island, the second portion of the first well region extending from the upper surface of the second epitaxial layer into the second epitaxial layer and electrically connecting the first portion of the first buried layer and the second portion of the first buried layer through the first isolation region, the second portion of the first well region being in contact with the second portion of the second isolation region; and
forming a second well region of the first doping type extending from the upper surface of the second epitaxial layer into the second isolation island, the second well region being electrically connected to a first portion of the first well region;
Extracting a first portion of the first well region and the second well region as a first electrode; and
the semiconductor substrate is led out as a second electrode.
12. The method of fabricating a tvs according to claim 11, wherein the second isolation region extends from a top surface of the second epitaxial layer into the second epitaxial layer, the second isolation region and the second portion of the second buried layer defining a third isolation island of the second epitaxial layer within the first isolation island comprising:
the second isolation region extends from a top surface of the second epitaxial layer into the second epitaxial layer along a contact surface between the first isolation island and the first isolation region to form the third isolation island.
13. The method of manufacturing a transient voltage suppressor of claim 11, wherein the step of extracting said semiconductor substrate as a second electrode comprises:
a metal layer is formed on a second surface of the semiconductor substrate, the first surface and the second surface of the semiconductor substrate being opposite to each other.
14. The method of manufacturing a transient voltage suppressor of claim 13, wherein prior to the step of forming a metal layer on the second surface of the semiconductor substrate, further comprising:
The semiconductor substrate is thinned from a second surface of the semiconductor substrate.
15. The method of manufacturing a transient voltage suppressor of claim 11, wherein the step of extracting the first portion of the first well region and the second well region as the first electrode comprises:
forming an insulating layer on the upper surface of the second epitaxial layer;
contact holes are formed in the insulating layer and corresponding positions of the first part of the first well region and the second well region; and
and electrically connecting the first part of the first well region and the second well region through the contact hole so as to lead out the first electrode.
16. The method of manufacturing a transient voltage suppressor of claim 11, wherein the step of providing said semiconductor substrate comprises:
and a first epitaxial layer of a first doping type is grown on the first surface of the semiconductor substrate in advance, and the first epitaxial layer is used as a sacrificial layer.
17. The method of manufacturing a transient voltage suppressor of claim 16, wherein the doping concentration of said second epitaxial layer is less than the doping concentration of said first epitaxial layer.
18. The method of manufacturing a transient voltage suppressor of claim 11, wherein said first doping type is either N-type or P-type and said second doping type is the other of either N-type or P-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810146821.4A CN108198813B (en) | 2018-02-12 | 2018-02-12 | Transient voltage suppressor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810146821.4A CN108198813B (en) | 2018-02-12 | 2018-02-12 | Transient voltage suppressor and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108198813A CN108198813A (en) | 2018-06-22 |
| CN108198813B true CN108198813B (en) | 2023-05-16 |
Family
ID=62593995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810146821.4A Active CN108198813B (en) | 2018-02-12 | 2018-02-12 | Transient voltage suppressor and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108198813B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261616A (en) * | 2015-09-22 | 2016-01-20 | 矽力杰半导体技术(杭州)有限公司 | Transient voltage suppressor and manufacturing method thereof |
| CN105932023A (en) * | 2016-05-10 | 2016-09-07 | 北京燕东微电子有限公司 | Transient voltage suppressor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8338854B2 (en) * | 2009-03-31 | 2012-12-25 | Alpha And Omega Semiconductor Incorporated | TVS with low capacitance and forward voltage drop with depleted SCR as steering diode |
| US8288839B2 (en) * | 2009-04-30 | 2012-10-16 | Alpha & Omega Semiconductor, Inc. | Transient voltage suppressor having symmetrical breakdown voltages |
| US8431999B2 (en) * | 2011-03-25 | 2013-04-30 | Amazing Microelectronic Corp. | Low capacitance transient voltage suppressor |
-
2018
- 2018-02-12 CN CN201810146821.4A patent/CN108198813B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261616A (en) * | 2015-09-22 | 2016-01-20 | 矽力杰半导体技术(杭州)有限公司 | Transient voltage suppressor and manufacturing method thereof |
| CN105932023A (en) * | 2016-05-10 | 2016-09-07 | 北京燕东微电子有限公司 | Transient voltage suppressor |
Non-Patent Citations (1)
| Title |
|---|
| 杨尊松 ; 王立新 ; 肖超 ; 陆江 ; 李彬鸿 ; .瞬态电压抑制二极管的概述和展望.电子设计工程.(第24期),1-5页. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108198813A (en) | 2018-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9837516B2 (en) | Bi-directional punch-through semiconductor device and manufacturing method thereof | |
| CN105932023B (en) | Transient Voltage Suppressor | |
| US20200243504A1 (en) | Rectification device having a forward pn junction and a reverse schottky barrier formed in an epitaxial semiconductor layer formed over a semiconductor substrate | |
| US20140126091A1 (en) | Protection Device And Related Fabrication Methods | |
| US20150085407A1 (en) | Stacked protection devices and related fabrication methods | |
| CN108198810B (en) | Transient voltage suppressor and method of manufacturing the same | |
| US9502890B2 (en) | Protection device and related fabrication methods | |
| CN106169508B (en) | Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof | |
| EP2827373B1 (en) | Protection device and related fabrication methods | |
| CN106158851B (en) | Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof | |
| CN107293533B (en) | Transient voltage suppressor and method of manufacturing the same | |
| US9129806B2 (en) | Protection device and related fabrication methods | |
| CN108198812B (en) | Transient voltage suppressor and method of manufacturing the same | |
| CN108198811B (en) | Transient voltage suppressor and method of manufacturing the same | |
| CN107706229B (en) | Transient voltage suppressor and method of manufacturing the same | |
| CN107301996B (en) | Transient voltage suppressor and method of manufacturing the same | |
| CN108198813B (en) | Transient voltage suppressor and method of manufacturing the same | |
| CN207165576U (en) | Transient voltage suppressor | |
| CN105932010B (en) | Transient Voltage Suppressor | |
| CN107527907B (en) | Transient voltage suppressor and method of manufacturing the same | |
| CN207834298U (en) | Transient voltage suppressor | |
| CN207834305U (en) | Transient voltage suppressor | |
| US8941959B2 (en) | ESD protection apparatus | |
| CN207068851U (en) | Transient voltage suppressor | |
| CN105185783A (en) | Capacitive diode assembly and manufacturing method of the capacitive diode assembly |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |