CN207165576U - Transient voltage suppressor - Google Patents
Transient voltage suppressor Download PDFInfo
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- CN207165576U CN207165576U CN201721113800.XU CN201721113800U CN207165576U CN 207165576 U CN207165576 U CN 207165576U CN 201721113800 U CN201721113800 U CN 201721113800U CN 207165576 U CN207165576 U CN 207165576U
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Abstract
The utility model discloses Transient Voltage Suppressor, Transient Voltage Suppressor includes：The Semiconductor substrate of first doping type；First epitaxial layer of the first doping type on semiconductor substrate surface；The buried regions of the second doping type in epitaxial layer；Second epitaxial layer of the first doping type on the first epitaxial layer；The first isolated area of the second doping type and the second isolated area of the first doping type extended to respectively from the second epi-layer surface in buried regions the second epitaxial layer of neutralization, the first isolated area and the second isolated area are respectively used to form multiple first isolated islands and multiple second isolated islands in the second epitaxial layer；The first doped region of the first doping type and the second doped region of the second doping type extended to respectively in each first isolated island and each second isolated island from epi-layer surface in the second epitaxial layer, each first doped region are electrically connected with to form multiple signalling channels between corresponding second doped region respectively.
Description
Technical field
Semiconductor microelectronic technology field is the utility model is related to, more particularly, to a kind of Transient Voltage Suppressor.
Background technology
Transient Voltage Suppressor (Transient Voltage Suppressor, TVS) is one kind of universal practicality at present
High-effect circuit brake, its profile are no different with general-purpose diode, but because of its special structure and technological design, can
Absorb up to thousands of watts of surge power.The working mechanism of TVS device is under the conditions of applied in reverse, when bearing a high-energy
Big pulse when, its working impedance can quickly be down to extremely low conduction value, so as to allow high current to flow through, while voltage clamp
In predeterminated level, the in general response time is only 10-12Second, therefore can effectively protect the precision components in electronic circuit
From the damage of various surge pulses.
The market rapid development of consumer electronics, the electronic product performance using mobile phone and mobile terminal as representative constantly carry
Rise, mobile phone or mobile terminal etc. all have higher requirements to reaction speed, transmission speed, and the ultra-low capacitance less than 1pF is TVS device
The rigid index that must meet.But traditional single core piece integrated technique make low-capacitance TVS device be generally applicable to 5V or 5V with
Lower operating voltage.And be applied to more than 5V high working voltages, such as 7.5V, 12V, 15V, 36V etc. TVS device again do not possess it is low
The characteristic of electric capacity.Therefore need to design suitable for a variety of operating voltages and combine the multichannel TVS device of low capacitor design.
To solve this problem, those skilled in the art are generally by the pole of PIN diode forward direction series zener two of low electric capacity
Pipe, then electric capacity PIN diode low with another are in parallel.But the TVS device obtained by such method is, it is necessary to more than two
Chip encapsulation in parallel, and 2 chips are placed on one of Ji Dao, the possibility of encapsulation defect is increased, adds and is packaged into
This.And because the integration packaging of multiple chips requires bigger space, overall dimensions are added, it is more for less packaging body
Group chip can not encapsulate simultaneously.
And in order to realize multichannel TVS device, multiple traditional single base diodes are generally arranged in more logical by prior art
Road, this method is although simple in construction easily to be realized, but due to that can have larger electric capacity inside circuit, therefore this structure is more
The application field of passage TVS device is restricted.
Utility model content
In order to solve the above-mentioned problems of the prior art, the utility model provides a kind of suitable for a variety of operating voltages
The Transient Voltage Suppressor of low electric capacity multichannel, the Transient Voltage Suppressor can compatible low-work voltages and high working voltage.
The utility model provides a kind of Transient Voltage Suppressor, it is characterised in that including：First doping type is partly led
Body substrate；First epitaxial layer of the first doping type on the Semiconductor substrate first surface；Positioned at the epitaxial layer
In the second doping type buried regions, wherein, the first doping type and the second doping type are different；Positioned at first epitaxial layer
On the first doping type the second epitaxial layer；The buried regions is extended to from second epi-layer surface neutralize described the respectively
First isolated area of the second doping type in two epitaxial layers and the second isolated area of the first doping type, first isolated area
It is respectively used to form multiple first isolated islands and multiple second isolated islands in second epitaxial layer with second isolated area；
And it is located in each first isolated island and each second isolated island extends to institute from the epi-layer surface respectively
The first doped region of the first doping type in the second epitaxial layer and the second doped region of the second doping type are stated, wherein, it is each
First doped region is electrically connected with to form multiple signalling channels between corresponding second doped region respectively.
Preferably, in addition to insulating barrier, the insulating barrier are located on second epitaxial layer.
Preferably, in addition to first electrode, the first electrode pass through the insulating barrier by each first doped region
It is electrically connected with corresponding second doped region using the signal end as the corresponding signalling channel.
Preferably, in addition to the second electrode positioned at the Semiconductor substrate second surface, the first surface and described
Second surface is relative to each other.
Preferably, second isolated area surrounds second doped region.
Preferably, the doping concentration of second epitaxial layer is less than the doping concentration of first epitaxial layer.
Preferably, the doping concentration of the buried regions is not less than E17cm-3, the doping concentration of first isolated area is not less than
E18cm-3, the doping concentration of second isolated area is not less than E18cm-3, the implantation dosage of first doped region is not less than
E14cm-2, the doping concentration of second doped region is not less than E18cm-3。
Preferably, the thickness of second epitaxial layer selects not less than 5 μ.
Preferably, first doping type is N-type or p-type, and second doping type is another in N-type or p-type
It is individual.
After the technical solution of the utility model, following beneficial effect can be obtained：As a result of identical doping type
Semiconductor substrate and epitaxial layer, the difficulty of processing of epitaxial layer is reduced, so as to ensure that the stabilization of product parameters and performance.And
The solid space of chip is make use of, the larger power device of footprint area is produced on chip internal, only advises some to design
Then there is the device of tightened up requirement to be placed on epitaxial layer upper surface to complete to make.Chip area utilization rate is higher, and integrated level is higher, core
Chip size is further compressed, and possesses industrialization advantage, and reduce packaging cost.Realize and be applied to a variety of operating voltages
, the Transient Voltage Suppressor of low electric capacity multichannel.
Brief description of the drawings
By the description to the utility model embodiment referring to the drawings, of the present utility model above-mentioned and other mesh
, feature and advantage will be apparent from.
Fig. 1 shows the circuit diagram for the Transient Voltage Suppressor that the utility model first embodiment provides.
Fig. 2 shows the circuit diagram of n=2 Transient Voltage Suppressor in Fig. 1.
Fig. 3 shows the schematic cross-section of n=2 Transient Voltage Suppressor in Fig. 1.
Fig. 3 a to 3j show each of the manufacturing process of the Transient Voltage Suppressor according to the utility model first embodiment
The schematic cross-section in stage.
Fig. 4 shows the circuit diagram of the Transient Voltage Suppressor of the utility model second embodiment.
Embodiment
The utility model is described below based on embodiment, but the utility model is not restricted to these implementations
Example.It is detailed to describe some specific detail sections below in the detailed description of the utility model embodiment, to this area
The description of part can also understand the utility model completely without these details for technical staff.In order to avoid obscuring this practicality
New essence, known process, flow do not describe in detail.
In various figures, identical element, which is adopted, will be referred to by like reference numbers expression.For the sake of clarity, in accompanying drawing
Various pieces are not necessarily to scale.In addition, some known parts may be not shown in figure.Flow chart, frame in accompanying drawing
Figure illustrates possible System Framework, function and the operation of the system of embodiment of the present utility model, device, the square frame of accompanying drawing with
And square frame order is used only to the process and step of preferably diagram embodiment, without should in this, as to utility model in itself
Limitation.
The utility model is more fully described hereinafter with reference to accompanying drawing.In various figures, identical element is using similar
Reference represent.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.Furthermore, it is possible to it is not shown
Some known parts.For brevity, the semiconductor structure that can be obtained described in a width figure after several steps.
It should be appreciated that in the structure of outlines device, it is referred to as when by a floor, a region positioned at another floor, another area
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Other layers or region are also included between individual region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario
Face " or the form of presentation of " A is on B and abuts therewith ".In this application, " A is in B " represents that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to whole half formed in each step of manufacture semiconductor devices
The general designation of conductor structure, including all layers formed or region.
It describe hereinafter many specific details of the present utility model, such as the structure of device, material, size, place
Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand,
The utility model can not be realized according to these specific details.
Fig. 1 shows the circuit diagram for the Transient Voltage Suppressor that the utility model first embodiment provides.Fig. 2 shows n in Fig. 1
The circuit diagram of=2 Transient Voltage Suppressor.
As shown in figure 1, the TVS device 100 that the utility model first embodiment provides is the TVS device of unidirectional multichannel,
Including multiple first rectifying tube D11 to D1n, multiple second rectifying tube D21 to D2n and Zener diode ZD, wherein, Zener two
Anode of the pole pipe ZD anode respectively with each first rectifying tube D11 to D1n is connected, Zener diode ZD negative electrode respectively with respectively
Individual second rectifying tube D21 to D2n negative electrode is connected using as earth terminal GND, the negative electrode of each first rectifying tube respectively with it is corresponding
The anode of second rectifying tube be connected together to a signal end IO, for example, the first rectifying tube D11 negative electrode and second whole
Flow tube D21 anode is connected and forms the first signal end IO1, the first rectifying tube D1n negative electrode and the second rectifying tube D2n anode
It is connected and forms the n-th signal end IOn.Wherein n is the natural number more than or equal to 2.
When surge occurs, if bearing negative voltage, the first rectification between the first signal end IO1 and earth terminal GND
Pipe D11 is turned on, and Zener diode ZD bears backward voltage, if the numerical value of negative voltage is higher than Zener diode ZD breakdown potential
Pressure, then produce along the positive electric currents with Zener diode ZD reverse flows of the first rectifying tube D11, prevent so as to play unidirectional ESD
The effect of shield.If bearing positive voltage between the first signal end IO1 and earth terminal GND, the second rectifying tube D21 conductings.
Similarly, when surge occurs, if bearing negative voltage between the n-th signal end IOn and earth terminal GND, first
Rectifying tube D1n is turned on, and Zener diode ZD bears backward voltage, if the numerical value of negative voltage is higher than Zener diode ZD breakdown
Voltage, then produce along the positive electric currents with Zener diode ZD reverse flows of the first rectifying tube D1n, it is unidirectional so as to also function to
The effect of ESD protection.If bearing positive voltage between the n-th signal end IOn and earth terminal GND, the second rectifying tube D2n is led
It is logical.So as to form the unidirectional TVS device of multichannel.
Fig. 3 shows the part-structure figure of Transient Voltage Suppressor in Fig. 2.In the following description, semiconductor material will be described
The doping type of material is specially one of p-type and N-type.If it is appreciated that inverting the doping type of each semi-conducting material, also may be used
To obtain the semiconductor devices of identical function.The structure of the Transient Voltage Suppressor in Fig. 1 is carried out so that n is equal to 2 as an example below
Explanation.
As shown in Fig. 2 TVS device 100 includes Semiconductor substrate 101, the on the first surface of Semiconductor substrate 101
One epitaxial layer 102, the second epitaxial layer 104 on the first epitaxial layer 102, the buried regions 103 in the first epitaxial layer 102,
The first isolated area 105, the second isolated area 107, the first doped region 109 and the second doped region in the second epitaxial layer 104
108。
Semiconductor substrate 101 is, for example, the N-type semiconductor substrate of heavy doping, in order to form p-type or n type semiconductor layer or area
Domain, the dopant of respective type can be mixed in semiconductor layer or region.For example, P-type dopant includes boron, N type dopant
Including phosphorus or arsenic or antimony.
In this embodiment, Semiconductor substrate 101 is the heavily doped N-type substrate that resistivity is less than 0.02 Ω cm, is adulterated
Agent is arsenic (As).
First epitaxial layer 102 is N-type epitaxy layer, and the second epitaxial layer 104 is that resistivity is not less than 5 Ω cm, and thickness is not
Lightly doped n type epitaxial layer less than 5 μm.Wherein, the resistivity and thickness of the first epitaxial layer 102 and the second epitaxial layer 104 will be certainly
The operating voltage and electric property of the fixed TVS device 100, when actually implementing, those skilled in the art can be according to the need of application
Freely to adjust.
Buried regions 103 is, for example, p type buried layer, and the buried regions 103 is located in the first epitaxial layer 102, and doping concentration is not less than
E17cm-3, dopant is, for example, boron.The doping concentration and junction depth of the buried regions 103 are by the operating voltage of decision TVS device and electrically
Performance, when actually implementing, those skilled in the art can freely adjust according to the needs of application.
First isolated area 105 is, for example, p-type isolated area, and the first isolated area 105 passes through second from the surface of the second epitaxial layer 104
Epitaxial layer 104 is extended in buried regions 103, and for limiting multiple first isolated islands, its doping concentration is not less than E18cm-3, dopant
For example, boron.
Second isolated area 107 is, for example, N-type isolated area, and the second isolated area 107 extends to the from the surface of the second epitaxial layer 104
In two epitaxial layers 104, for limiting multiple second isolated islands, in the present embodiment, the second isolated area 107 is, for example, annular, its
Doping concentration is not less than E18cm-3, dopant is, for example, phosphorus.
First doped region 109 is, for example, n-type doping area.First doped region 109 is in each first isolated island outside second
Prolong the surface of layer 104 to extend in the second epitaxial layer 104, its implantation dosage is not less than E14cm-2, dopant is, for example, phosphorus.
Second doped region 108 is, for example, p-type doped region.Second doped region 108 is in each second isolated island outside second
Prolong the surface of layer 104 to extend in the second epitaxial layer 104, its doping concentration is not less than E18cm-3。
It should be noted that the magnitude relationship of doping concentration is as follows between each n-type doping area：Second epitaxial layer 104<First
Epitaxial layer 102<Second 107 >=Semiconductor substrate of isolated area 101.
Further, TVS device also includes insulating barrier 106, first electrode 110 and second electrode 111.
Insulating barrier 106 is located on the second epitaxial layer 104, and first electrode 110 passes through opening in insulating barrier 106 by each the
One doped region 109 is electrically connected with corresponding second doped region 108 to form multiple signal end IO respectively.Second electrode 111
In the second surface of Semiconductor substrate 101.Insulating barrier 106 is for example made up of silica or silicon nitride, first electrode 110 and
Two electrodes 111 are selected from the metal or alloy such as gold, silver, copper, aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold composition.
Corresponding to Fig. 2, in the TVS device shown in Fig. 3, the first isolated area 105 and buried regions 103 are collectively as the first rectification
Pipe D11 anode, the second epitaxial layer 104 are located at the moon of part as the first rectifying tube D11 and D12 in each first isolated island
Pole, the part that the first isolated area 105, the epitaxial layer 104 of buried regions 103 and second are located in corresponding first isolated island form first
Rectifying tube D11 and D12 PN junction；Anode of the buried regions 103 as Zener diode ZD, the first epitaxial layer 102 is as the pole of Zener two
Pipe ZD negative electrode, the epitaxial layer 102 of buried regions 103 and first form Zener diode ZD PN junction；Second doped region 108 is used as second
Rectifying tube D21 anode, negative electrode of first epitaxial layer 102 as the second rectifying tube D21, the second doped region 108 and the second extension
The part that layer 104 is located in each second isolated island respectively constitutes the second rectifying tube D21 PN junction and the second rectifying tube D22 PN
Knot.Voltage termination ring of second isolated area 107 as the second rectifying tube D21 and D22, first electrode 110 are used as TVS device 100
Signal end IO, earth terminal GND of the second electrode 111 as TVS device.
Fig. 3 a to 3j show each of the manufacturing process of the Transient Voltage Suppressor according to the utility model first embodiment
The sectional view in stage.
As shown in Figure 3 a, N-type Semiconductor substrate 101 first surface formed N-type the first epitaxial layer 102.
In order to form p-type or n type semiconductor layer or region, mixing for respective type can be mixed in semiconductor layer and region
Miscellaneous dose, for example, P-type dopant includes boron, N type dopant includes phosphorus or arsenic or antimony.In this embodiment, Semiconductor substrate 101
It is less than 0.02 Ω cm heavily doped N-type substrate for resistivity, dopant is arsenic (As).
First epitaxial layer 102 can use known depositing technology to be formed.For example, depositing technology can be selected from electron beam
One kind in evaporation, chemical vapor deposition, ald, sputtering.
As shown in Figure 3 b, p type buried layer 103 is formed in the first epitaxial layer 102.
The buried regions 103 is located in the first epitaxial layer 102, and doping concentration is not less than E17cm-3, dopant is, for example, boron.This is buried
The doping concentration and junction depth of layer 103 will determine the operating voltage and electric property of TVS device, when actually implementing, this area skill
Art personnel can freely adjust according to the needs of application.
As shown in Figure 3 c, the second epitaxial layer 104 of N-type is formed on the first epitaxial layer 102.
The resistivity of second epitaxial layer 104 is not less than 5 Ω cm, and thickness is not less than 5 μm.The electricity of second epitaxial layer 104
Resistance rate and thickness will determine the operating voltage and electric property of the TVS device, and when actually implementing, those skilled in the art can root
Freely adjusted according to the needs of application.
Second epitaxial layer 104 can use known depositing technology to be formed.For example, depositing technology can be selected from electron beam
One kind in evaporation, chemical vapor deposition, ald, sputtering.
As shown in Figure 3 d, the first isolated area 105 of p-type is formed in the second epitaxial layer 104, and in the second epitaxial layer 104
Upper formation insulating barrier 106.
The doping concentration of first isolated area 105 is not less than E18cm-3, dopant is, for example, boron.It is being initially formed the first isolation
During area 105, the first isolated area 105 is extended in the second epitaxial layer 104 from the surface of the second epitaxial layer 104, due in successive process
High temperature, the first isolated area 105 will further to the direction of Semiconductor substrate 101 extend, finally extend in buried regions 103, use
In limiting multiple first isolated islands, directly illustrated in Fig. 3 d when completing whole processing procedures, the state of the first isolated area 105.
Insulating barrier 106 is for example made up of silica or silicon nitride, sputtering or thermal oxide can be used to be formed.For example, insulation
Layer 106 is the silicon oxide layer that thermal oxide is formed, and in follow-up doping step, insulating barrier 106 is used as protective layer, and using as
The interlayer insulating film of resulting devices.
As shown in Figure 3 e, the second isolated area 107 of N-type is formed in the second epitaxial layer 104.
Second isolated area 107 is extended in the second epitaxial layer 104 from the surface of the second epitaxial layer 104, for limiting multiple
Two isolated islands, in this embodiment, the second isolated area 107 are, for example, annular, and its doping concentration is not less than E18cm-3, dopant example
Such as it is phosphorus.
As illustrated in figure 3f, the second doped region 108 of multiple p-types is formed in the second epitaxial layer 104.
Second doped region 108 is located in each second isolated island, and the second epitaxial layer is extended to from the surface of the second epitaxial layer 104
In 104, its doping concentration is not less than E18cm-3。
As shown in figure 3g, the first doped region 109 of multiple N-types is formed in the second epitaxial layer 104.
First doped region 109 is located in each first isolated island, and the second epitaxial layer is extended to from the surface of the second epitaxial layer 104
In 104, its implantation dosage is not less than E14cm-2, dopant is, for example, phosphorus.
As illustrated in figure 3h, opening is formed on insulating barrier 106 so that each first doped region 109 and each second doping
Area 108 is exposed outside via corresponding opening.
As shown in figure 3i, multiple first electrodes 110 through insulating barrier 106 are formed, first electrode 110 is respectively by each
One doped region 109 and corresponding second doped region 108 electrically connect using as the TVS device signal end IO (as n=2, signal
End IO includes the first signal end IO1 and secondary signal end IO2).
As shown in Fig. 3 j, second electrode 111 is formed in the second surface of Semiconductor substrate 101, as connecing for the TVS device
Ground terminal GND, first surface and second surface are relative to each other.First electrode 110 and second electrode 111 be selected from gold, silver,
The metal or alloy such as copper, aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold form.
Fig. 4 shows the circuit diagram of the Transient Voltage Suppressor of the utility model second embodiment.
The Transient Voltage Suppressor 200 of the utility model second embodiment suppresses with the transient voltage of above-mentioned first embodiment
Device is essentially identical, and difference is：By taking n=2 as an example, as shown in figure 4, the transient voltage suppression of the utility model second embodiment
Device 200 processed can be used as bidirectional transient voltage suppressor to be applied in hyperbaric environment, i.e., in some cases, the transient voltage
Two signal end IO of suppressor can use respectively as two electrode leads to client of nonpolarity bilateral device.Such as with
One signal end IO1 is as the first feeder ear, and secondary signal end IO2 is as the second feeder ear.When surge occurs for the first signal end IO1
During impact, electric current will flow through rectifying tube D21, Zener diode pipe ZD and rectifying tube D12 successively, and be let out through secondary signal end IO2
Put；And when surge impact occurs for secondary signal end IO2, electric current will flow through rectifying tube D22, Zener diode ZD and first successively
Rectifying tube D11, and released through the first signal end IO1, it is achieved thereby that the bidirectional transient voltage that can be applied to hyperbaric environment presses down
Device processed.
It should be noted that the various embodiments described above essentially describe the transient voltage of n=2 (i.e. comprising two data channel)
Suppressor, but as shown in Figure 1, the Transient Voltage Suppressor of the utility model embodiment can include the signal of more than two
Passage, its structure can be analogized to obtain, will not be repeated here by the structure of above-mentioned two channel instantaneous voltage suppressor.
As can be seen that according to device of the present utility model, can be prepared with easy steps suitable for a variety of operating voltages
Under multichannel one-way low-capacitance Transient Voltage Suppressor.Pass through the Semiconductor substrate and extension from identical doping type
Layer, the manufacture difficulty of epitaxial layer is reduced, so as to ensure that the stabilization of device parameters and performance.It is and more different from conventional single-chip
The Integrated Solution of design and the making of core devices is completed in the upper surface of epitaxial layer, according to device of the present utility model very great Cheng
The solid space of chip is make use of on degree, the larger power device of footprint area is produced on chip internal, only sets some pairs
The device that meter rule has tightened up requirement is placed on epitaxial layer upper surface and completes to make, and chip area utilization rate is higher, and integrated level is more
Height, chip size are further compressed, and reduce packaging cost, possess industrialization advantage.
It should be noted that herein, such as first and second or the like relational terms are used merely to a reality
Body or operation make a distinction with another entity or operation, and not necessarily require or imply and deposited between these entities or operation
In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Nonexcludability includes, so that process, article or equipment including a series of elements not only include those key elements, and
Also include the other element that is not expressly set out, or also include for this process, article or the intrinsic key element of equipment.
In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that including the key element
Process, other identical element also be present in article or equipment.
According to embodiment of the present utility model as described above, these embodiments do not have all details of detailed descriptionthe,
Also it is only described specific embodiment not limit the utility model.Obviously, as described above, many modification and change can be made
Change.This specification is chosen and specifically describes these embodiments, is to preferably explain that principle of the present utility model and reality should
With so that skilled artisan can repairing using the utility model and on the basis of the utility model well
Change use.The utility model is only limited by claims and its four corner and equivalent.
Claims (9)
- A kind of 1. Transient Voltage Suppressor, it is characterised in that including：The Semiconductor substrate of first doping type；First epitaxial layer of the first doping type on the Semiconductor substrate first surface；The buried regions of the second doping type in the epitaxial layer, wherein, the first doping type and the second doping type are different；Second epitaxial layer of the first doping type on first epitaxial layer；The second doping type extended to respectively from second epi-layer surface in the buried regions neutralization second epitaxial layer The first isolated area and the first doping type the second isolated area, first isolated area and second isolated area are respectively used to Multiple first isolated islands and multiple second isolated islands are formed in second epitaxial layer；AndRespectively institute is extended in each first isolated island and each second isolated island from the epi-layer surface The first doped region of the first doping type in the second epitaxial layer and the second doped region of the second doping type are stated,Wherein, each first doped region is electrically connected with to form multiple letters between corresponding second doped region respectively Number passage.
- 2. Transient Voltage Suppressor according to claim 1, it is characterised in that also including insulating barrier, the insulating barrier position In on second epitaxial layer.
- 3. Transient Voltage Suppressor according to claim 2, it is characterised in that also including first electrode, first electricity Each first doped region and corresponding second doped region are electrically connected with using as correspondingly by pole through the insulating barrier The signalling channel signal end.
- 4. Transient Voltage Suppressor according to claim 1, it is characterised in that also include positioned at the Semiconductor substrate the The second electrode on two surfaces, the first surface and the second surface are relative to each other.
- 5. Transient Voltage Suppressor according to claim 1, it is characterised in that second isolated area surrounds described second Doped region.
- 6. Transient Voltage Suppressor according to claim 1, it is characterised in that the doping concentration of second epitaxial layer is small In the doping concentration of first epitaxial layer.
- 7. Transient Voltage Suppressor according to claim 1, it is characterised in that the doping concentration of the buried regions is not less than E17cm-3, the doping concentration of first isolated area is not less than E18cm-3, the doping concentration of second isolated area is not less than E18cm-3, the implantation dosage of first doped region is not less than E14cm-2, the doping concentration of second doped region is not less than E18cm-3。
- 8. Transient Voltage Suppressor according to claim 1, it is characterised in that the thickness of second epitaxial layer is not less than 5μm。
- 9. Transient Voltage Suppressor according to claim 1, it is characterised in that first doping type is N-type or P Type, second doping type are another in N-type or p-type.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721113800.XU CN207165576U (en) | 2017-08-31 | 2017-08-31 | Transient voltage suppressor |
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| CN201721113800.XU CN207165576U (en) | 2017-08-31 | 2017-08-31 | Transient voltage suppressor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107706229A (en) * | 2017-08-31 | 2018-02-16 | 北京燕东微电子有限公司 | Transient Voltage Suppressor and its manufacture method |
| CN111180421A (en) * | 2020-01-06 | 2020-05-19 | 杰华特微电子（杭州）有限公司 | Transistor structure for electrostatic protection and manufacturing method thereof |
-
2017
- 2017-08-31 CN CN201721113800.XU patent/CN207165576U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107706229A (en) * | 2017-08-31 | 2018-02-16 | 北京燕东微电子有限公司 | Transient Voltage Suppressor and its manufacture method |
| CN107706229B (en) * | 2017-08-31 | 2024-04-09 | 北京燕东微电子有限公司 | Transient voltage suppressor and method of manufacturing the same |
| CN111180421A (en) * | 2020-01-06 | 2020-05-19 | 杰华特微电子（杭州）有限公司 | Transistor structure for electrostatic protection and manufacturing method thereof |
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