CN207353250U - Transient voltage suppressor - Google Patents

Abstract

The utility model discloses a kind of Transient Voltage Suppressor, which includes Semiconductor substrate；The first epitaxial layer on the Semiconductor substrate first surface；Buried regions in epitaxial layer；The second epitaxial layer on the first epitaxial layer；The first isolated area and the second isolated area in buried regions the second epitaxial layer of neutralization are extended to from the second epi-layer surface respectively, the first isolated area and the second isolated area are respectively used to form the first active area and the second active area in the second epitaxial layer；And be located in the first active area and the second active area the first doped region and the second doped region in the second epitaxial layer are extended to from epi-layer surface respectively, wherein, it is electrically connected between the first doped region and the second doped region, substrate is identical with epitaxial layer doping type.The larger power device of footprint area is produced on chip internal by the Transient Voltage Suppressor, is improved chip area utilization rate and integrated level, further be have compressed chip size, reduces packaging cost.

Description

Transient Voltage Suppressor

Technical field

Semiconductor devices and its manufacture method are the utility model is related to, more particularly, to a kind of Transient Voltage Suppressor.

Background technology

((Transient Voltage Suppressor, TVS) is to be used to protect integrated circuit to exempt to Transient Voltage Suppressor The device damaged by overvoltage.Designed integrated circuit is worked in the normal range (NR) of voltage.However, static discharge (Electronic Static Discharge, ESD), the electric fortuitous event such as fast transient and lightning produce it is unpredictable, Uncontrollable high voltage, can cause damage circuit.When this high voltage produces, it is necessary to TVS device protects integrated circuit, Evade these situations that may damage integrated circuit.

The market rapid development of consumer electronics, the electronic product performance using mobile phone and mobile terminal as representative constantly carry Rise, mobile phone or mobile terminal etc. all have higher requirements reaction speed, transmission speed, and the ultra-low capacitance less than 1pF is TVS device The rigid index that must meet.But the low-capacitance TVS that traditional single core piece integrated technique makes is generally applicable to 5V or below 5V works Make voltage.And it is suitable for more than 5V high working voltages, such as the TVS device of 7.5V, 12V, 15V, 36V etc. do not possess low capacitance again Characteristic.

To solve this problem, those skilled in the art are usually by two pole of PIN diode forward direction series zener of low capacitance Pipe, then capacitance PIN diode low with another are in parallel.But the TVS device obtained by such method is, it is necessary to more than two Chip encapsulation in parallel, and 2 chips are placed on one of Ji Dao, the possibility of encapsulation defect is increased, adds and is packaged into This.And since the integration packaging of multiple chips requires the space of bigger, overall dimensions are added, it is more for less packaging body Group chip can not encapsulate at the same time.

Utility model content

In view of this, the purpose of this utility model is to provide a kind of unidirectional transient voltage suppression of low capacitance of Single-Chip Integration Device processed.

In order to solve the above-mentioned technical problem, a kind of Transient Voltage Suppressor is provided according to the utility model, including：First mixes The Semiconductor substrate of miscellany type；First epitaxial layer of the first doping type on the Semiconductor substrate first surface；Position The buried regions of the second doping type in the epitaxial layer, wherein, the first doping type and the second doping type are different；Positioned at institute State the second epitaxial layer of the first doping type on the first epitaxial layer；Respectively described bury is extended to from second epi-layer surface Layer neutralizes the first isolated area of the second doping type and the second isolated area of the first doping type in second epitaxial layer, institute State the first isolated area and second isolated area is respectively used to form the first active area and second in second epitaxial layer and has Source region；And in first active area and second active area described the is extended to from the epi-layer surface respectively First doped region of the first doping type in two epitaxial layers and the second doped region of the second doping type, wherein, described first It is electrically connected between doped region and second doped region.

Preferably, insulating layer is further included, the insulating layer is located on second epitaxial layer.

Preferably, first electrode is further included, the first electrode passes through the insulating layer and first doped region and institute State the electric connection of the second doped region.

Preferably, the second electrode positioned at the Semiconductor substrate second surface is further included, the first surface and described Second surface is relative to each other.

Preferably, second isolated area surrounds second doped region.

Preferably, the doping concentration of second epitaxial layer is less than the doping concentration of first epitaxial layer.

Preferably, the doping concentration of the buried regions is not less than E17cm^-3, the doping concentration of first isolated area is not less than E18cm^-3, the doping concentration of second isolated area is not less than E18cm^-3, the implantation dosage of first doped region is not less than E14cm^-2, the doping concentration of second doped region is not less than E18cm-3.

Preferably, the thickness of second epitaxial layer is not less than 5 μm.

Preferably, first doping type is N-type or p-type, and second doping type is another in N-type or p-type It is a.

After the technical solution of the utility model, following beneficial effect can be obtained：

As a result of the Semiconductor substrate and epitaxial layer of identical doping type, the difficulty of processing of epitaxial layer is reduced, from And it ensure that the stabilization of product parameters and performance.And the solid space of chip is make use of, by the power device that footprint area is larger Chip internal is produced on, some devices for having tightened up requirement to design rule only are placed on epitaxial layer upper surface completes to make. Chip area utilization rate higher, integrated level higher, chip size are further compressed, and possess industrialization advantage, and reduce Packaging cost.

Brief description of the drawings

By the description to utility model embodiment referring to the drawings, the above-mentioned and other purposes of the utility model, Feature and advantage will be apparent from, in the accompanying drawings：

Fig. 1 shows the circuit diagram for the Transient Voltage Suppressor that the utility model first embodiment provides.

Fig. 2 shows the structure chart for the Transient Voltage Suppressor that the utility model first embodiment provides.

Fig. 3 a to 3j show each rank of manufacture method according to the Transient Voltage Suppressor of the utility model first embodiment The sectional view of section.

Embodiment

The utility model is described below based on embodiment, but the utility model is not restricted to these implementations Example.It is detailed to describe some specific detail sections below in the detailed description of the utility model embodiment, to this area The description of part can also understand the utility model completely without these details for technical staff.In order to avoid obscuring this practicality New essence, known method, process, flow do not describe in detail.

In various figures, identical element, which is adopted, will be referred to by like reference numbers expression.For the sake of clarity, in attached drawing Various pieces are not necessarily to scale.In addition, some known parts may be not shown in figure.Flow chart, frame in attached drawing Figure illustrates possible System Framework, function and the operation of the system of the embodiment of the utility model, method, apparatus, attached drawing Square frame and square frame order are used only to the process and step of preferably diagram embodiment, without should be in this, as to utility model The limitation of itself.

Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical element is using similar Reference numeral represent.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to it is not shown Some known parts.For brevity, the semiconductor structure that can be obtained described in a width figure after several steps.

It should be appreciated that in the structure of outlines device, it is known as when by a floor, a region positioned at another floor, another area When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another Layer, another region " following " or " lower section ".

If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario Face " or the form of presentation of " A is on B and abuts therewith ".In this application, " A is in B " represents that A is located in B, and And A and B is abutted directly against, rather than A is located in the doped region formed in B.

In this application, term " semiconductor structure " refers to whole half formed in each step of manufacture semiconductor devices The general designation of conductor structure, including all layers formed or region.

It describe hereinafter many specific details of the utility model, such as the structure of device, material, size, place Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand, The utility model can not be realized according to these specific details.

Fig. 1 shows the circuit diagram for the Transient Voltage Suppressor that the utility model first embodiment provides.

As shown in Figure 1, the TVS device 100 is unidirectional TVS device, including the first rectifying tube D1 of series connection inverting each other and Zener diode ZD, and the second rectifying tube D2 connected in parallel.Wherein, the anode of the first rectifying tube D1 is with Zener diode ZD's Anode connects, and the cathode of the first rectifying tube D1 is connected with the anode of the second rectifying tube D2 and is used as the signal end I/ of the TVS device O, the cathode of Zener diode ZD are connected with the cathode of the second rectifying tube D2 and are used as the ground terminal GND of the TVS device.

When surge occurs, if bearing negative voltage between signal end I/O and ground terminal GND, the first rectifying tube D1 Conducting, Zener diode ZD bear backward voltage, if the numerical value of negative voltage is higher than the breakdown voltage of Zener diode ZD, produce The raw electric current along the first rectifying tube D1 forward directions and Zener diode ZD reverse flows, so as to play the role of unidirectional ESD protection. If bearing positive voltage between signal end I/O and ground terminal GND, the second rectifying tube D2 conductings.

Fig. 2 shows the structure chart for the Transient Voltage Suppressor that the utility model first embodiment provides.Description below In, the doping type by description semi-conducting material is specially one of p-type and N-type.If it is appreciated that invert each semiconductor material The doping type of material, it is also possible to obtain the semiconductor devices of identical function.

As shown in Fig. 2, TVS device 100 includes Semiconductor substrate 101, the on 101 first surface of Semiconductor substrate One epitaxial layer 102, the second epitaxial layer 104 on the first epitaxial layer 102, the buried regions 103 in the first epitaxial layer 102, The first isolated area 105, the second isolated area 107, the first doped region 109 and the second doped region in the second epitaxial layer 104 108。

Semiconductor substrate 101 is, for example, the N-type semiconductor substrate of heavy doping, in order to form p-type or n type semiconductor layer or area Domain, can mix the dopant of respective type in semiconductor layer or region.For example, P-type dopant includes boron, N type dopant Including phosphorus or arsenic or antimony.

In this embodiment, Semiconductor substrate 101 is less than the heavily doped N-type substrate of 0.02 Ω cm, doping for resistivity Agent is arsenic (As).

First epitaxial layer 102 is N-type epitaxy layer, and the second epitaxial layer 104 is not less than 5 Ω cm for resistivity, and thickness is not Lightly doped n type epitaxial layer less than 5 μm.Wherein, the resistivity and thickness of the first epitaxial layer 102 and the second epitaxial layer 104 will be certainly The operating voltage and electric property of the fixed TVS device 100, in actual implementation, those skilled in the art can be according to the need of application Freely to adjust.

Buried regions 103 is, for example, p type buried layer, which is located in the first epitaxial layer 102, and doping concentration is not less than E17cm^-3, dopant is, for example, boron.The doping concentration and junction depth of the buried regions 103 are by the operating voltage of decision TVS device and electrically Performance, in actual implementation, those skilled in the art can freely adjust according to the needs of application.

First isolated area 105 is, for example, p-type isolated area, and the first isolated area 105 passes through second from 104 surface of the second epitaxial layer Epitaxial layer 104 is extended in buried regions 103, and for limiting the first isolated island, its doping concentration is not less than E18cm^-3, dopant is for example For boron.

Second isolated area 107 is, for example, N-type isolated area, and the second isolated area 107 extends to the from 104 surface of the second epitaxial layer In two epitaxial layers 104, for limiting the second isolated island, in the present embodiment, the second isolated area 107 is, for example, annular, it is adulterated Concentration is not less than E18cm^-3, dopant is, for example, phosphorus.

First doped region 109 is, for example, n-type doping area, and the first doped region 109 is in the first isolated island from the second epitaxial layer 104 surfaces are extended in the second epitaxial layer 104, its implantation dosage is not less than E14cm^-2, dopant is, for example, phosphorus.

Second doped region 108 is, for example, p-type doped region, and the second doped region 108 is in the second isolated island from the second epitaxial layer 104 surfaces are extended in the second epitaxial layer 104, its doping concentration is not less than E18cm^-3。

It should be noted that the magnitude relationship of doping concentration is as follows between each n-type doping area：Second epitaxial layer 104<First Epitaxial layer 102<Second 107 >=Semiconductor substrate of isolated area 101.

Further, TVS device further includes insulating layer 106, first electrode 110 and second electrode 111.

Insulating layer 106 is located on the second epitaxial layer 104, and first electrode 110 passes through the opening in insulating layer 106 to be mixed first Miscellaneous 109 and second doped region 108 of area is electrically connected, and second electrode 111 is located at the second surface of Semiconductor substrate 101, the second table Face and first surface are relative to each other.Insulating layer 106 is for example made of silica or silicon nitride, the electricity of first electrode 110 and second Pole 111 is selected from the metal or alloy such as gold, silver, copper, aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold composition.

Corresponding to Fig. 1, in the TVS device shown in Fig. 2, the first isolated area 105 and buried regions 103 are collectively as the first rectification The anode of pipe D1, the second epitaxial layer 104 are located at cathode of the part as the first rectifying tube D1 in the first isolated island, the first isolation The part that area 105,103 and second epitaxial layer 104 of buried regions are located in the first isolated island forms the PN junction of the first rectifying tube D1；Bury 103 anode as Zener diode ZD of layer, cathode of first epitaxial layer 102 as Zener diode ZD, buried regions 103 and first Epitaxial layer 102 forms the PN junction of Zener diode ZD；Anode of second doped region 108 as the second rectifying tube D2, the first extension 102 cathode as the second rectifying tube D2 of layer, the second doped region 108 and the second epitaxial layer 104 are located at the portion in the second isolated island Divide the PN junction for forming the second rectifying tube D2, voltage termination ring of second isolated area 107 as the second rectifying tube D2, first electrode The 110 signal end I/O as TVS device 100, ground terminal GND of the second electrode 111 as TVS device.

Fig. 3 a to 3j show each rank of manufacture method according to the Transient Voltage Suppressor of the utility model first embodiment The sectional view of section.

As shown in Figure 3a, N-type Semiconductor substrate 101 first surface formed N-type the first epitaxial layer 102.

In order to form p-type or n type semiconductor layer or region, mixing for respective type can be mixed in semiconductor layer and region Miscellaneous dose, for example, P-type dopant includes boron, N type dopant includes phosphorus or arsenic or antimony.In this embodiment, Semiconductor substrate 101 It is less than the heavily doped N-type substrate of 0.02 Ω cm for resistivity, dopant is arsenic (As).

First epitaxial layer 102 can be formed using known depositing technology.For example, depositing technology can be selected from electron beam One kind in evaporation, chemical vapor deposition, atomic layer deposition, sputtering.

As shown in Figure 3b, p type buried layer 103 is formed in the first epitaxial layer 102.

The buried regions 103 is located in the first epitaxial layer 102, and doping concentration is not less than E17cm^-3, dopant is, for example, boron.This is buried The doping concentration and junction depth of layer 103 will determine the operating voltage and electric property of TVS device, in actual implementation, this area skill Art personnel can freely adjust according to the needs of application.

As shown in Figure 3c, the second epitaxial layer 104 of N-type is formed on the first epitaxial layer 102.

The resistivity of second epitaxial layer 104 is not less than 5 Ω cm, and thickness is not less than 5 μm.The electricity of second epitaxial layer 104 Resistance rate and thickness will determine the operating voltage and electric property of the TVS device, and in actual implementation, those skilled in the art can root Freely adjusted according to the needs of application.

Second epitaxial layer 104 can be formed using known depositing technology.For example, depositing technology can be selected from electron beam One kind in evaporation, chemical vapor deposition, atomic layer deposition, sputtering.

As shown in Figure 3d, the first isolated area 105 of p-type is formed in the second epitaxial layer 104, and in the second epitaxial layer 104 Upper formation insulating layer 106.

The doping concentration of first isolated area 105 is not less than E18cm^-3, dopant is, for example, boron.It is being initially formed the first isolation During area 105, the first isolated area 105 is extended in the second epitaxial layer 104 from 104 surface of the second epitaxial layer, due in follow-up process High temperature, the first isolated area 105 will further to 101 direction of Semiconductor substrate extend, finally extend in buried regions 103, use In limiting the first isolated island, directly illustrated in Fig. 3 d when completing whole processing procedures, the state of the first isolated area 105.

Insulating layer 106 is for example made of silica or silicon nitride, sputtering or thermal oxide can be used to be formed.For example, insulation Layer 106 is the silicon oxide layer that thermal oxide is formed, and in follow-up doping step, insulating layer 106 is used as protective layer, and using as The interlayer insulating film of resulting devices.

As shown in Figure 3 e, the second isolated area 107 of N-type is formed in the second epitaxial layer 104.

Second isolated area 107 is extended in the second epitaxial layer 104 from 104 surface of the second epitaxial layer, for limit second every Li Island, in this embodiment, the second isolated area 107 are, for example, annular, its doping concentration is not less than E18cm^-3, dopant is, for example, Phosphorus.

As illustrated in figure 3f, the second doped region 108 of p-type is formed in the second epitaxial layer 104.

Second doped region 108 is located in the second isolated island, and the second epitaxial layer 104 is extended to from 104 surface of the second epitaxial layer In, its doping concentration is not less than E18cm^-3。

As shown in figure 3g, the first doped region 109 of N-type is formed in the second epitaxial layer 104.

First doped region 109 is located in the first isolated island, and the second epitaxial layer 104 is extended to from 104 surface of the second epitaxial layer In, its implantation dosage is not less than E14cm^-2, dopant is, for example, phosphorus.

As illustrated in figure 3h, opening is formed on insulating layer 106 so that the first doped region 109 and the second doped region 108 via Corresponding opening is exposed outside.

As shown in figure 3i, the first electrode 110 through insulating layer 106 is formed, first electrode 110 is electrically connected the first doping 109 and second doped region 108 of area, the signal end I/O as the TVS device.

As shown in Fig. 3 j, second electrode 111 is formed in the second surface of Semiconductor substrate 101, as connecing for the TVS device Ground terminal GND, first surface and second surface are relative to each other.First electrode 110 and second electrode 111 be selected from gold, silver, The metal or alloy such as copper, aluminium, aluminium silicon, aluminium copper silicon, titanium silver, titanium nickel gold form.

As can be seen that device according to the present utility model, can be prepared with easy steps and be operated under high working voltage One-way low-capacitance Transient Voltage Suppressor.By selecting the Semiconductor substrate and epitaxial layer of identical doping type, reduce outer Prolong the manufacture difficulty of layer, so as to ensure that the stabilization of device parameters and performance.It is and more in epitaxial layer different from conventional single-chip The Integrated Solution of design and the making of core devices is completed in upper surface, and device according to the present utility model largely make use of The solid space of chip, chip internal is produced on by the larger power device of footprint area, only has some more to design rule The device of strict demand is placed on epitaxial layer upper surface and completes to make, chip area utilization rate higher, integrated level higher, chip size Further compressed, reduce packaging cost, possess industrialization advantage.

It should be noted that herein, relational terms such as first and second and the like are used merely to a reality Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to Non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only will including those Element, but also including other elements that are not explicitly listed, or further include as this process, method, article or equipment Intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that Also there are other identical element in process, method, article or equipment including the key element.

As described above, these embodiments do not have all details of detailed descriptionthe to embodiment according to the utility model, Also it is only the specific embodiment not limit the utility model.Obviously, as described above, many modification and change can be made Change.This specification is chosen and specifically describes these embodiments, and being should in order to preferably explain the principle and reality of the utility model With so that skilled artisan can repairing using the utility model and on the basis of the utility model well Change use.The utility model is limited only by the claims and their full scope and equivalents.

Claims (9)

1. A kind of 1. Transient Voltage Suppressor, it is characterised in that including：

   The Semiconductor substrate of first doping type；

   First epitaxial layer of the first doping type on the Semiconductor substrate first surface；

   The buried regions of the second doping type in the epitaxial layer, wherein, the first doping type and the second doping type are different；

   Second epitaxial layer of the first doping type on first epitaxial layer；

   The second doping type in the buried regions neutralization second epitaxial layer is extended to from second epi-layer surface respectively The first isolated area and the first doping type the second isolated area, first isolated area and second isolated area are respectively used to The first isolated island and the second isolated island are formed in second epitaxial layer；And

   Extended to respectively in first isolated island and second isolated island from the epi-layer surface outside described second Prolong the first doped region of the first doping type in layer and the second doped region of the second doping type,

   Wherein, it is electrically connected between first doped region and second doped region.
2. 2. Transient Voltage Suppressor according to claim 1, it is characterised in that further include insulating layer, the insulating layer position In on second epitaxial layer.
3. 3. Transient Voltage Suppressor according to claim 2, it is characterised in that further include first electrode, first electricity Pole is electrically connected through the insulating layer and first doped region and second doped region.
4. 4. Transient Voltage Suppressor according to claim 1, it is characterised in that further include positioned at the Semiconductor substrate The second electrode on two surfaces, the first surface and the second surface are relative to each other.
5. 5. Transient Voltage Suppressor according to claim 1, it is characterised in that second isolated area surrounds described second Doped region.
6. 6. Transient Voltage Suppressor according to claim 1, it is characterised in that the doping concentration of second epitaxial layer is small In the doping concentration of first epitaxial layer.
7. 7. Transient Voltage Suppressor according to claim 1, it is characterised in that the doping concentration of the buried regions is not less than E17cm^-3, the doping concentration of first isolated area is not less than E18cm^-3, the doping concentration of second isolated area is not less than E18cm^-3, the implantation dosage of first doped region is not less than E14cm^-2, the doping concentration of second doped region is not less than E18cm^-3。
8. 8. Transient Voltage Suppressor according to claim 1, it is characterised in that the thickness of second epitaxial layer is not less than 5μm。
9. 9. Transient Voltage Suppressor according to claim 1, it is characterised in that first doping type is N-type or P Type, second doping type are another in N-type or p-type.