CN105679836B

CN105679836B - Ultra-low capacitance TVS diode structure and preparation method thereof

Info

Publication number: CN105679836B
Application number: CN201610166380.5A
Authority: CN
Inventors: 杨忠武
Original assignee: Beihai Huike Semiconductor Technology Co Ltd
Current assignee: Beihai Huike Semiconductor Technology Co Ltd
Priority date: 2016-03-23
Filing date: 2016-03-23
Publication date: 2022-07-12
Anticipated expiration: 2036-03-23
Also published as: CN105679836A

Abstract

The invention provides a transient suppression protector (TVS) diode for ESD protection of an ultra-low capacitance electronic product and a preparation method thereof. The invention forms second impurity regions with deep junctions and shallow junctions arranged at intervals on a silicon wafer with high-resistivity first impurity, and adjusts the concentration ratio of a contact region of a PN junction by injecting the first impurity under the second impurity region of the shallow junction so as to achieve the designed reverse avalanche breakdown voltage. Forming ultra-low capacitance at the deep junction region, and adjusting the area ratio of the deep junction region and the shallow junction region and the resistivity of the high resistivity region to reach the designed capacitance value; the depth of the deep junction region is adjusted to a high power value. The TVS is mainly applied to ESD protection of ultrahigh frequency electronic equipment, and has a wide application range.

Description

Ultra-low capacitance TVS diode structure and preparation method thereof

Technical Field

The invention belongs to the technical field of diodes and preparation thereof, and particularly relates to an ultra-low capacitance Transient Voltage Suppressor (TVS) diode and a preparation method thereof.

Background

TVS diodes are widely used for protection of electronic circuits, and are generally connected in parallel to components to be protected, and when external high pulse voltages such as lightning strikes and static Electricity (ESD) pass, the current can be quickly discharged, so that the voltage is maintained at a low level, and the damage of the high voltage to the components is avoided. Along with the miniaturization of the circuit, the use frequency is higher and higher, the speed is faster and faster, and the external TVS capacitance must be smaller and smaller, otherwise, the frequency of the whole circuit is reduced, and the loss is increased. The capacitance of TVS is reduced from several hundred PF to below 1PF, posing new challenges for TVS.

In order to realize the TVS low capacitance characteristic, a common method is to connect a common capacitance diode in series with a low capacitance diode, as shown in fig. 1 in U.S. patent No. US2008/0217749 a1, and connect a common TVS diode (11) and a low capacitance PIN diode (12) in series back to back, and then connect a low capacitance rectifier diode (13) in parallel, and package the three diodes together to form the low capacitance characteristic. The problem is that it is costly to do so and the packaging is complex.

It is desirable to implement on a single chip to ensure both low capacitance, proper voltage (slightly above and near operating voltage), and sufficient power without increasing chip area. This is the object of the present invention.

Disclosure of Invention

The invention forms second impurity regions with deep junctions and shallow junctions arranged at intervals on a silicon wafer with high-resistivity first impurity, and adjusts the concentration ratio of a contact region of a PN junction by injecting the first impurity under the second impurity region of the shallow junction so as to achieve the designed reverse avalanche breakdown voltage. Forming ultra-low capacitance at the deep junction region, and adjusting the area ratio of the deep junction region and the shallow junction region and the resistivity of the high resistivity region to reach the designed capacitance value; the depth of the deep junction region is adjusted to a high power value.

Fig. 2 is a schematic structural diagram of the present invention. For semiconductor silicon materials the first impurity is of the N-type and the second impurity is of the P-type, and vice versa. The explanation is given for the first impurity as an N-type, whereas a P-type is the same.

The unit capacitance is mainly determined by the resistivity of the N-layer, and the capacitance is small when the resistivity is high. E.g., a resistivity of 0.06 ohm-cm and a specific capacitance of about 100000PF/cm²E.g., a resistivity of 50 ohm-cm and a specific capacitance of about 350PF/cm²About 285 times different. For the structure shown in fig. 2, the shallow junction region and the deep junction region are connected in parallel, and the total capacitance is the sum of the two regions. Shallow junction region to achieve low avalanche breakdown voltage, a slightly higher concentration of N-type region is added on the N-region, the concentration of the N-type region is determined by the breakdown voltage, such as 7V, with a concentration of about 1.8E17/cm³(corresponding to a resistivity of 0.06 ohm cm); the N-resistivity under the deep junction region can be selected to be high resistivity, so that the unit capacitance C/A is reduced,

total capacitance = C_{Deep junction region}+C_{Shallow junction region}=S_{Deep junction region} X （C/A）_{Deep junction region}+ S_{Shallow junction region} X （C/A）_{Shallow junction region}

(S is an area)

Thus adjusting S_{Deep junction region} / S_{Shallow junction region}The value, the total capacitance can be adjusted. As in the above example, if S_{Deep junction region} / S_{Shallow junction region}

10 times, the total capacitance would be 1/7 for the conventional structure

The N-type region formation can be achieved by implanting N-type impurities, the impurity concentration profile is shown in fig. 3.

The structure of the invention arranges the deep junction region and the shallow junction region at intervals, and the junction of the deep junction region is deeper than that of the N-type modulation region. Avalanche breakdown will occur first due to the shallow junction region having an N-type modulation region. When avalanche breakdown of the shallow junction region occurs, a large number of carriers enter the N-type region, breakdown of the deep junction region occurs immediately, the whole effective region becomes a low-resistance region, all the carriers participate in power bearing, and reduction of effective area and power caused by addition of the high-resistivity N-region and the deep junction region is avoided.

For chip terminal protection, a mesa structure or a planar structure can be adopted. The mesa structure is more advantageous in reducing capacitance.

Drawings

FIG. 1 is a diagram of a standard low capacitance TVS circuit;

FIG. 2 is a schematic diagram of a chip according to the present invention;

FIG. 3 is a graph showing the concentration distribution of shallow junction regions.

Detailed Description

The present invention is further illustrated by the following specific examples, which are not intended to limit the scope of the invention.

Examples

Growing an oxide layer of 0.6um on a silicon epitaxial wafer (N-region thickness is 7um, resistivity is 50 ohm cm), photoetching a deep junction region, and implanting boron 8E14/cm²Junction pushing, oxide layer removing, phosphorus (1E 13/cm) injection²) Push-to-knot, implant boron (8E 14/cm)²) The method comprises the steps of knot pushing, photoetching and etching of a table board, passivation of the table board, evaporation of front metal, photoetching of the front metal, evaporation of back metal, testing and scribing.

The chip area of the embodiment is 0.09mm²The area ratio of the deep junction to the shallow junction is 50:1, the reverse cut-off (breakdown) voltage of the obtained diode is 7V, and the capacitance is 0.8 PF.

Of course, those skilled in the art should realize that the above embodiments are illustrative only and not limiting of the present invention, and that changes and modifications to the above described embodiments are intended to fall within the scope of the appended claims, as long as they fall within the true spirit and scope of the present invention.

Claims

1. A low-voltage TVS diode with ultra-low capacitance is characterized in that a chip is formed by forming second impurity regions with deep junctions and shallow junctions at intervals on a high-resistivity silicon chip with first impurities, forming the first impurity regions below the second impurity regions of the shallow junctions, wherein the junctions of the deep junctions are deeper than the first impurity regions, the first impurity regions are opposite to the second impurity regions in type, the deep junctions and the shallow junctions are arranged at intervals, the first impurity regions are formed below the shallow junctions to adjust the concentration ratio of contact regions of PN junctions so as to achieve the designed reverse avalanche breakdown voltage, the shallow junctions and the deep junctions are connected in parallel, the total capacitance is the sum of the capacitances of the two regions, the deep junctions form ultra-low capacitance, the area ratio of the deep junctions and the shallow junctions and the resistivity of the high-resistivity regions are adjusted so as to achieve the designed capacitance value, S deep junction/S shallow junctions is 10, and S is the area; the depth of the deep junction region is adjusted to a high power value.

2. A preparation method of a TVS diode comprises the following steps: forming a deep junction second impurity region on a high-resistivity silicon epitaxial wafer or a diffusion wafer, forming a first impurity region by injecting a1 st impurity, forming a shallow junction second impurity region, arranging the deep junction and the shallow junction regions at intervals, photoetching a terminal, forming upper and lower electrode metals, forming the first impurity region under the second impurity region of the shallow junction, wherein the junction depth of the deep junction is deeper than that of the first impurity region, the first impurity region and the second impurity region are opposite in type, the shallow junction region and the deep junction region are connected in parallel, the total capacitance is the sum of two regions of capacitance, the deep junction region forms an ultra-low capacitance, the area ratio of the deep junction and the shallow junction region and the resistivity of the high-resistivity region are adjusted to reach a designed capacitance value, the S deep junction/S shallow junction region is 10, and the S is the area; the depth of the deep junction region is adjusted to a high power value.