CN105679836A - Ultra-low-capacitance TVS diode structure and preparation method therefor - Google Patents
Ultra-low-capacitance TVS diode structure and preparation method therefor Download PDFInfo
- Publication number
- CN105679836A CN105679836A CN201610166380.5A CN201610166380A CN105679836A CN 105679836 A CN105679836 A CN 105679836A CN 201610166380 A CN201610166380 A CN 201610166380A CN 105679836 A CN105679836 A CN 105679836A
- Authority
- CN
- China
- Prior art keywords
- impurity
- low
- region
- capacitance
- ultra
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 230000015556 catabolic process Effects 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract 2
- 238000013461 design Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 claims 1
- 230000001052 transient effect Effects 0.000 abstract description 2
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- APTZNLHMIGJTEW-UHFFFAOYSA-N pyraflufen-ethyl Chemical compound C1=C(Cl)C(OCC(=O)OCC)=CC(C=2C(=C(OC(F)F)N(C)N=2)Cl)=C1F APTZNLHMIGJTEW-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a transient voltage suppressor (TVS) diode used for ultra-low-capacitance electronic product ESD protection and a preparation method for the TVS diode. According to the method, a high-electrical-resistivity silicon wafer is adopted to lower the diode PN junction capacitance; the concentration of a low-concentration region of a PN junction contact region is partially adjusted through impurity injection to achieve the designed low voltage; and therefore, ultra-low capacitance, low voltage and high power can be ensured. A second impurity region with deep junctions and shallow junctions that are arranged at intervals is formed on the silicon wafer of the high-electrical-resistivity first impurity; the concentration ratio of the contact region of the PN junctions can be adjusted by injecting the first impurity below the second impurity region of the shallow junctions so as to achieve the designed reverse avalanche breakdown voltage; ultra-low capacitance is formed in the deep junction region; the designed capacitance value can be achieved by adjusting the area proportion of the deep junctions and the shallow junctions and the electrical resistivity of the high-electrical-resistivity region; and a high power value can be realized by adjusting the depth of the deep junction region. The TVS provided by the invention is mainly applied to ESD protection of ultra-high-frequency electronic equipment, and has wide application ranges.
Description
Technical field
The invention belongs to the technical field of diode and preparation thereof, particularly relate to transient state voltage suppressor (TVS) diode and its preparation method of a kind of ultra-low capacitance.
Background technology
TVS diode is extensively for the protection of electronic circuit; usually be parallel to the components and parts to be protected, when there being outside high pulse voltage, as thunderbolt, electrostatic (ESD) by time can fast its current drain be fallen; voltage is maintained lower level, avoids high-voltage to the damage of components and parts. Along with the miniaturization of circuit, it may also be useful to frequency is more and more higher, speed goes is fast, and the electric capacity of external TVS also must be more and more less, otherwise can reduce the frequency of whole circuit, increases loss. So the electric capacity of TVS is from several hundred PF, below 1PF to be dropped to, TVS is proposed new challenge.
In order to realize the low capacitance characteristic of TVS, general method is a low electric capacity diode of being connected by conventional capacitive diode, such as United States Patent (USP) (patent No. US2008/0217749A1), it is shown in Fig. 1, low to a general T VS diode (11) and one electric capacity PIN diode (12) is connected back-to-back, loong shunt low capacitance rectifier diode (13) again, three diode package together, form low capacitance characteristic. Problem does cost height like this, and encapsulation is complicated.
It is desirable that complete on a single die, both ensured low electric capacity, suitable voltage (Lve Gao close to operating voltage), the basis of chip area had ensured enough power not increasing again. This is the object of the present invention.
Summary of the invention
The present invention is the 2nd kind of impurity district being formed on the silicon chip of the first impurity of high resistivity and being spaced dark knot and shallow junction, and in the 2nd kind of impurity district of shallow junction below by the concentration ratio injecting the zone of action that the first impurity regulates PN to tie, reach the reverse avalanche breakdown voltage of design. Dark interface forms ultra-low capacitance, and the resistivity in the dark knot of adjustment and shallow junction region area ratio and high resistivity district reaches the capacitance of design; The degree of depth adjusting dark interface reaches high performance number.
Fig. 2 show present configuration schematic diagram. If for the first impurity N-type of semiconductor silicon material, then the 2nd kind of impurity is P type, and vice versa.This explanation is illustrated by N-type of the first impurity, otherwise P type is as a same reason.
Specific capacitance value size is mainly determined by N-layer resistivity, and then electric capacity is little for resistivity height. If resistivity is 0.06 ohmcm, specific capacitance is about 100000PF/cm2, if resistivity is 50 ohmcms, specific capacitance is about 350PF/cm2, differ about 285 times. For structure as shown in Figure 2, shallow junction region and dark interface are in parallel, and total capacitance is two district's capacitance. Shallow junction region, in order to realize low avalanche breakdown voltage, to be increased the slightly high N-type region of concentration in N-district, and the concentration design of this N-type region is determined by voltage breakdown, and such as 7V voltage, concentration is about 1.8E17/cm3(being equivalent to 0.06 ohmcm resistivity); Under dark interface, N-resistivity can select high resistivity, then reduce specific capacitance C/A,
Total capacitance=CDark interface+CShallow junction region=SDark interfaceX(C/A)Dark interface+SShallow junction regionX(C/A)Shallow junction region
(S is area)
Therefore S is adjustedDark interface/SShallow junction regionValue, adjustable total capacitance. As above example parameter value, if SDark interface/SShallow junction region
Be 10 times, then total capacitance can be the 1/7 of ordinary construction
N-type region is formed and realizes by injecting N-type impurity mode. and impurities concentration distribution is as shown in Figure 3.
Present configuration is spaced in dark interface and shallow junction region, and dark interface knot modulates district in N-type deeply. Owing to there is N-type modulation district shallow junction region, will first there is avalanche breakdown. After shallow junction region avalanche breakdown occurs, having a large amount of current carrier to enter N-type district, dark interface punctures immediately, all becomes low-resistance region in whole effective district, all participate in power carrying, it is unlikely to cause owing to adopting high resistivity N-district and dark interface to add useful area to reduce and power reduction.
For chip terminal protection, mesa structure can be adopted, it is possible to adopt two dimensional structure. Mesa structure is more favourable to reduction electric capacity.
Accompanying drawing explanation
Fig. 1 standard low-capacitance TVS wiring diagram;
Fig. 2 chip schematic diagram of the present invention;
Fig. 3 shallow junction region concentration profile.
Embodiment
Below by way of specific embodiment, the invention will be further described, but embodiment does not limit the scope of the invention.
Embodiment
At silicon epitaxial wafer (N-district thickness 7um, resistivity 50 ohmcm) upper growth zone of oxidation 0.6um, the dark interface of photoetching, injects boron 8E14/cm2, knot, removes zone of oxidation, injects phosphorus (1E13/cm2), knot, injects boron (8E14/cm2), knot, chemical wet etching table top, mesa passivation, evaporation front metal, photoetching front metal, evaporation back metal, test, scribing.
The present embodiment chip area 0.09mm2, dark knot and shallow junction area ratio are 50:1, gained diode reverse cut-off (puncturing) voltage 7V, electric capacity 0.8PF.
Certainly, those of ordinary skill in the art will be appreciated that, above embodiment is only used to the present invention is described, and not as limitation of the invention, as long as in the spirit of the present invention, to the change of the above embodiment, distortion all by the scope dropping on claims of the present invention.
Claims (5)
1. a ultra-low capacitance low pressure TVS diode, its chip is the 2nd kind of impurity district being formed on the silicon chip of the first impurity of high resistivity and being spaced dark knot and shallow junction, and forming the first impurity district of lower concentration below the 2nd kind of impurity district of shallow junction, the knot of dark knot is deeply in the first impurity district of lower concentration.
2. TVS diode according to claim 1, it is characterised in that, it is spaced dark knot and shallow junction region, under shallow junction region, forms the first impurity district of lower concentration to the concentration ratio of the zone of action that regulates PN to tie, reach the reverse avalanche breakdown voltage of design.
3. dark interface forms ultra-low capacitance, and the resistivity in the dark knot of adjustment and shallow junction region area ratio and high resistivity district reaches the capacitance of design; The degree of depth adjusting dark interface reaches high performance number.
4. the preparation method of a Schottky barrier diode, its step comprises: forms dark knot the 2nd kind of impurity district on silicon epitaxial wafer or diffusion sheet, forms the 1st kind of low impurity concentration region by injecting the 1st kind of impurity method, then form shallow 2nd kind of impurity district, photoetching terminal, then forms upper/lower electrode metal.
5. the preparation method of TVS diode according to claim 3, it is characterised in that, form low-concentration impurity region by injecting opposite types impurity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610166380.5A CN105679836B (en) | 2016-03-23 | 2016-03-23 | Ultra-low capacitance TVS diode structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610166380.5A CN105679836B (en) | 2016-03-23 | 2016-03-23 | Ultra-low capacitance TVS diode structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105679836A true CN105679836A (en) | 2016-06-15 |
| CN105679836B CN105679836B (en) | 2022-07-12 |
Family
ID=56311397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610166380.5A Active CN105679836B (en) | 2016-03-23 | 2016-03-23 | Ultra-low capacitance TVS diode structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105679836B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106252349A (en) * | 2016-09-30 | 2016-12-21 | 安徽富芯微电子有限公司 | A kind of low Capacitance Power TVS device and manufacture method thereof |
| CN107680962A (en) * | 2017-09-27 | 2018-02-09 | 安徽富芯微电子有限公司 | A kind of low forward voltage TVS device and its manufacture method |
| CN110444537A (en) * | 2019-08-29 | 2019-11-12 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of ceramic paster encapsulates the design method of two-way low junction capacity TVS diode |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1328346A (en) * | 2000-06-07 | 2001-12-26 | 日本电气株式会社 | Diode capable of regulating breakdown valtage without increasing parasitic capacitance and manufacturing method thereof |
| JP2003188391A (en) * | 2001-12-21 | 2003-07-04 | Sanken Electric Co Ltd | Semiconductor device and manufacturing method thereof |
| CN101697357A (en) * | 2009-05-12 | 2010-04-21 | 上海芯石微电子有限公司 | Schottky barrier diode and preparation method thereof |
| CN201498983U (en) * | 2009-08-26 | 2010-06-02 | 苏州晶讯科技股份有限公司 | Programmable semiconductor anti-surge protective device with deep well structure |
| CN102646723A (en) * | 2011-02-22 | 2012-08-22 | 株式会社日立制作所 | Semiconductor device and device with use of it |
| CN103208530A (en) * | 2013-03-11 | 2013-07-17 | 江苏应能微电子有限公司 | Low capacitance super-deep groove transient voltage restraining diode structure |
| CN103840013A (en) * | 2014-01-26 | 2014-06-04 | 上海韦尔半导体股份有限公司 | Bidirectional TVS and manufacturing method of bidirectional TVS |
| CN104091823A (en) * | 2014-07-24 | 2014-10-08 | 江苏捷捷微电子股份有限公司 | Transient-suppression diode chip and manufacturing method thereof |
| US20140361398A1 (en) * | 2013-06-05 | 2014-12-11 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing same |
| US20150091125A1 (en) * | 2013-10-02 | 2015-04-02 | Robert Bosch Gmbh | Semiconductor array having temperature-compensated breakdown voltage |
| CN104508806A (en) * | 2012-09-27 | 2015-04-08 | 罗姆股份有限公司 | Chip diode and method for manufacturing same |
| CN205582945U (en) * | 2016-03-23 | 2016-09-14 | 上海安微电子有限公司 | Ultralow electric capacity TVS diode |
-
2016
- 2016-03-23 CN CN201610166380.5A patent/CN105679836B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1328346A (en) * | 2000-06-07 | 2001-12-26 | 日本电气株式会社 | Diode capable of regulating breakdown valtage without increasing parasitic capacitance and manufacturing method thereof |
| JP2003188391A (en) * | 2001-12-21 | 2003-07-04 | Sanken Electric Co Ltd | Semiconductor device and manufacturing method thereof |
| CN101697357A (en) * | 2009-05-12 | 2010-04-21 | 上海芯石微电子有限公司 | Schottky barrier diode and preparation method thereof |
| CN201498983U (en) * | 2009-08-26 | 2010-06-02 | 苏州晶讯科技股份有限公司 | Programmable semiconductor anti-surge protective device with deep well structure |
| CN102646723A (en) * | 2011-02-22 | 2012-08-22 | 株式会社日立制作所 | Semiconductor device and device with use of it |
| CN104508806A (en) * | 2012-09-27 | 2015-04-08 | 罗姆股份有限公司 | Chip diode and method for manufacturing same |
| CN103208530A (en) * | 2013-03-11 | 2013-07-17 | 江苏应能微电子有限公司 | Low capacitance super-deep groove transient voltage restraining diode structure |
| US20140361398A1 (en) * | 2013-06-05 | 2014-12-11 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing same |
| US20150091125A1 (en) * | 2013-10-02 | 2015-04-02 | Robert Bosch Gmbh | Semiconductor array having temperature-compensated breakdown voltage |
| CN103840013A (en) * | 2014-01-26 | 2014-06-04 | 上海韦尔半导体股份有限公司 | Bidirectional TVS and manufacturing method of bidirectional TVS |
| CN104091823A (en) * | 2014-07-24 | 2014-10-08 | 江苏捷捷微电子股份有限公司 | Transient-suppression diode chip and manufacturing method thereof |
| CN205582945U (en) * | 2016-03-23 | 2016-09-14 | 上海安微电子有限公司 | Ultralow electric capacity TVS diode |
Non-Patent Citations (1)
| Title |
|---|
| 李宏: "《电力电子设备用器件与集成电路应用指南•第4册，其他配套元器件》", 31 October 2001, 机械工业出版社 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106252349A (en) * | 2016-09-30 | 2016-12-21 | 安徽富芯微电子有限公司 | A kind of low Capacitance Power TVS device and manufacture method thereof |
| CN106252349B (en) * | 2016-09-30 | 2019-10-29 | 富芯微电子有限公司 | A kind of low Capacitance Power TVS device and its manufacturing method |
| CN107680962A (en) * | 2017-09-27 | 2018-02-09 | 安徽富芯微电子有限公司 | A kind of low forward voltage TVS device and its manufacture method |
| CN107680962B (en) * | 2017-09-27 | 2023-06-13 | 富芯微电子有限公司 | Low forward voltage TVS device and manufacturing method thereof |
| CN110444537A (en) * | 2019-08-29 | 2019-11-12 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of ceramic paster encapsulates the design method of two-way low junction capacity TVS diode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105679836B (en) | 2022-07-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8377757B2 (en) | Device and method for transient voltage suppressor | |
| US9837516B2 (en) | Bi-directional punch-through semiconductor device and manufacturing method thereof | |
| US8338854B2 (en) | TVS with low capacitance and forward voltage drop with depleted SCR as steering diode | |
| US8835977B2 (en) | TVS with low capacitance and forward voltage drop with depleted SCR as steering diode | |
| KR101414005B1 (en) | Transient voltage suppressor and its manufacturing method | |
| CN102623454B (en) | There is the vertical transient voltage inhibitor of Electromagnetic interference filter | |
| CN106129058B (en) | Groove extraction integrated low-voltage bidirectional transient voltage suppressor and manufacturing method thereof | |
| US8304838B1 (en) | Electrostatic discharge protection device structure | |
| CN105932023A (en) | Transient voltage suppressor | |
| CN105679836A (en) | Ultra-low-capacitance TVS diode structure and preparation method therefor | |
| CN106158851B (en) | Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof | |
| CN106169508B (en) | Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof | |
| US9543420B2 (en) | Protection device and related fabrication methods | |
| CN105185782A (en) | Capacitive diode assembly and manufacturing method of the capacitive diode assembly | |
| US20140302647A1 (en) | Symmetric blocking transient voltage suppressor (tvs) using bipolar npn and pnp transistor base snatch | |
| CN107919355B (en) | Ultralow-residual-voltage low-capacity transient voltage suppressor and manufacturing method thereof | |
| CN108565260B (en) | Semiconductor device with a plurality of transistors | |
| US9831327B2 (en) | Electrostatic discharge protection devices and methods of forming the same | |
| CN111668210A (en) | Unidirectional high-voltage transient voltage suppression protection device and preparation method thereof | |
| CN205582945U (en) | Ultralow electric capacity TVS diode | |
| JP6594296B2 (en) | Zener diode with polysilicon layer with improved reverse surge capability and reduced leakage current | |
| CN108198812B (en) | Transient voltage suppressor and method of manufacturing the same | |
| CN108198811B (en) | Transient voltage suppressor and method of manufacturing the same | |
| KR20200027902A (en) | Structure and method for sic based protection device | |
| CN107527907A (en) | Transient Voltage Suppressor and its manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20190822 Address after: Room A-430, 4th Floor, Block A, Phase II, Guangxi Huike Science and Technology Co., Ltd., 336 East Extension Line of Beihai Avenue, Beihai Industrial Park, Guangxi Zhuang Autonomous Region Applicant after: BEIHAI HKC PHOTOELECTRIC TECHNOLOGY Co.,Ltd. Address before: Room 303-45, 33 Block 680 Guiping Road, Xuhui District, Shanghai, 2003 Applicant before: Shanghai Anwei Electronics Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20210422 Address after: Room 301, 3rd floor, building 16, Guangxi Huike Technology Co., Ltd., No. 336, East extension of Beihai Avenue, Beihai Industrial Park, 536000, Guangxi Zhuang Autonomous Region Applicant after: Beihai Huike Semiconductor Technology Co.,Ltd. Address before: Room A-430, 4th Floor, Block A, Phase II, Guangxi Huike Science and Technology Co., Ltd., 336 East Extension Line of Beihai Avenue, Beihai Industrial Park, Guangxi Zhuang Autonomous Region Applicant before: BEIHAI HKC PHOTOELECTRIC TECHNOLOGY Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |