CN106252349A - A kind of low Capacitance Power TVS device and manufacture method thereof - Google Patents
A kind of low Capacitance Power TVS device and manufacture method thereof Download PDFInfo
- Publication number
- CN106252349A CN106252349A CN201610874344.4A CN201610874344A CN106252349A CN 106252349 A CN106252349 A CN 106252349A CN 201610874344 A CN201610874344 A CN 201610874344A CN 106252349 A CN106252349 A CN 106252349A
- Authority
- CN
- China
- Prior art keywords
- diffusion layer
- type
- type diffusion
- power tvs
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Abstract
The present invention discloses a kind of low Capacitance Power TVS device, belong to quasiconductor protective device field, described low Capacitance Power TVS device is the monolithic integrated device connected by power TVS diode and low di-cap, including N-type semiconductor matrix, N+ type diffusion layer, P+ type diffusion layer, ion implanted region, passivation layer, metal level.The Diode series of power TVS diode and low electric capacity is integrated on one chip by the present invention, encapsulation is made to simplify, improve the yield of encapsulation, high resistant N-type semiconductor substrate is used to manufacture, reduce the junction capacity of device, avoiding signal of communication distortion, simultaneously by controlling ion implanting amount, the breakdown reverse voltage controlling device is 75 100V.
Description
Technical field
The invention belongs to quasiconductor protective device technical field, be specifically related to a kind of low Capacitance Power TVS device and
Manufacture method.
Background technology
TVS device is a kind of clamper type over-voltage protector, can with the response speed of ns by surge voltage clamper specific
Level, make rear end protected circuit from excessive pressure damages.TVS device is divided into power TVS device and low-capacitance TVS device, and one
For as, power TVS device can bear the surge current I of up to hundreds of amperes under 10/1000 μ s waveformPP, surge power (10/
1000 μ s) several kW can be reached, but generally its electric capacity also up to counts nF；And low-capacitance TVS device is only capable of bearing tens ampere 8/
Surge current under 20 μ s waveforms, power is only capable of reaching a few hectowatt (8/20 μ s), but have an advantage in that electric capacity can as little as 1pF with
Under.Along with the development of electronic product, the requirement to TVS protection device also improves constantly, and wishes TVS device in application
Surge power is the highest but capacitance is the lowest, especially in terms of capacitance parameter, because electric capacity is the biggest, to high workload frequency
The impact of rate circuit is the biggest, can cause transmitting distorted signals, the most even can have a strong impact on the function of circuit.Therefore the most a lot
Manufacturer is all researching and developing low Capacitance Power TVS protection device.
In order to reduce the electric capacity of power TVS, conventional method is that TVS diode and low di-cap are connected on one
Rising, the electric capacity of the most whole device depends on low di-cap, and electric capacity is substantially reduced, and typical product is SAC and LCE
The low Capacitance Power TVS of series.But this structure has a problem that, it be by power TVS diode the biggest for usual area and
The least low di-cap Series Package of area, in axial shell, encapsulates sufficiently complex, and process consistency is poor, the envelope of product
Dress yield is the lowest.
Summary of the invention
The one low Capacitance Power TVS device of present invention offer and manufacture method thereof, it is therefore intended that reduce the electricity of TVS device
Capacitance, ensures the high surge capacity of TVS device simultaneously.
The purpose of the present invention can be achieved through the following technical solutions:
A kind of low Capacitance Power TVS device, it is characterised in that: include that N-type semiconductor matrix, N+ type diffusion layer, P+ type expand
Dissipate layer, ion implanted region, passivation layer, metal level；Described N-type semiconductor matrix is positioned at the centre of device, described N+ type diffusion layer
Being positioned at the lower surface of N-type semiconductor, described P+ type diffusion layer is positioned at the upper surface of described N-type semiconductor matrix, in described P+ type
The inside of diffusion layer is distributed described N+ type diffusion layer, and described ion implanted region is between described P+ type diffusion layer and described N-type half
Region between conductor matrix, described passivation region is positioned at the groove of both sides, described N-type semiconductor matrix top, described metal level
The N+ type of the upper surface and described N-type semiconductor matrix underpart that lay respectively at the N+ type diffusion layer in described P+ type diffusion layer spreads
The lower surface of layer.
Further, described low Capacitance Power TVS device is the list connected by power TVS diode and low di-cap
Sheet integrated device.
Further, when the surge voltage on electrode T1 is higher than the surge voltage on electrode T2, the P+ type on device top
Diffusion layer and be positioned at the PN junction that the N+ type diffusion layer of P+ type diffusion layer constitutes and be in reverse-biased, and P+ type diffusion layer and N-type
The PN junction that semiconductor substrate is constituted is in positively biased state, and electrical surge high pressure makes reverse-biased PN junction generation avalanche breakdown, avenges simultaneously
Collapse and puncture knot and surge current is released by the PN junction of positively biased.
Further, when occurring without surge voltage on electrode T1, when electrode T2 is relative to electrode T1 high voltage, on device
The PN junction that the P+ type diffusion layer in portion and N-type ion implanted region are constituted is in reverse-biased, by controlling the dense of N-shaped ion implanted region
The working inverse voltage of device can be controlled between 75-100V by degree.
The manufacture method of a kind of low Capacitance Power TVS device, comprises the steps:
(1), silicon single crystal flake twin polishing；
(2), aoxidizing silicon chip, the thickness of oxide layer is Tox >=1.5 μm；
(3), POCl is used3Liquid source carries out phosphorus pre-deposited diffusion, finally carries out phosphorus and spreads knot again；
(4), ion implanted region is carried out photoetching；
(5), to silicon chip surface carry out phosphonium ion injection, then carry out phosphorus injection knot；
(6), boron diffusion: boron pre-deposition, boron spreads again；
(7), cathode chamber is carried out photoetching；
(8), phosphorus diffusing, doping: phosphorus pre-deposited is spread, and carries out phosphorus and spread knot again after diffusion；
(9), mesa recess is carried out photoetching, then mesa trench is corroded, finally groove is passivated；
(10), fairlead photoetching；
(11), on silicon chip two sides evaporate aluminum film, then aluminium lamination is carried out photoetching, carry out aluminium alloy the most again；
(12), the positive back side of silicon chip is evaporated Ti-Ni-Ag layer, then Ti-Ni-Ag layer is carried out photoetching.
Further, described low Capacitance Power TVS device uses n-type semiconductor silicon chip to make, the electricity of this semi-conductor silicon chip
Resistance rate is 50-500 Ω cm.
Further, the dosage that described phosphonium ion injects is 2e13-2e14cm-2, the energy of injection is 80-120keV.
Beneficial effects of the present invention: the Diode series of power TVS diode and low electric capacity is integrated in single by the present invention
On chip, make encapsulation simplify, improve the yield of encapsulation, use High Resistivity n-Type Semiconductor substrate to manufacture, reduce the knot electricity of device
Holding, it is to avoid signal of communication distortion, simultaneously by controlling ion implanting amount, the breakdown reverse voltage controlling device is 75-100V.
Accompanying drawing explanation
For the ease of it will be appreciated by those skilled in the art that the present invention is further illustrated below in conjunction with the accompanying drawings.
Fig. 1 is the structural representation of a kind of low Capacitance Power TVS device of the present invention.
Detailed description of the invention
As it is shown in figure 1, the list that a kind of low Capacitance Power TVS device is connected by power TVS diode and low di-cap
The device that sheet is integrated, as it is shown in figure 1, this low Capacitance Power TVS device includes that N-type semiconductor matrix, N+ type diffusion layer, P+ type expand
Dissipate layer, ion implanted region, passivation layer, metal level；N-type semiconductor matrix is positioned at the centre of device, and N+ type diffusion layer is positioned at N-type half
The lower surface of conductor, P+ type diffusion layer is positioned at the upper surface of N-type semiconductor matrix, N+ type is distributed in the inside of P+ type diffusion layer
Diffusion layer, ion implanted region region between P+ type diffusion layer and N-type semiconductor matrix, passivation region is positioned at N-type semiconductor
In the groove of both sides, matrix top, metal level lays respectively at the upper surface of the N+ type diffusion layer in P+ type diffusion layer and N-type is partly led
The lower surface of the N+ type diffusion layer of body bottom.
Respectively at layer on surface of metal extraction electrode T1 and electrode T2.When the surge voltage on electrode T1 is higher than on electrode T2
During surge voltage, the PN junction that the P+ type diffusion layer on device top and the N+ type diffusion layer being positioned at P+ type diffusion layer are constituted is in instead
State partially, and the PN junction that P+ type diffusion layer and N-type semiconductor matrix are constituted is in positively biased state, electrical surge high pressure makes reverse-biased
PN junction generation avalanche breakdown, by high voltage surge clamper in a relatively low level, the PN junction of avalanche breakdown knot and positively biased is by wave simultaneously
Gush current drain, thus protect rear end sensitivity circuit to damage from high voltage surge；When occurring without surge voltage, electrode on electrode T1
When T2 is relative to electrode T1 high voltage, the PN junction that the P+ type diffusion layer on device top and N-type ion implanted region are constituted is in instead
State partially, can be controlled the working inverse voltage of device between 75-100V by the concentration controlling N-type ion implanted region.
The gesture of the PN junction that the junction capacity of low Capacitance Power TVS device is made up of P+ type diffusion layer and N-type matrix in the present invention
Base electric capacity determines, and the barrier capacitance of PN junction is directly proportional to the square root of the low-doped side concentration constituting this PN junction, wherein N-type
Semiconductor substrate uses resistivity to be up to the N-type silicon chip of 50-500 Ω cm, and wherein capacitance is less than below 30pF.
The manufacture method of a kind of low Capacitance Power TVS device, comprises the steps:
(1), to select resistivity be 50～500 Ω cm, thickness is that the N-type silicon single crystal flake of 220～230 μm carries out two-sided throwing
Light；
(2), using the method for dry oxygen-wet oxygen-dry oxygen to grow one layer of thermal oxide layer at silicon chip surface, temperature is 1130 ± 10
DEG C, dry oxygen-wet oxygen-dry oxygen time is respectively 1h-4h-1h, and oxygen flow is 8L/min, it is desirable to 800 DEG C of turnover stoves, aoxidizes thickness
Degree is dsio2≥1.5μm；
(3), POCl is used3Carrying out pre-deposited diffusion, temperature is 1150 ± 2 DEG C, and the time is 120min, N2Flow is 4.5L/
Min, O2Flow is 1.5L/min, R□=0.5～0.6 Ω/, carries out phosphorus after pre-deposited diffusion and spreads knot, temperature 1200 again
± 2 DEG C, time 360 ± 30min, N2Flow is 6L/min, O2Flow is 2L/min；
(4), ion implanted region is carried out photoetching；
(5), to silicon chip surface carrying out phosphonium ion injection, the dosage injecting phosphonium ion is 2e13～2e14cm-2, the energy of injection
Amount is 80-120keV, then carries out phosphorus injection knot, temperature 1250 ± 5 DEG C, time 60 ± 10h, N2Flow is 6L/min, O2Flow
For 2L/min；
(6), boron diffusion: boron pre-deposition, temperature is 1100 ± 2 DEG C, the time is 100-200min；Boron spreads again, diffusion
Temperature 1230 ± 5 DEG C, time are 6 ± 1h；
(7), cathode chamber is carried out photoetching；
(8), phosphorus diffusing, doping: phosphorus pre-deposited is spread, temperature 1100 ± 2 DEG C, time 120-180min, N2Flow is 6L/
Min, O2Flow is 0.2L/min, R□=2～5 Ω/, carries out phosphorus after pre-deposited diffusion and spreads knot, temperature 1200 ± 2 again
DEG C, time 300 ± 60min, N2Flow is 6L/min, O2Flow is 2L/min；
(9), mesa recess is carried out photoetching, then with nitric acid: Fluohydric acid.: the corrosive liquid of glacial acetic acid=10:4:2 is to mesa trench
Corroding, the temperature of corrosion 5 ± 2 DEG C, time 15-20min, table top groove depth is 60～70 μm, finally groove is carried out glass
Passivation, sintering temperature 760 ± 5 DEG C, time 10-15min；
(10), fairlead photoetching；
(11), on silicon chip two sides evaporate aluminum film, aluminum layer thickness 1.5-2 μm, then aluminium lamination is carried out photoetching, carry out aluminum the most again
Alloy, temperature is 450 DEG C, and the time is 30min；
(12), the positive back side of silicon chip is evaporated Ti-Ni-Ag layer, then is carried out Ti-Ni-Ag layer photoetching.
The Diode series of power TVS diode and low electric capacity is integrated on one chip by the present invention, makes encapsulation simple
Change, improve the yield of encapsulation, use High Resistivity n-Type Semiconductor substrate to manufacture, reduce the junction capacity of device, it is to avoid signal of communication loses
Very, simultaneously by controlling ion implanting amount, the breakdown reverse voltage controlling device is 75-100V.
Above content is only the design example to the present invention and explanation, affiliated those skilled in the art
Described specific embodiment is made various amendment or supplements or use similar mode to substitute, without departing from invention
Design or surmount scope defined in the claims, protection scope of the present invention all should be belonged to.
Claims (7)
1. one kind low Capacitance Power TVS device, it is characterised in that: include that N-type semiconductor matrix, N+ type diffusion layer, P+ type spread
Layer, ion implanted region, passivation layer, metal level；Described N-type semiconductor matrix is positioned at the centre of device, described N+ type diffusion layer position
In the lower surface of N-type semiconductor, described P+ type diffusion layer is positioned at the upper surface of described N-type semiconductor matrix, expands in described P+ type
The inside dissipating layer is distributed described N+ type diffusion layer, and described ion implanted region is partly led between described P+ type diffusion layer and described N-type
Region between body matrix, described passivation region is positioned at the groove of both sides, described N-type semiconductor matrix top, and described metal level divides
It is not positioned at the upper surface of the N+ type diffusion layer of described P+ type diffusion layer and the N+ type diffusion layer of described N-type semiconductor matrix underpart
Lower surface.
One the most according to claim 1 low Capacitance Power TVS device, it is characterised in that: described low Capacitance Power TVS device
The monolithic integrated device that part is connected by power TVS diode and low di-cap.
One the most according to claim 1 low Capacitance Power TVS device, it is characterised in that: when the surge electricity on electrode T1
When pressure is higher than the surge voltage on electrode T2, the P+ type diffusion layer on device top and the N+ type diffusion layer being positioned at P+ type diffusion layer
The PN junction constituted is in reverse-biased, and the PN junction that P+ type diffusion layer and N-type semiconductor matrix are constituted is in positively biased state, transient state
High voltage surge makes reverse-biased PN junction generation avalanche breakdown, and surge current is released by the PN junction of avalanche breakdown knot and positively biased simultaneously.
One the most according to claim 1 low Capacitance Power TVS device, it is characterised in that: when occurring without wave on electrode T1
Gushing voltage, when electrode T2 is relative to electrode T1 high voltage, the P+ type diffusion layer on device top and N-type ion implanted region are constituted
PN junction is in reverse-biased, can be controlled the working inverse voltage of device at 75-by the concentration controlling N-type ion implanted region
Between 100V.
5. the manufacture method of one kind low Capacitance Power TVS device, it is characterised in that comprise the steps:
(1), silicon single crystal flake twin polishing；
(2), aoxidizing silicon chip, the thickness of oxide layer is Tox >=1.5 μm；
(3), POCl is used3Liquid source carries out phosphorus pre-deposited diffusion, finally carries out phosphorus and spreads knot again；
(4), ion implanted region is carried out photoetching；
(5), to silicon chip surface carry out phosphonium ion injection, then carry out phosphorus injection knot；
(6), boron diffusion: boron pre-deposition, boron spreads again；
(7), cathode chamber is carried out photoetching；
(8), phosphorus diffusing, doping: phosphorus pre-deposited is spread, and carries out phosphorus and spread knot again after diffusion；
(9), mesa recess is carried out photoetching, then mesa trench is corroded, finally groove is passivated；
(10), fairlead photoetching；
(11), on silicon chip two sides evaporate aluminum film, then aluminium lamination is carried out photoetching, carry out aluminium alloy the most again；
(12), the positive back side of silicon chip is evaporated Ti-Ni-Ag layer, then is carried out Ti-Ni-Ag layer photoetching.
The manufacture method of a kind of low Capacitance Power TVS device the most according to claim 5, it is characterised in that: described low electricity
Holding power TVS device uses N-type semiconductor silicon chip to make, and the resistivity of this semi-conductor silicon chip is 50-500 Ω cm.
The manufacture method of a kind of Capacitance Power TVS device the most according to claim 5, it is characterised in that: described phosphonium ion
The dosage injected is 2e13-2e14cm-2, the energy of injection is 80-120keV.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610874344.4A CN106252349B (en) | 2016-09-30 | 2016-09-30 | A kind of low Capacitance Power TVS device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610874344.4A CN106252349B (en) | 2016-09-30 | 2016-09-30 | A kind of low Capacitance Power TVS device and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106252349A true CN106252349A (en) | 2016-12-21 |
| CN106252349B CN106252349B (en) | 2019-10-29 |
Family
ID=57612219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610874344.4A Active CN106252349B (en) | 2016-09-30 | 2016-09-30 | A kind of low Capacitance Power TVS device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106252349B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113161427A (en) * | 2020-11-30 | 2021-07-23 | 江苏吉莱微电子股份有限公司 | Low-capacitance high-voltage discharge tube and preparation method thereof |
| CN115472605A (en) * | 2022-09-10 | 2022-12-13 | 江苏晟驰微电子有限公司 | Manufacturing method of high-power low-clamping protection device and protection device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040075160A1 (en) * | 2002-10-18 | 2004-04-22 | Jack Eng | Transient voltage suppressor having an epitaxial layer for higher avalanche voltage operation |
| CN102437199A (en) * | 2011-12-06 | 2012-05-02 | 绍兴旭昌科技企业有限公司 | Table-board type unidirectional negative resistance diode chip and manufacturing method thereof |
| CN202332849U (en) * | 2011-10-11 | 2012-07-11 | 康可电子（无锡）有限公司 | LED (light-emitting diode) protection unit with the functions of over-voltage protection and open-circuit freewheeling |
| CN105679836A (en) * | 2016-03-23 | 2016-06-15 | 上海安微电子有限公司 | Ultra-low-capacitance TVS diode structure and preparation method therefor |
-
2016
- 2016-09-30 CN CN201610874344.4A patent/CN106252349B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040075160A1 (en) * | 2002-10-18 | 2004-04-22 | Jack Eng | Transient voltage suppressor having an epitaxial layer for higher avalanche voltage operation |
| CN202332849U (en) * | 2011-10-11 | 2012-07-11 | 康可电子（无锡）有限公司 | LED (light-emitting diode) protection unit with the functions of over-voltage protection and open-circuit freewheeling |
| CN102437199A (en) * | 2011-12-06 | 2012-05-02 | 绍兴旭昌科技企业有限公司 | Table-board type unidirectional negative resistance diode chip and manufacturing method thereof |
| CN105679836A (en) * | 2016-03-23 | 2016-06-15 | 上海安微电子有限公司 | Ultra-low-capacitance TVS diode structure and preparation method therefor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113161427A (en) * | 2020-11-30 | 2021-07-23 | 江苏吉莱微电子股份有限公司 | Low-capacitance high-voltage discharge tube and preparation method thereof |
| CN115472605A (en) * | 2022-09-10 | 2022-12-13 | 江苏晟驰微电子有限公司 | Manufacturing method of high-power low-clamping protection device and protection device |
| CN115472605B (en) * | 2022-09-10 | 2023-11-28 | 江苏晟驰微电子有限公司 | Manufacturing method of high-power low-clamping protection device and protection device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106252349B (en) | 2019-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102856318B (en) | Uni-directional transient voltage suppressor | |
| US8134217B2 (en) | Bypass diode for a solar cell | |
| CN105977154B (en) | One kind having double-buffering layer fast recovery diode chip manufacturing method based on diffusion technique | |
| CN101527324B (en) | Two-way low-voltage punch-through transient voltage suppression diode and manufacturing method thereof | |
| CN107204361B (en) | A kind of low-capacitance bidirectional TVS device and its manufacturing method | |
| CN103384063B (en) | A kind of surge protection circuit and manufacture method thereof | |
| JP5895950B2 (en) | Manufacturing method of semiconductor device | |
| CN102969245B (en) | A kind of inverse conductivity type integrated gate commutated thyristor manufacture method | |
| CN106601826A (en) | Fast recovery diode and manufacturing method thereof | |
| CN107170738B (en) | A kind of unidirectional TVS device of low capacitor and its manufacturing method | |
| CN106783984A (en) | A kind of two-sided terminal structure, inverse conductivity type semiconductor devices and preparation method thereof | |
| CN106252349B (en) | A kind of low Capacitance Power TVS device and its manufacturing method | |
| CN101859703B (en) | Low turn-on voltage diode preparation method | |
| CN107680962A (en) | A kind of low forward voltage TVS device and its manufacture method | |
| CN105206680A (en) | Bidirectional transient voltage suppressing diode and manufacturing method thereof | |
| CN108922920A (en) | A kind of unidirectional TVS device of big surge and its manufacturing method | |
| CN204011437U (en) | Bilateral transient voltage suppression diode | |
| CN104733544A (en) | TVS device and technological method | |
| CN110459593A (en) | A kind of unidirectional TVS device of low clamp voltage and its manufacturing method | |
| CN205177857U (en) | Fast recovery diode | |
| CN208781854U (en) | A kind of unidirectional TVS device of big surge | |
| CN105097908A (en) | Ultra high-speed pulse thyristor and manufacturing method thereof | |
| CN106816463A (en) | A kind of terminal structure, semiconductor devices and preparation method thereof | |
| CN104183593A (en) | Electrostatic discharge protection structure | |
| CN112271136A (en) | Preparation method of trigger type silicon controlled rectifier device and rectifying device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 230000 Hefei 503 high tech park, Anhui Applicant after: Wick Microelectronics Co., Ltd. Address before: 230031 room 521, innovation building, 860 Wangjiang West Road, Hefei high tech Zone, Anhui Applicant before: Anhui core Microelectronics Co., Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |