CN101859703B - Low turn-on voltage diode preparation method - Google Patents

Low turn-on voltage diode preparation method Download PDF

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CN101859703B
CN101859703B CN 201010173070 CN201010173070A CN101859703B CN 101859703 B CN101859703 B CN 101859703B CN 201010173070 CN201010173070 CN 201010173070 CN 201010173070 A CN201010173070 A CN 201010173070A CN 101859703 B CN101859703 B CN 101859703B
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type impurity
type
knot
high temperature
thickness
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CN101859703A (en
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唐文雄
李泽宏
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V-CHIP MICROSYSTEMS Inc
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V-CHIP MICROSYSTEMS Inc
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Abstract

The invention discloses a low turn-on voltage diode and a preparation method thereof, aiming to solve the technical problems on how to reduce forward voltage drop, enhance breakdown voltage and reduce the cost on the low turn-on voltage diode. The low turn-on voltage diode is prepared by the following steps of: preparing monocrystalline silicon, preparing Pring, pushing knot at high temperature, preparing a polysilicon gate, preparing Pbody, pushing knot at high temperature, preparing NSD, preparing PSD by pushing knot at high temperature, oxidizing at high temperature, metallizing the front surface, thinning and metallizing the back surface, testing preliminarily, scribing, sintering, wire bonding, testing in the middle stage, encapsulating and testing totally to obtain the low turn-on voltage diode. Compared with the prior art, the low turn-on voltage diode has the breakdown voltage exceeding 100V, and has the turn-on voltage below 0.54V at 1A. The low turn-on voltage diode is prepared on a monocrystalline substrate; only four photomasks are used, without adopting an epitaxial technology; and a chip has lower manufacturing cost.

Description

The preparation method of low turn-on voltage diode
Technical field
The present invention relates to a kind of semiconductor device and preparation method thereof, particularly a kind of diode and preparation method thereof.
Background technology
Traditional rectifier diode mainly contains PN junction diode and Schottky diode two classes.Wherein PN junction diode forward pressure drop VF is bigger, and reverse recovery time, Trr was longer, but the stability of PN junction diode better, can work in high voltage; Schottky diode has absolute predominance when low-voltage: its forward voltage drop is little, and reverse recovery time is short, but the leakage current when Schottky diode is reverse is higher relatively, and unstable.In order to improve diode behavior, Junction Barrier Controlled rectifier JBS (JBS:JunctionBarrier Controlled Schottky Rectifier) has been proposed both at home and abroad, mix PiN/ Schottky rectifier MPS (MPS:MergedP-i-N/Schottky Rectifier), MOS control diode MCD devices such as (MCD:MOS Controlled Diode).Superpotential is built diode (Super Barrier Rectifier-SBR), it is rapid, the widely used power electronic device of a kind of development, it is the new unit that utilizes vertical double diffusion Metal-Oxide Semiconductor field-effect transistor VDMOS (the Vertical Double-diffusion MOSFET) advantage that switching speed is fast, current density is big to optimize, and has the characteristics of low forward voltage drop, short reverse recovery time and low-leakage current.Be widely used in DC-to-DC DC-DC transducer, UPS uninterrupted power supply, automotive electronics, portable electronics, motor drive system and other energy conversion device.But the low turn-on voltage diode of prior art all adopts epitaxy technique usually, causes the cost of chip higher.
Summary of the invention
The purpose of this invention is to provide a kind of low turn-on voltage diode and preparation method thereof, the technical problem that solve is to reduce forward voltage drop, improves puncture voltage, and reduces the cost of low turn-on voltage diode.
The present invention is by the following technical solutions: a kind of low turn-on voltage diode, adopt following method to prepare:
One, monocrystalline silicon is prepared, and adopts n type single crystal silicon substrate (1), and resistivity is 20 Ω cm, and its crystal orientation is＜100 〉, by prior art pre-oxidation formation thickness be
Figure GDA0000039958210000021
Silicon dioxide layer of protection (2);
Two, preparation P type terminal protection ring carries out boron (201) with photoresist (3) as mask layer and injects, and dosage is 3 * 10 15Cm -2, energy is 30KeV, forms P type ring terminal protection ring: thick be 0.5 μ m p type impurity one district (21), thick be 4 μ m p type impurity two districts (22), thick be p type impurity three districts (23) of 4 μ m;
Three, high temperature knot, the method deposition thickness by prior art behind the removal photoresist is
Figure GDA0000039958210000022
First oxide layer (31), under nitrogen environment, temperature is 1100 ℃, the time is 100min, obtaining p type impurity one district (21) concentration is 1 * 10 17Cm -3, p type impurity two districts (22) concentration is 1 * 10 17Cm -3, p type impurity three districts (23) concentration is 1 * 10 17Cm -3
Four, preparation polysilicon gate is made the zone of device and is adopted the active area reticle to carry out the active area etching by prior art at needs, by prior art growth 8nm gate oxide (41), by low pressure chemical vapor deposition thickness be then
Figure GDA0000039958210000023
Polysilicon (42), oxidation forms thickness and is again
Figure GDA0000039958210000024
Second oxide layer (43), adopt chemical vapor deposition thickness to be at last
Figure GDA0000039958210000025
Si 3N 4And adopt the multi-crystal silicon area reticle to carry out the P type doped body region window that etching forms metal-oxide-semiconductor (43);
Five, preparation P type doped body region is with Si 3N 4The mask layer that injects as ion carries out boron (501) injection, and dosage is 3 * 10 15Cm -2, energy is 30KeV, forms thickness to be
Figure GDA0000039958210000031
P type doped body region: p type impurity district (51);
Six, high temperature knot carries out knot to the impurity in the P type doped body region, forms channel region, and the high temperature knot is under nitrogen environment, and temperature is 1000 ℃, and the time is 20min, and obtaining p type impurity district (51) concentration is 1 * 10 15Cm -3
Seven, preparation N type impurity heavy doping is with Si 3N 4The mask layer that injects as ion carries out arsenic (701) injection, and dosage is 1 * 10 15Cm -2, energy is 30KeV, forms N type impurity heavily doped region: N type impurity heavy doping one district (71);
Eight, high temperature knot carries out impurity activation to N type impurity heavily doped region, forms the path of conduction, and activation of N type impurity heavily doped region and knot are under nitrogen environment, and temperature is 950 ℃, and the time is 10min, obtains N type impurity heavy doping one district (71), and concentration is 1 * 10 19Cm -3
Nine, preparation p type impurity heavy doping is with Si 3N 4As mask layer etching one layer thickness is the silicon of 0.15 μ m, and carries out boron (901) and BF 2(902) inject, form the p type impurity heavily doped region: the thickness that is positioned at etching groove sidewall is that N type impurity heavy doping two districts (72) of 1.0 μ m and the thickness that is positioned at etching groove below are the p type impurity heavily doped region (91) of 0.8 μ m, boron divides four injections, and accumulated dose is 6 * 10 14Cm -2, energy is 100KeV, each amount is 1.5 * 10 14Cm -2, energy is 100KeV, BF 2Inject, dosage is 8 * 10 15Cm -2, energy is 30KeV;
Ten, high-temperature oxydation carries out impurity activation and knot to the p type impurity heavily doped region, forms thickness on the whole silicon wafer surface simultaneously to be
Figure GDA0000039958210000032
The 3rd oxide layer (101), p type impurity heavy doping high temperature knot is under nitrogen environment, temperature is 950 ℃, the time is 60min, obtaining N type impurity heavy doping two districts (71) concentration is 1 * 10 19Cm -3, obtaining p type impurity heavily doped region (91) concentration is 1 * 10 18Cm -3
11, front-side metallization, at the first etching oxidation layer in entire device surface, the metal lithographic of splash-proofing sputtering metal aluminium (121), and employing again carving erosion metal forms metal lead wire by prior art;
12, thinning back side and metallization are carried out mechanical reduction to the device back side and are handled, and device is thinned to 200 μ m, form metal lead wire by prior art at device back spatter metal afterwards; Carry out preliminary survey, scribing, sintering, lead-in wire bonding, middle survey, encapsulation and total the survey again, obtain low turn-on voltage diode;
The resolution of the photoetching of described P type terminal protection ring, active area photoetching, multi-crystal silicon area photoetching and metal lithographic is 0.25um;
The N type impurity substrate (1) of described low turn-on voltage diode is a negative electrode, and metallic aluminium (121) is an anode, and the cellular gate oxide thickness of low turn-on voltage diode is 9nm, and the cellular groove depth is 0.18 μ m.
A kind of preparation method of low turn-on voltage diode, adopt following method to prepare:
One, monocrystalline silicon is prepared, and adopts n type single crystal silicon substrate (1), and resistivity is 20 Ω cm, and its crystal orientation is＜100 〉, by prior art pre-oxidation formation thickness be
Figure GDA0000039958210000041
Silicon dioxide layer of protection (2);
Two, preparation P type terminal protection ring carries out boron (201) with photoresist (3) as mask layer and injects, and dosage is 3 * 10 15Cm -2, energy is 30KeV, forms P type terminal protection ring: thick be 0.5 μ m p type impurity one district (21), thick be 4 μ m p type impurity two districts (22), thick be p type impurity three districts (23) of 4 μ m;
Three, high temperature knot, the method deposition thickness by prior art behind the removal photoresist is First oxide layer (31), under nitrogen environment, temperature is 1100 ℃, the time is 100min, obtaining p type impurity one district (21) concentration is 1 * 10 17Cm -3, p type impurity two districts (22) concentration is 1 * 10 17Cm -3, p type impurity three districts (23) concentration is 1 * 10 17Cm -3
Four, preparation polysilicon gate is made the zone of device and is adopted the active area reticle to carry out the active area etching by prior art at needs, by prior art growth 8nm gate oxide (41), by low pressure chemical vapor deposition thickness be then
Figure GDA0000039958210000051
Polysilicon (42), oxidation forms thickness and is again
Figure GDA0000039958210000052
Second oxide layer (43), adopt chemical vapor deposition thickness to be at last
Figure GDA0000039958210000053
Si 3N 4And adopt the multi-crystal silicon area reticle to carry out the P type doped body region window that etching forms metal-oxide-semiconductor (43);
Five, preparation P type doped body region is with Si 3N 4The mask layer that injects as ion carries out boron (501) injection, and dosage is 3 * 10 15Cm -2, energy is 30KeV, forms thickness to be
Figure GDA0000039958210000054
P type doped body region: p type impurity district (51);
Six, high temperature knot carries out knot to the impurity in the P type doped body region, forms channel region, and the high temperature knot is under nitrogen environment, and temperature is 1000 ℃, and the time is 20min, and obtaining p type impurity district (51) concentration is 1 * 10 15Cm -3
Seven, preparation N type impurity heavy doping is with Si 3N 4The mask layer that injects as ion carries out arsenic (701) injection, and dosage is 1 * 10 15Cm -2, energy is 30KeV, forms N type impurity heavily doped region: N type impurity heavy doping one district (71);
Eight, high temperature knot carries out impurity activation to N type impurity heavily doped region, forms the path of conduction, and activation of N type impurity heavily doped region and knot are under nitrogen environment, and temperature is 950 ℃, and the time is 10min, obtains N type impurity heavy doping one district (71), and concentration is 1 * 10 19Cm -3
Nine, preparation p type impurity heavy doping is with Si 3N 4As mask layer etching one layer thickness is the silicon of 0.15 μ m, and carries out boron (901) and BF 2(902) inject, form the p type impurity heavily doped region: the thickness that is positioned at etching groove sidewall is that N type impurity heavy doping two districts (72) of 1.0 μ m and the thickness that is positioned at etching groove below are the p type impurity heavily doped region (91) of 0.8 μ m, boron divides four injections, and accumulated dose is 6 * 10 14Cm -2, energy is 100KeV, each amount is 1.5 * 10 14Cm -2, energy is 100KeV, BF 2Inject, dosage is 8 * 10 15Cm -2, energy is 30KeV;
Ten, high-temperature oxydation carries out impurity activation and knot to the p type impurity heavily doped region, forms thickness on the whole silicon wafer surface simultaneously to be
Figure GDA0000039958210000061
The 3rd oxide layer (101), p type impurity heavy doping high temperature knot is under nitrogen environment, temperature is 950 ℃, the time is 60min, obtaining N type impurity heavy doping two districts (72) concentration is 1 * 10 19Cm -3, obtaining p type impurity heavily doped region (91) concentration is 1 * 10 18Cm -3
11, front-side metallization, at the first etching oxidation layer in entire device surface, the metal lithographic of splash-proofing sputtering metal aluminium (121), and employing again carving erosion metal forms metal lead wire by prior art;
12, thinning back side and metallization are carried out mechanical reduction to the device back side and are handled, and device is thinned to 200 μ m, form metal lead wire by prior art at device back spatter metal afterwards; Carry out preliminary survey, scribing, sintering, lead-in wire bonding, middle survey, encapsulation and total the survey again, obtain low turn-on voltage diode;
The resolution of the photoetching of described P type terminal protection ring, active area photoetching, multi-crystal silicon area photoetching and metal lithographic is 0.25um.
The present invention compared with prior art, low turn-on voltage diode has puncture voltage and surpasses 100V, has the cut-in voltage that is lower than 0.54V when 1A, on single crystalline substrate, prepare low turn-on voltage diode, do not adopt epitaxy technique, only use four reticle, chip has lower manufacturing cost.
Description of drawings
Fig. 1 is a process chart of the present invention.
Fig. 2 is the present invention's second step process generalized section.
Fig. 3 is the polysilicon generalized section that the present invention prepares.
Fig. 4 is that the present invention prepares the Pbody generalized section.
Fig. 4 a is the generalized section after Pbody high temperature of the present invention pushes away joint
Fig. 5 is that the present invention prepares the NSD generalized section.
Fig. 5 a is the generalized section after NSD high temperature of the present invention pushes away joint
Fig. 6 is that the present invention prepares the PSD generalized section.
Fig. 7 is the low turn-on voltage diode device architecture schematic diagram that the present invention prepares.
Fig. 8 is the low turn-on voltage diode cellular SEM photo that the present invention prepares.
Fig. 9 is the low turn-on voltage diode current-voltage characteristic curve that the present invention prepares.
Figure 10 is the low turn-on voltage diode breakdown characteristic that the present invention prepares.
Embodiment
Reference numeral is as follows: 1 is N type impurity substrate, and 2 are thin oxygen pad layer, and 3 is photoresist, and 21 is p type impurity one district, 22 is p type impurity two districts, and 23 is p type impurity three districts, and 31 is the ground floor oxide layer, and 41 is gate oxide, 42 is polysilicon, and 43 is second layer oxide layer, and 44 is Si 3N 4Layer, 51 is the p type impurity district, and 71 is N type impurity heavy doping one district, and 72 is N type impurity heavy doping two districts, 91 is the p type impurity heavily doped region, 121 is metal, and 201 is p type impurity, and 501 is p type impurity, 701 is N type heavy doping impurity, 901 is p type impurity, and 902 is P type heavy doping impurity, and 101 is the 3rd layer of oxide layer.
Technical term explanation: P type terminal protection ring district Pring; P type doped body region Pbody; active area Active; multi-crystal silicon area Poly; N type impurity heavily doped region NSD; p type impurity heavily doped region PSD, metal area Metal, high temperature knot refer to mix under the hot conditions impurity and spread the junction depth that increases PN junction in silicon.
Below in conjunction with drawings and Examples the present invention is described in further detail.As shown in Figure 1, the preparation method of low turn-on voltage diode of the present invention comprises following processing step:
One, monocrystalline silicon is prepared, and as shown in Figure 2, adopts n type single crystal silicon (N type impurity) substrate 1, and resistivity is 20 Ω cm, and its crystal orientation is＜100 〉, at n type single crystal silicon substrate 1 by prior art pre-oxidation formation thickness be
Figure GDA0000039958210000081
Silicon dioxide layer of protection 2 (thin oxygen pad layer).
Two, preparation Pring as shown in Figure 2, adopts ring Ring reticle by prior art Pring to be carried out photoetching, carries out boron 201 (p type impurity) with photoresist 3 as mask layer and injects, and dosage is 3 * 10 15Cm -2, energy is 30KeV, form Pring terminal protection ring: width is p type impurity one district 21 of 0.5 μ m, p type impurity 2 22 districts that width is 4 μ m, p type impurity three districts 23 that width is 4 μ m.
Three, high temperature knot, as shown in Figure 3, the method deposition thickness by prior art behind the removal photoresist is
Figure GDA0000039958210000082
First oxide layer 31, and Pring carried out the high temperature knot, to increase the puncture voltage of device, the high temperature knot is under nitrogen environment, temperature is 1100 ℃, the time is 100min, obtaining p type impurity one district 21 concentration is 1 * 10 17Cm -3, p type impurity two districts 22 concentration are 1 * 10 17Cm -3, p type impurity three districts 23 concentration are 1 * 10 17Cm -3
Four, preparation polysilicon gate as shown in Figure 3, is made the zone of device and is adopted the Active reticle to carry out the active area etching by prior art at needs, by prior art growth 8nm gate oxide 41, by low pressure chemical vapor deposition thickness be then
Figure GDA0000039958210000083
Polysilicon 42, oxidation forms thickness and is again
Figure GDA0000039958210000084
Second oxide layer 43, adopt chemical vapor deposition thickness to be at last Si 3N 444, and adopt the Poly reticle to carry out the pbody district window that etching forms metal-oxide-semiconductor.
Five, preparation Pbody, as shown in Figure 4, with Si 3N 4The mask layer that injects as ion carries out boron 501 (p type impurity) injection, and dosage is 3 * 10 15Cm -2, energy is 30KeV, forms thickness to be
Figure GDA0000039958210000086
The Pbody district: p type impurity district 51.
Six, high temperature knot shown in Fig. 4 a, carries out knot to the impurity in the Pbody district, forms channel region, and the high temperature knot is under nitrogen environment, and temperature is 1000 ℃, and the time is 20min, and obtaining p type impurity district 51 concentration is 1 * 10 15Cm -3
Seven, preparation NSD, as shown in Figure 5, with Si 3N 4The mask layer that injects as ion carries out arsenic 701 (N type heavy doping impurity) injection, and dosage is 1 * 10 15Cm -2, energy is 30KeV, forms the NSD district: N type impurity heavy doping one district 71.
Eight, high temperature knot shown in Fig. 5 a, carries out impurity activation to the NSD district, forms the path of conduction, and activation of NSD district and knot are under nitrogen environment, and temperature is 950 ℃, and the time is 10min, obtains N type impurity heavy doping one district 71, and concentration is 1 * 10 19Cm -3
Nine, preparation PSD, as shown in Figure 6, with Si 3N 4As mask layer etching one layer thickness is the silicon of 0.15 μ m, and carries out boron 901 (p type impurity) and BF 2902 (P type heavy doping impurity) inject, and form PSD: the thickness that is positioned at etching groove sidewall is that N type impurity heavy doping two districts 72 of 1.0 μ m and the thickness that is positioned at etching groove below are the p type impurity heavily doped region 91 of 0.8 μ m, and boron divides four injections, and accumulated dose is 6 * 10 14Cm -2, energy is 100KeV, each amount is 1.5 * 10 14Cm -2, energy is 100KeV, BF 2Inject, dosage is 8 * 10 15Cm -2, energy is 30KeV.
Ten, high-temperature oxydation as shown in Figure 6, carries out impurity activation and knot to PSD, forms thickness on the whole silicon wafer surface simultaneously to be
Figure GDA0000039958210000091
The 3rd oxide layer 101, PSD high temperature knot is under nitrogen environment, temperature is 950 ℃, the time is 60min, obtaining N type impurity heavy doping two districts 72 concentration is 1 * 10 19Cm -3, obtaining p type impurity heavily doped region 91 concentration is 1 * 10 18Cm -3
11, front-side metallization, as shown in Figure 7, at the first etching oxidation layer in entire device surface, splash-proofing sputtering metal aluminium 121 again by prior art, and adopt Metal reticle etching metal, form metal lead wire.
12, thinning back side and metallization are carried out mechanical reduction to the device back side and are handled, and device is thinned to 200 μ m, form metal lead wire by prior art at device back spatter metal afterwards.
Carry out preliminary survey, scribing, sintering, lead-in wire bonding, middle survey, encapsulation and total the survey by prior art again, obtain low turn-on voltage diode.
Method of the present invention adopts 4 reticle altogether, is followed successively by Pring reticle, Active reticle, Poly reticle, Metal reticle according to the order of version number, and resolution is 0.25um.
The ion implantation process that method of the present invention is carried out has: Pring boron injects, and Pbody boron injects, and NSD phosphorus injects, PSD boron, BF 2Inject.
The thermal process of four high temperature knots of method of the present invention: high temperature knot thermal process forms the Pring guard ring for the first time, and one deck silica of growing on this basis; The thermal process of high temperature knot forms the Pbody district for the second time; The thermal process of high temperature knot forms NSD for the third time; The thermal process of the 4th high temperature knot forms PSD.
As shown in Figure 8, adopt the KYKY-EM3200 type digital scanning electron microscope of Beijing KYKY Technology Development Co., Ltd. under 50,000 times amplification mode, to observe, the low turn-on voltage diode of method preparation of the present invention, the N type impurity substrate 1 of below is a negative electrode, the metallic aluminium part 121 of top is an anode, the cellular gate oxide thickness is 9nm, and the cellular groove depth is 0.18 μ m.This structure is the base unit of the forward work of this diode.
This structure can cause the p type impurity district 51 of poly below pbody to realize that transoid is the N type when having forward voltage to import; Thereby realize that electronics by the N type that p type impurity district 51 transoids of n type single crystal silicon substrate 1 to pbody form, arrives N type impurity heavy doping one district 71, N type impurity heavy doping two districts 72 again, arrive the homomorphism conducting state of Metal metallic aluminium 121 then.Eliminate the resistance of the electric field that causes by the PN joint of general-purpose diode existence, be lower than the cut-in voltage of 0.55V when can be implemented in 1A.The effect of the reverse withstand voltage 100V of this structure is caused by pring, is arranged in 22,23 the position of Fig. 2.
As shown in Figure 9, in temperature is 25 ℃, the transistor graphic instrument of employing standard is tested, draw out test result, wherein along slope coordinate is an anode current, and each lattice is represented 0.5A, lateral coordinates is an anode voltage, each lattice is represented 1V, from test result as can be seen the cut-in voltage of this diode be about 0.54V, this moment anode current be 1A.
As shown in figure 10, in temperature is 25 ℃, the transistor graphic instrument of employing standard is tested, draw out test result, along slope coordinate is an anode current, and each lattice is represented 50 μ A, and lateral coordinates is an anode voltage, each lattice is represented 20V, from test result as can be seen the puncture voltage of this diode be about 110V.
Method of the present invention prepares low turn-on voltage diode on single crystalline substrate, only use four reticle, does not adopt epitaxy technique, adopts the method for thinning back side, makes the low turn-on voltage diode chip have lower manufacturing cost.
The low turn-on voltage diode of the present invention's preparation has the advantages that forward voltage drop is low and puncture voltage is high, can be widely used in DC-DC transducer, UPS uninterrupted power supply, automotive electronics, portable electronics, motor drive system and other energy conversion device.
The present invention can also adopt body silicon, carborundum, GaAs, indium phosphide or germanium silicon semiconductor material to make.Wherein the boron ion divides four injections in the step 9, obtains good Impurity Distribution, reduces the reverse recovery time of device, improves switch performance.Wherein oxide layer deposit and anaerobic high temperature knot thermal process are merged into aerobic high temperature knot thermal process in the step 3, have saved manufacturing cost.The thickness of etch silicon is 0.1 μ m～0.6 μ m in the step 9, obtains good Impurity Distribution and bigger metal contact area, and area of dissipation increases, and has improved the heat dispersion of device.

Claims (1)

1. the preparation method of a low turn-on voltage diode, adopt following method to prepare:
One, monocrystalline silicon is prepared, and adopts n type single crystal silicon substrate (1), and resistivity is 20 Ω cm, and its crystal orientation is＜100 〉, by prior art pre-oxidation formation thickness be
Figure FDA0000039958200000011
Silicon dioxide layer of protection (2);
Two, preparation P type terminal protection ring carries out boron (201) with photoresist (3) as mask layer and injects, and dosage is 3 * 10 15Cm -2, energy is 30KeV, forms P type terminal protection ring: thick be 0.5 μ m p type impurity one district (21), thick be 4 μ m p type impurity two districts (22), thick be p type impurity three districts (23) of 4 μ m;
Three, high temperature knot, the method deposition thickness by prior art behind the removal photoresist is
Figure FDA0000039958200000012
First oxide layer (31), under nitrogen environment, temperature is 1100 ℃, the time is 100min, obtaining p type impurity one district (21) concentration is 1 * 10 17Cm -3, p type impurity two districts (22) concentration is 1 * 10 17Cm -3, p type impurity three districts (23) concentration is 1 * 10 17Cm -3
Four, preparation polysilicon gate is made the zone of device and is adopted the active area reticle to carry out the active area etching by prior art at needs, by prior art growth 8nm gate oxide (41), by low pressure chemical vapor deposition thickness be then Polysilicon (42), oxidation forms thickness and is again
Figure FDA0000039958200000014
Second oxide layer (43), adopt chemical vapor deposition thickness to be at last
Figure FDA0000039958200000015
Si 3N 4And adopt the multi-crystal silicon area reticle to carry out the P type doped body region window that etching forms metal-oxide-semiconductor (43);
Five, preparation P type doped body region is with Si 3N 4The mask layer that injects as ion carries out boron (501) injection, and dosage is 3 * 10 15Cm -2, energy is 30KeV, forms thickness to be P type doped body region: p type impurity district (51);
Six, high temperature knot carries out knot to the impurity in the P type doped body region, forms channel region, and the high temperature knot is under nitrogen environment, and temperature is 1000 ℃, and the time is 20min, and obtaining p type impurity district (51) concentration is 1 * 10 15Cm -3
Seven, preparation N type impurity heavy doping is with Si 3N 4The mask layer that injects as ion carries out arsenic (701) injection, and dosage is 1 * 10 15Cm -2, energy is 30KeV, forms N type impurity heavily doped region: N type impurity heavy doping one district (71);
Eight, high temperature knot carries out impurity activation to N type impurity heavily doped region, forms the path of conduction, and activation of N type impurity heavily doped region and knot are under nitrogen environment, and temperature is 950 ℃, and the time is 10min, obtains N type impurity heavy doping one district (71), and concentration is 1 * 10 19Cm -3
Nine, preparation p type impurity heavy doping is with Si 3N 4As mask layer etching one layer thickness is the silicon of 0.15 μ m, and carries out boron (901) and BF 2(902) inject, form p type impurity heavy doping heavily doped region: the thickness that is positioned at etching groove sidewall is that N type impurity heavy doping two districts (72) of 1.0 μ m and the thickness that is positioned at etching groove below are the p type impurity heavily doped region (91) of 0.8 μ m, boron divides four injections, and accumulated dose is 6 * 10 14Cm -2, energy is 100KeV, each amount is 1.5 * 10 14Cm -2, energy is 100KeV, BF 2Inject, dosage is 8 * 10 15Cm -2, energy is 30KeV;
Ten, high-temperature oxydation carries out impurity activation and knot to the p type impurity heavily doped region, forms thickness on the whole silicon wafer surface simultaneously to be
Figure FDA0000039958200000021
The 3rd oxide layer (101), p type impurity heavy doping high temperature knot is under nitrogen environment, temperature is 950 ℃, the time is 60min, obtaining N type impurity heavy doping two districts (72) concentration is 1 * 10 19Cm -3, obtaining p type impurity heavily doped region (91) concentration is 1 * 10 18Cm -3
11, front-side metallization, at the first etching oxidation layer in entire device surface, the metal lithographic of splash-proofing sputtering metal aluminium (121), and employing again carving erosion metal forms metal lead wire by prior art;
12, thinning back side and metallization are carried out mechanical reduction to the device back side and are handled, and device is thinned to 200 μ m, form metal lead wire by prior art at device back spatter metal afterwards; Carry out preliminary survey, scribing, sintering, lead-in wire bonding, middle survey, encapsulation and total the survey again, obtain low turn-on voltage diode;
The resolution of the photoetching of described P type terminal protection ring, active area photoetching, multi-crystal silicon area photoetching and metal lithographic is 0.25um.
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