CN110459593A - A kind of unidirectional TVS device of low clamp voltage and its manufacturing method - Google Patents
A kind of unidirectional TVS device of low clamp voltage and its manufacturing method Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 238000009792 diffusion process Methods 0.000 claims description 91
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 76
- 229910052710 silicon Inorganic materials 0.000 claims description 76
- 239000010703 silicon Substances 0.000 claims description 76
- 238000000151 deposition Methods 0.000 claims description 45
- 238000001259 photo etching Methods 0.000 claims description 45
- 230000008021 deposition Effects 0.000 claims description 41
- 229910052751 metal Inorganic materials 0.000 claims description 38
- 239000002184 metal Substances 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 32
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 20
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 20
- 239000007788 liquid Substances 0.000 claims description 20
- 229910052698 phosphorus Inorganic materials 0.000 claims description 20
- 239000011574 phosphorus Substances 0.000 claims description 20
- 229910052782 aluminium Inorganic materials 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- 239000004411 aluminium Substances 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- UIFOTCALDQIDTI-UHFFFAOYSA-N arsanylidynenickel Chemical compound [As]#[Ni] UIFOTCALDQIDTI-UHFFFAOYSA-N 0.000 claims description 5
- 230000008020 evaporation Effects 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 238000010189 synthetic method Methods 0.000 claims description 5
- 238000003466 welding Methods 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 5
- 238000003892 spreading Methods 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 210000000080 chela (arthropods) Anatomy 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0761—Vertical bipolar transistor in combination with diodes only
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
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- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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Abstract
The present invention discloses a kind of unidirectional TVS device of low clamp voltage, including P-type semiconductor substrate, positioned at the N-type isolated area of TVS device two sides, the middle part of TVS device is equipped with P-type semiconductor substrate, the two sides of the P-type semiconductor substrate are equipped with N-type isolated area, the top of the P-type semiconductor substrate is equipped with doped region in N-type, the two sides of doped region are equipped with P-doped zone in the N-type, and the lower part of the P-type semiconductor substrate is equipped with doped region under N-type；By being integrated with a NPN triode in traditional unidirectional TVS diode; NPN triode reverse breakdown negative resistance effect is utilized; it realizes in surge current increase; the clamp voltage of unidirectional TVS device can be effectively reduced; so that can work normally by protection circuit; the service life for increasing circuit reduces back-end circuit and is damaged or a possibility that maloperation, improves the safety of circuit.
Description
Technical field
The invention belongs to semiconductor protective device field more particularly to a kind of unidirectional TVS devices of low clamp voltage and its system
Make method.
Background technique
TVS is a kind of voltage clamp bit-type overvoltage protection diode, and TVS is generally parallel to by protection electronic circuit both ends, when
When the voltage at the both ends TVS is more than its breakdown reverse voltage, it can be at a terrific speed by overvoltage surge clamper in certain electricity
In pressure, thus surge energy of releasing, and do not influence to be protected the normal work of circuit.From application it is upper for, in order to avoid
Back-end circuit damage or maloperation, the clamp voltage of TVS necessarily are greater than the normal working voltage of protected circuit and are lower than
The breakdown voltage of protected circuit.
TVS diode usually utilizes the reversed avalanche breakdown principle production of pn-junction, with the increase of surge current, the pincers of TVS
Position voltage also will increase, the application (such as 8/20 μ s waveform) for some low surge energy high currents, traditional TVS device
Clamp voltage is too high, is no longer satisfied application requirement.In order to reduce the clamp voltage of TVS device, some companies use extension
Piece makes TVS device, and extension TVS includes N+Substrate, N-Epitaxial layer and P+Diffusion region, due to using low resistivity substrate and relatively thin
Epitaxial layer, the series resistance compared to extension TVS for traditional TVS substantially reduces, thus clamp voltage can be effectively reduced, greatly
The application range of TVS is extended greatly.But extension TVS of epitaxial wafer because made, more important there is also the deficiency that cost is excessively high
Be extension TVS be still using the reversed avalanche breakdown principle of pn-junction, clamp voltage and surge current there are positive resistance characteristic, essence
On still there is clamp voltage as surge current increases and the deficiency that significantly increases.
Summary of the invention
It is too high it is an object of the invention to solve the clamp voltage of existing TVS device, it is not able to satisfy application requirement, if
Made that TVS device cost is excessively high of epitaxial wafer, and the clamp voltage of extension TVS and surge current be there are positive resistance characteristic, with
The increase of surge current, the clamp voltage of TVS also will increase, influence by the normal work of protection circuit, after being easy to happen
Terminal circuit damage or the technical issues of maloperation, and a kind of unidirectional TVS device of low clamp voltage and its manufacturing method are provided, it can
To realize that the clamp voltage of the low unidirectional TVS device of clamp voltage can be effectively reduced when surge current increases.
To realize above-mentioned technical purpose and the technique effect, the invention is realized by the following technical scheme:
A kind of unidirectional TVS device of low clamp voltage, including doped region in P-type semiconductor substrate 1, N-type isolated area and N-type；
The middle part of TVS device is equipped with P-type semiconductor substrate, and the two sides of the P-type semiconductor substrate are equipped with N-type isolated area,
The top of the P-type semiconductor substrate is equipped with doped region in N-type, and the two sides of doped region are equipped with P-doped zone, institute in the N-type
The lower part for stating P-type semiconductor substrate is equipped with doped region under N-type；
The upper end face of the P-type semiconductor substrate is equipped with upper metal layer, and the both ends of the upper metal layer are equipped with titanium dioxide
Insulating layer on silicon, the rear surface of the P-type semiconductor substrate are equipped with lower metal layer, and the both ends of the lower metal layer are equipped with dioxy
Insulating layer under SiClx；
The upper metal layer is equipped with anode electrode, and the lower metal layer is equipped with cathode electrode.
Further, the width of the N-type isolated area is 50-100 μm.
Further, the area ratio of doped region and P-doped zone is 4:1-1:1 in the N-type.
Further, doped region and P-doped zone are connect with anode electrode in the N-type.
Further, doped region connects under the cathode electrode of P-type semiconductor substrate lower end and N-type.
The present invention also provides a kind of manufacturing methods of low unidirectional TVS device of clamp voltage, method includes the following steps:
Step S1, substrate prepare
Selection P-type silicon single crystal piece, 260 ± 5 μm of thickness；
Step S2, polishing
Using cmp method by polishing silicon single crystal sheet to a thickness of 200 ± 5 μm；
Step S3, oxidation
Using hydrogen-oxygen synthetic method silicon chip surface grow layer of silicon dioxide insulating layer, 1000-1100 DEG C of oxidizing temperature,
T=5-10h, oxidated layer thickness TOX=1.2-1.5 μm；
Step S4, N-type isolated area photoetching
Using isolated area reticle, isolated area window is formed simultaneously in the upper and lower surface of silicon wafer using double face photoetching machine；
Step S5, the diffusion of N-type isolated area
Using phosphorus oxychloride liquid source method of diffusion, phosphorus pre-deposition diffusion is first carried out simultaneously in silicon wafer two sides isolated area window
Doping, 1100-1170 DEG C of pre-deposition temperature, pre-deposition time 2h-6h, spread square resistance 0.1-0.5 Ω/, through it is too long when
Between the knot that spreads again make the phosphorus diffusion area on two sides connect together to form isolated area, then 1270 ± 5 DEG C of diffusion temperature, the time
80h-140h；
Step S6, anode P+ area's photoetching
The area P+, which is formed, in the upper surface of silicon wafer using anode P+ area's reticle spreads window；
Step S7, the diffusion of the area anode P+
The method spread using boron liquid source, the area the P+ diffusion window in the upper surface of silicon wafer carry out boron diffusing, doping, in advance
1000-1100 DEG C of depositing temperature, pre-deposition time 1h-3h, spread square resistance 5-15 Ω/, then diffusion temperature 1200 ± 5
DEG C, time 3h-5h；
Step S8, anode N+ area's photoetching
Using the area anode N+ reticle, the area anode N+ is formed in the upper surface of silicon wafer and spreads window；
Step S9, the diffusion of the area anode N+
Using phosphorus oxychloride liquid source method of diffusion, the area the anode N+ diffusion window in silicon wafer upper surface carries out phosphorus diffusion and mixes
Miscellaneous, 1100-1150 DEG C of pre-deposition temperature, pre-deposition time 2h-3h spreads square resistance 0.5-0.8 Ω/, then diffusion temperature
1250 ± 5 DEG C, time 10h-12h；
Step S10, cathode N+ area's photoetching
The area cathode N+, which is formed, in the lower surface of silicon wafer using photoetching principle spreads window；
Step S11, the diffusion of the area cathode N+
Using phosphorus oxychloride liquid source method of diffusion, the area the cathode N+ diffusion window in silicon wafer lower surface carries out phosphorus diffusion and mixes
Miscellaneous, 1000-1100 DEG C of pre-deposition temperature, pre-deposition time 1.5h-2h spreads square resistance 1.5-2 Ω/, then diffusion temperature
1200 ± 5 DEG C, time 2h-5h；
Step S12, fairlead photoetching
Upper and lower surfaces using photoetching principle in silicon wafer form metal ohmic contact window；
Step S13, evaporation of aluminum
The metallic aluminum that a layer thickness is 5 ± 2 μm is evaporated in the upper surface of silicon wafer；
Step S14, aluminium anti-carve
Metal aluminium electrode area is formed in the upper surface of silicon wafer using photoetching principle；
Step S15, back metal
One layer of titanium nickeline complex metal layer is evaporated in the lower surface of silicon wafer, thickness is respectively titanium layerNickel
LayerSilver layerAnd alloy is carried out, and 510 ± 5 DEG C of temperature, time 30-45min, thus shape
At easy welding layer.
Technical principle of the invention:
As shown in Fig. 2, pn-junction diode is integrated in by the unidirectional TVS device of low clamp voltage of the invention with NPN triode
Together, when the backward voltage at the both ends TVS device AK is lower, TVS device is released lesser electric current, a part of conduct of the electric current
The base current of NPN triode；When the backward voltage at the both ends TVS device AK reaches the breakdown reverse voltage of pn-junction diode,
Avalanche breakdown occurs for pn-junction diode.As backward voltage increases, the electric current that TVS device is released also is incrementally increased, NPN triode
Base current also incrementally increase, when the base current of NPN triode makes the emitter junction positively biased of NPN triode, tri- pole NPN
Pipe emitter injects electronics to substrate base area, and as backward voltage increases between AK, the emitter region of NPN triode is to substrate base area
More electronics are injected, the electronics for being injected into substrate base area reduces base resistance, thus as reverse current increases between AK
There is negative resistance effect, by the overvoltage clamper at the both ends TVS in a lower level.
Compared with prior art, beneficial effects of the present invention:
Unidirectional TVS device of the invention is utilized by being integrated with a NPN triode in traditional unidirectional TVS diode
NPN triode reverse breakdown negative resistance effect realizes in surge current increase, unidirectional TVS device can be effectively reduced
Clamp voltage increases the service life of circuit so that can work normally by protection circuit, reduces back-end circuit and damages
A possibility that bad or maloperation, improve the safety of circuit.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is the low unidirectional TVS device structural schematic diagram of clamp voltage provided by the invention；
Fig. 2 is the low unidirectional TVS device schematic diagram of clamp voltage provided by the invention；
In figure: 1, P-type semiconductor substrate；2, N-type isolated area；3, doped region in N-type；4, P-doped zone；5, it is mixed under N-type
Miscellaneous area；6, insulating layer on silica；7, upper metal layer；8, insulating layer under silica；9, lower metal layer；10, anode electrode；
11, cathode electrode.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts all other
Embodiment shall fall within the protection scope of the present invention.
A kind of low unidirectional TVS device of clamp voltage as shown in Figure 1, including P-type semiconductor substrate 1 are located at TVS device two
The N-type isolated area 2 of side, the width of isolated area are 50-100 μm, doped region 3 and P-doped zone 4 in the N-type on substrate top,
The area ratio of doped region 3 and P-doped zone 4 is 4:1 to 1:1 in N-type, doped region 5 and is located under the N-type of substrate lower part
Insulating layer 6 and upper metal layer 7 on the silica of semiconductor substrate upper end face, insulating layer 6 with a thickness of 1.2-1.5 μm, position
Insulating layer 8 and lower metal layer 9 under the silica of semiconductor substrate rear surface, upper metal layer 7 become the anode of TVS device
Electrode 10, lower metal layer 9 become the cathode electrode 11 of TVS device.
Embodiment 1
A kind of manufacturing method of the unidirectional TVS device of low clamp voltage, the manufacturing method the following steps are included:
Step S1, substrate prepare
Selection P-type silicon single crystal piece, 257 μm of thickness；
Step S2, polishing
Using cmp method by polishing silicon single crystal sheet to a thickness of 197 μm；
Step S3, oxidation
Using hydrogen-oxygen synthetic method silicon chip surface grow layer of silicon dioxide insulating layer, 1050 DEG C of oxidizing temperature, t=
6h, oxidated layer thickness TOX=1.3 μm；
Step S4, N-type isolated area photoetching
Using isolated area reticle, isolated area window is formed simultaneously in the upper and lower surface of silicon wafer using double face photoetching machine；
Step S5, the diffusion of N-type isolated area
Using phosphorus oxychloride liquid source method of diffusion, phosphorus pre-deposition diffusion is first carried out simultaneously in silicon wafer two sides isolated area window
Doping, is spread 0.3 Ω of square resistance/, is pushed away by spreading again for a long time by 1140 DEG C of pre-deposition temperature, pre-deposition time 3h
Knot is so that the phosphorus diffusion area on two sides connects together to form isolated area, then 1265 DEG C of diffusion temperature, time 110h；
Step S6, anode P+ area's photoetching
The area P+, which is formed, in the upper surface of silicon wafer using anode P+ area's reticle spreads window；
Step S7, the diffusion of the area anode P+
The method spread using boron liquid source, the area the P+ diffusion window in the upper surface of silicon wafer carry out boron diffusing, doping, in advance
1050 DEG C of depositing temperature, pre-deposition time 1.5h, spread 7 Ω of square resistance/, then 1197 DEG C of diffusion temperature, time 3.5h；
Step S8, anode N+ area's photoetching
Using the area anode N+ reticle, the area anode N+ is formed in the upper surface of silicon wafer and spreads window；
Step S9, the diffusion of the area anode N+
Using phosphorus oxychloride liquid source method of diffusion, the area the anode N+ diffusion window in silicon wafer upper surface carries out phosphorus diffusion and mixes
It is miscellaneous, 1120 DEG C of pre-deposition temperature, pre-deposition time 2.2h, spread 0.7 Ω of square resistance/, then 1247 DEG C of diffusion temperature, time
10.5h；
Step S10, cathode N+ area's photoetching
The area cathode N+, which is formed, in the lower surface of silicon wafer using photoetching principle spreads window；
Step S11, the diffusion of the area cathode N+
Using phosphorus oxychloride liquid source method of diffusion, the area the cathode N+ diffusion window in silicon wafer lower surface carries out phosphorus diffusion and mixes
It is miscellaneous, 1050 DEG C of pre-deposition temperature, pre-deposition time 1.7h, spread 1.6 Ω of square resistance/, then 1198 DEG C of diffusion temperature, time
2.4h；
Step S12, fairlead photoetching
Upper and lower surfaces using photoetching principle in silicon wafer form metal ohmic contact window；
Step S13, evaporation of aluminum
The metallic aluminum that a layer thickness is 4 μm is evaporated in the upper surface of silicon wafer；
Step S14, aluminium anti-carve
Metal aluminium electrode area is formed in the upper surface of silicon wafer using photoetching principle；
Step S15, back metal
One layer of titanium nickeline complex metal layer is evaporated in the lower surface of silicon wafer, thickness is respectively titanium layerNickel layerSilver layerAnd alloy is carried out, and 507 DEG C of temperature, time 38min, to form easy welding layer.
Embodiment 2
A kind of manufacturing method of the unidirectional TVS device of low clamp voltage, method includes the following steps:
Step S1, substrate prepare
Selection P-type silicon single crystal piece, 260 μm of thickness；
Step S2, polishing
Using cmp method by polishing silicon single crystal sheet to a thickness of 200 μm；
Step S3, oxidation
Using hydrogen-oxygen synthetic method silicon chip surface grow layer of silicon dioxide insulating layer, 1000 DEG C of oxidizing temperature, t=
5h, oxidated layer thickness TOX=1.4 μm；
Step S4, N-type isolated area photoetching
Using isolated area reticle, isolated area window is formed simultaneously in the upper and lower surface of silicon wafer using double face photoetching machine；
Step S5, the diffusion of N-type isolated area
Using phosphorus oxychloride liquid source method of diffusion, phosphorus pre-deposition diffusion is first carried out simultaneously in silicon wafer two sides isolated area window
Doping, is spread 0.1 Ω of square resistance/, is pushed away by spreading again for a long time by 1100 DEG C of pre-deposition temperature, pre-deposition time 2h
Knot is so that the phosphorus diffusion area on two sides connects together to form isolated area, then 1270 DEG C of diffusion temperature, time 80h；
Step S6, anode P+ area's photoetching
The area P+, which is formed, in the upper surface of silicon wafer using anode P+ area's reticle spreads window；
Step S7, the diffusion of the area anode P+
The method spread using boron liquid source, the area the P+ diffusion window in the upper surface of silicon wafer carry out boron diffusing, doping, in advance
1000 DEG C of depositing temperature, pre-deposition time 1h, spread 5 Ω of square resistance/, then 1200 DEG C of diffusion temperature, time 3h；
Step S8, anode N+ area's photoetching
Using the area anode N+ reticle, the area anode N+ is formed in the upper surface of silicon wafer and spreads window；
Step S9, the diffusion of the area anode N+
Using phosphorus oxychloride liquid source method of diffusion, the area the anode N+ diffusion window in silicon wafer upper surface carries out phosphorus diffusion and mixes
It is miscellaneous, 1100 DEG C of pre-deposition temperature, pre-deposition time 2h, spread 0.5 Ω of square resistance/, then 1250 DEG C of diffusion temperature, time
10h；
Step S10, cathode N+ area's photoetching
The area cathode N+, which is formed, in the lower surface of silicon wafer using photoetching principle spreads window；
Step S11, the diffusion of the area cathode N+
Using phosphorus oxychloride liquid source method of diffusion, the area the cathode N+ diffusion window in silicon wafer lower surface carries out phosphorus diffusion and mixes
It is miscellaneous, 1000 DEG C of pre-deposition temperature, pre-deposition time 1.5h, spread 1.5 Ω of square resistance/, then 1200 DEG C of diffusion temperature, time
2h；
Step S12, fairlead photoetching
Upper and lower surfaces using photoetching principle in silicon wafer form metal ohmic contact window；
Step S13, evaporation of aluminum
The metallic aluminum that a layer thickness is 5 μm is evaporated in the upper surface of silicon wafer；
Step S14, aluminium anti-carve
Metal aluminium electrode area is formed in the upper surface of silicon wafer using photoetching principle；
Step S15, back metal
One layer of titanium nickeline complex metal layer is evaporated in the lower surface of silicon wafer, thickness is respectively titanium layerNickel layerSilver layerAnd alloy is carried out, and 510 DEG C of temperature, time 30min, to form easy welding layer.
Embodiment 3
A kind of manufacturing method of the unidirectional TVS device of low clamp voltage, method includes the following steps:
Step S1, substrate prepare
Selection P-type silicon single crystal piece, 263 μm of thickness；
Step S2, polishing
Using cmp method by polishing silicon single crystal sheet to a thickness of 203 μm；
Step S3, oxidation
Using hydrogen-oxygen synthetic method silicon chip surface grow layer of silicon dioxide insulating layer, 1080 DEG C of oxidizing temperature, t=
9h, oxidated layer thickness TOX=1.5 μm；
Step S4, N-type isolated area photoetching
Using isolated area reticle, isolated area window is formed simultaneously in the upper and lower surface of silicon wafer using double face photoetching machine；
Step S5, the diffusion of N-type isolated area
Using phosphorus oxychloride liquid source method of diffusion, phosphorus pre-deposition diffusion is first carried out simultaneously in silicon wafer two sides isolated area window
Doping, is spread 0.5 Ω of square resistance/, is pushed away by spreading again for a long time by 1170 DEG C of pre-deposition temperature, pre-deposition time 6h
Knot is so that the phosphorus diffusion area on two sides connects together to form isolated area, then 1273 DEG C of diffusion temperature, time 140h；
Step S6, anode P+ area's photoetching
The area P+, which is formed, in the upper surface of silicon wafer using anode P+ area's reticle spreads window；
Step S7, the diffusion of the area anode P+
The method spread using boron liquid source, the area the P+ diffusion window in the upper surface of silicon wafer carry out boron diffusing, doping, in advance
1100 DEG C of depositing temperature, pre-deposition time 3h, spread 15 Ω of square resistance/, then 1205 DEG C of diffusion temperature, time 5h；
Step S8, anode N+ area's photoetching
Using the area anode N+ reticle, the area anode N+ is formed in the upper surface of silicon wafer and spreads window；
Step S9, the diffusion of the area anode N+
Using phosphorus oxychloride liquid source method of diffusion, the area the anode N+ diffusion window in silicon wafer upper surface carries out phosphorus diffusion and mixes
It is miscellaneous, 1150 DEG C of pre-deposition temperature, pre-deposition time 3h, spread 0.8 Ω of square resistance/, then 1255 DEG C of diffusion temperature, time
12h；
Step S10, cathode N+ area's photoetching
The area cathode N+, which is formed, in the lower surface of silicon wafer using photoetching principle spreads window；
Step S11, the diffusion of the area cathode N+
Using phosphorus oxychloride liquid source method of diffusion, the area the cathode N+ diffusion window in silicon wafer lower surface carries out phosphorus diffusion and mixes
It is miscellaneous, 1100 DEG C of pre-deposition temperature, pre-deposition time 2h, spread 2 Ω of square resistance/, then 1205 DEG C of diffusion temperature, time 5h；
Step S12, fairlead photoetching
Upper and lower surfaces using photoetching principle in silicon wafer form metal ohmic contact window；
Step S13, evaporation of aluminum
The metallic aluminum that a layer thickness is 7 μm is evaporated in the upper surface of silicon wafer；
Step S14, aluminium anti-carve
Metal aluminium electrode area is formed in the upper surface of silicon wafer using photoetching principle；
Step S15, back metal
One layer of titanium nickeline complex metal layer is evaporated in the lower surface of silicon wafer, thickness is respectively titanium layerNickel layerSilver layerAnd alloy is carried out, and 514 DEG C of temperature, time 45min, to form easy welding layer.
The unidirectional TVS device of the present invention is utilized by being integrated with a NPN triode in traditional unidirectional TVS diode
NPN triode reverse breakdown negative resistance effect realizes in surge current increase, the pincers of unidirectional TVS device can be effectively reduced
Position voltage increases the service life of circuit so that can work normally by protection circuit, reduces back-end circuit and is damaged
Or a possibility that maloperation, improve the safety of circuit.
The basic principles, main features and advantages of the present invention have been shown and described above.The technology of the industry
Personnel are it should be appreciated that the present invention is not limited to the above embodiments, and the above embodiments and description only describe this
The principle of invention, without departing from the spirit and scope of the present invention, various changes and improvements may be made to the invention, these changes
Change and improvement all fall within the protetion scope of the claimed invention.
Claims (6)
1. a kind of unidirectional TVS device of low clamp voltage, which is characterized in that including P-type semiconductor substrate (1), N-type isolated area (2)
With doped region in N-type (3)；
The middle part of TVS device is equipped with P-type semiconductor substrate (1), and the two sides of the P-type semiconductor substrate (1) are equipped with N-type isolated area
(2), the top of the P-type semiconductor substrate (1) is equipped with doped region (3) in N-type, and the two sides of doped region (3) are equipped in the N-type
The lower part of P-doped zone (4), the P-type semiconductor substrate (1) is equipped with doped region (5) under N-type；
The upper end face of the P-type semiconductor substrate (1) is equipped with upper metal layer (7), and the both ends of the upper metal layer (7) are equipped with two
The rear surface of insulating layer (6) on silica, the P-type semiconductor substrate (1) is equipped with lower metal layer (9), the lower metal layer
(9) both ends are equipped with insulating layer (8) under silica；
The upper metal layer (7) is equipped with anode electrode (10), and the lower metal layer (9) is equipped with cathode electrode (11).
2. a kind of low unidirectional TVS device of clamp voltage according to claim 1, which is characterized in that the N-type isolated area
(2) width is 50-100 μm.
3. a kind of low unidirectional TVS device of clamp voltage according to claim 1, which is characterized in that doped region in the N-type
(3) and the area ratio of P-doped zone (4) is 4:1-1:1.
4. a kind of low unidirectional TVS device of clamp voltage according to claim 1, which is characterized in that doped region in the N-type
(3) it is connect with anode electrode (10) with P-doped zone (4).
5. a kind of low unidirectional TVS device of clamp voltage according to claim 1, which is characterized in that the P-type semiconductor lining
The cathode electrode (11) of bottom (1) lower end is connect with doped region under N-type (5).
6. a kind of manufacturing method of the unidirectional TVS device of low clamp voltage, which is characterized in that method includes the following steps:
Step S1, substrate prepare
Selection P-type silicon single crystal piece, 260 ± 5 μm of thickness；
Step S2, polishing
Using cmp method by polishing silicon single crystal sheet to a thickness of 200 ± 5 μm；
Step S3, oxidation
Using hydrogen-oxygen synthetic method silicon chip surface grow layer of silicon dioxide insulating layer, 1000-1100 DEG C of oxidizing temperature, t=
5-10h, oxidated layer thickness TOX=1.2-1.5 μm；
Step S4, N-type isolated area photoetching
Using isolated area reticle, isolated area window is formed simultaneously in the upper and lower surface of silicon wafer using double face photoetching machine；
Step S5, the diffusion of N-type isolated area
Using phosphorus oxychloride liquid source method of diffusion, the diffusion of phosphorus pre-deposition is first carried out simultaneously in silicon wafer two sides isolated area window and is mixed
Miscellaneous, 1100-1170 DEG C of pre-deposition temperature, pre-deposition time 2h-6h spreads square resistance 0.1-0.5 Ω/, by for a long time
The knot that spreads again make the phosphorus diffusion area on two sides connect together to form isolated area, then 1270 ± 5 DEG C of diffusion temperature, time 80h-
140h；
Step S6, anode P+ area's photoetching
The area P+, which is formed, in the upper surface of silicon wafer using anode P+ area's reticle spreads window；
Step S7, the diffusion of the area anode P+
The method spread using boron liquid source, the area the P+ diffusion window in the upper surface of silicon wafer carry out boron diffusing, doping, pre-deposition
1000-1100 DEG C of temperature, pre-deposition time 1h-3h, square resistance 5-15 Ω/, then 1200 ± 5 DEG C of diffusion temperature are spread, when
Between 3h-5h；
Step S8, anode N+ area's photoetching
Using the area anode N+ reticle, the area anode N+ is formed in the upper surface of silicon wafer and spreads window；
Step S9, the diffusion of the area anode N+
Using phosphorus oxychloride liquid source method of diffusion, the area the anode N+ diffusion window in silicon wafer upper surface carries out phosphorus diffusion doping,
1100-1150 DEG C of pre-deposition temperature, pre-deposition time 2h-3h spread square resistance 0.5-0.8 Ω/, then diffusion temperature 1250
± 5 DEG C, time 10h-12h；
Step S10, cathode N+ area's photoetching
The area cathode N+, which is formed, in the lower surface of silicon wafer using photoetching principle spreads window；
Step S11, the diffusion of the area cathode N+
Using phosphorus oxychloride liquid source method of diffusion, the area the cathode N+ diffusion window in silicon wafer lower surface carries out phosphorus diffusion doping,
1000-1100 DEG C of pre-deposition temperature, pre-deposition time 1.5h-2h spread square resistance 1.5-2 Ω/, then diffusion temperature 1200
± 5 DEG C, time 2h-5h；
Step S12, fairlead photoetching
Upper and lower surfaces using photoetching principle in silicon wafer form metal ohmic contact window；
Step S13, evaporation of aluminum
The metallic aluminum that a layer thickness is 5 ± 2 μm is evaporated in the upper surface of silicon wafer；
Step S14, aluminium anti-carve
Metal aluminium electrode area is formed in the upper surface of silicon wafer using photoetching principle；
Step S15, back metal
One layer of titanium nickeline complex metal layer is evaporated in the lower surface of silicon wafer, thickness is respectively titanium layerNickel layerSilver layerAnd alloy is carried out, and 510 ± 5 DEG C of temperature, time 30-45min, to be formed easy
Welding layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113270318A (en) * | 2021-05-27 | 2021-08-17 | 江苏晟驰微电子有限公司 | Manufacturing process of unidirectional negative resistance type TVS chip |
| CN115346979A (en) * | 2022-10-18 | 2022-11-15 | 富芯微电子有限公司 | TVS device based on thyristor structure and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930975A (en) * | 2008-10-01 | 2010-12-29 | 万国半导体有限公司 | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (tvs) |
| WO2017118028A1 (en) * | 2016-01-05 | 2017-07-13 | 深圳市槟城电子有限公司 | Surge protector device |
| CN108039347A (en) * | 2018-01-17 | 2018-05-15 | 上海长园维安微电子有限公司 | A kind of integrated ultra-low capacitance returns greatly the common mode filtering device of TVS suddenly |
| CN109166908A (en) * | 2018-07-23 | 2019-01-08 | 富芯微电子有限公司 | A kind of unidirectional TVS of low overshoot voltage and its manufacturing method |
| CN210272368U (en) * | 2019-08-01 | 2020-04-07 | 富芯微电子有限公司 | Low clamping voltage unidirectional TVS device |
-
2019
- 2019-08-01 CN CN201910708894.2A patent/CN110459593B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930975A (en) * | 2008-10-01 | 2010-12-29 | 万国半导体有限公司 | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (tvs) |
| WO2017118028A1 (en) * | 2016-01-05 | 2017-07-13 | 深圳市槟城电子有限公司 | Surge protector device |
| CN108039347A (en) * | 2018-01-17 | 2018-05-15 | 上海长园维安微电子有限公司 | A kind of integrated ultra-low capacitance returns greatly the common mode filtering device of TVS suddenly |
| CN109166908A (en) * | 2018-07-23 | 2019-01-08 | 富芯微电子有限公司 | A kind of unidirectional TVS of low overshoot voltage and its manufacturing method |
| CN210272368U (en) * | 2019-08-01 | 2020-04-07 | 富芯微电子有限公司 | Low clamping voltage unidirectional TVS device |
Non-Patent Citations (1)
| Title |
|---|
| MADHUR BOBDE ET AL: "A Novel ESD Super-Clamp Structure for TVS Applications", APEC 2008: TWENTY-THIRD ANNUAL IEEE APPLIED ELECTRONICS CONFERENCE AND EXPOSITION, vol. 1, 1 January 2008 (2008-01-01), pages 987 - 900 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113270318A (en) * | 2021-05-27 | 2021-08-17 | 江苏晟驰微电子有限公司 | Manufacturing process of unidirectional negative resistance type TVS chip |
| CN115346979A (en) * | 2022-10-18 | 2022-11-15 | 富芯微电子有限公司 | TVS device based on thyristor structure and manufacturing method thereof |
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