CN110459593B - Low-clamping-voltage unidirectional TVS device and manufacturing method thereof - Google Patents
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Abstract
The invention discloses a low clamping voltage unidirectional TVS device, which comprises a P-type semiconductor substrate and N-type isolation regions positioned at two sides of the TVS device, wherein the P-type semiconductor substrate is arranged in the middle of the TVS device, the N-type isolation regions are arranged at two sides of the P-type semiconductor substrate, an N-type upper doping region is arranged at the upper part of the P-type semiconductor substrate, P-type doping regions are arranged at two sides of the N-type upper doping region, and an N-type lower doping region is arranged at the lower part of the P-type semiconductor substrate; through integrating an NPN triode in traditional unidirectional TVS diode, utilized NPN triode reverse breakdown negative resistance effect, realized when surge current increases, can effectively reduce unidirectional TVS device's clamp voltage for protected circuit can normally work, increased the life of circuit, reduced the possibility that the back-end circuit takes place to damage or maloperation, improved the security of circuit.
Description
Technical Field
The invention belongs to the field of semiconductor protection devices, and particularly relates to a low clamping voltage unidirectional TVS device and a manufacturing method thereof.
Background
The TVS is a voltage clamping type overvoltage protection diode, the TVS is generally connected in parallel with two ends of a protected electronic circuit, when the voltage of the two ends of the TVS exceeds the reverse breakdown voltage of the TVS, the TVS can clamp the surge overvoltage at a certain voltage at an extremely high speed, so that the surge energy is discharged, and the normal operation of the protected circuit is not influenced. In order to avoid damage or malfunction of the back-end circuit, the clamping voltage of the TVS must be higher than the normal operating voltage of the protected line and lower than the breakdown voltage of the protected line.
TVS diodes are typically fabricated using the pn junction reverse avalanche breakdown principle, with increasing surge current, the clamping voltage of the TVS will also increase, and for some low-surge energy high-current applications (e.g., 8/20 μs waveforms), the clamping voltage of conventional TVS devices is too high to meet the application requirements. In order to reduce the clamping voltage of the TVS device, some companies adopt epitaxial wafers to manufacture the TVS device, the epitaxial TVS comprises an N + substrate, an N - epitaxial layer and a P + diffusion region, and compared with the traditional TVS, the series resistance of the epitaxial TVS is greatly reduced due to the fact that the low-resistance substrate and the thinner epitaxial layer are adopted, so that the clamping voltage can be effectively reduced, and the application range of the TVS is greatly expanded. However, the epitaxial TVS is manufactured by adopting an epitaxial wafer, so that the defect of high cost exists, more importantly, the epitaxial TVS still utilizes the principle of reverse avalanche breakdown of a pn junction, and the clamping voltage and the surge current have positive resistance characteristics, and basically, the defect that the clamping voltage is obviously increased along with the increase of the surge current exists.
Disclosure of Invention
The invention aims to solve the technical problems that the clamping voltage of the conventional TVS device is too high to meet the application requirement, if the TVS device is manufactured by adopting an epitaxial wafer, the cost is too high, the clamping voltage of the epitaxial TVS and the surge current have positive resistance characteristics, and the clamping voltage of the TVS is increased along with the increase of the surge current, so that the normal operation of a protected circuit is influenced, the damage or misoperation of a rear-end circuit is easy to occur, and the low-clamping-voltage unidirectional TVS device and the manufacturing method thereof are provided, so that the clamping voltage of the low-clamping-voltage unidirectional TVS device can be effectively reduced when the surge current is increased.
In order to achieve the technical purpose and the technical effect, the invention is realized by the following technical scheme:
A low clamping voltage unidirectional TVS device comprises a P-type semiconductor substrate 1, an N-type isolation region and an N-type upper doping region;
the middle part of the TVS device is provided with a P-type semiconductor substrate, two sides of the P-type semiconductor substrate are provided with N-type isolation regions, the upper part of the P-type semiconductor substrate is provided with an N-type upper doping region, two sides of the N-type upper doping region are provided with P-type doping regions, and the lower part of the P-type semiconductor substrate is provided with an N-type lower doping region;
An upper metal layer is arranged on the upper end surface of the P-type semiconductor substrate, silicon dioxide upper insulating layers are arranged at two ends of the upper metal layer, a lower metal layer is arranged on the lower end surface of the P-type semiconductor substrate, and silicon dioxide lower insulating layers are arranged at two ends of the lower metal layer;
the upper metal layer is provided with an anode electrode, and the lower metal layer is provided with a cathode electrode.
Further, the width of the N-type isolation region is 50-100 μm.
Further, the area ratio of the N-type upper doped region to the P-type doped region is 4:1-1:1.
Further, the N-type upper doped region and the P-type doped region are connected with the anode electrode.
Further, a cathode electrode at the lower end of the P-type semiconductor substrate is connected with the N-type lower doped region.
The invention also provides a manufacturing method of the low clamping voltage unidirectional TVS device, which comprises the following steps:
Step S1, substrate preparation
Selecting a P-type silicon single crystal wafer with the thickness of 260+/-5 mu m;
Step S2, polishing
Polishing the silicon single crystal wafer to a thickness of 200+/-5 mu m by adopting a chemical mechanical polishing method;
Step S3, oxidizing
Growing a silicon dioxide insulating layer on the surface of a silicon wafer by adopting an oxyhydrogen synthesis method, wherein the oxidation temperature is 1000-1100 ℃, t=5-10 h, and the thickness T OX =1.2-1.5 mu m;
Step S4, N-type isolation region photoetching
Forming isolation region windows on the upper and lower surfaces of the silicon wafer simultaneously by using an isolation region photoetching plate and a double-sided photoetching machine;
Step S5, N-type isolation region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, firstly carrying out phosphorus pre-deposition diffusion doping at the windows of isolation areas on two sides of a silicon wafer at the same time, wherein the pre-deposition temperature is 1100-1170 ℃, the pre-deposition time is 2-6 h, the diffusion square resistance is 0.1-0.5 omega/≡, the two phosphorus diffusion areas on two sides are connected together to form an isolation area through long-time re-diffusion push junction, and the re-diffusion temperature is 1270+/-5 ℃ for 80-140 h;
step S6, anodic P+ region lithography
Forming a P+ region diffusion window on the upper surface of the silicon wafer by utilizing an anode P+ region photoetching plate;
Step S7, anode P+ region diffusion
Adopting a boron liquid source diffusion method, carrying out boron diffusion doping on a P+ region diffusion window on the upper surface of a silicon wafer, wherein the pre-deposition temperature is 1000-1100 ℃, the pre-deposition time is 1-3 h, the diffusion square resistance is 5-15 omega/≡and the diffusion temperature is 1200+/-5 ℃ for 3-5 h;
Step S8, anode N+ region photoetching
Forming an anode N+ region diffusion window on the upper surface of the silicon wafer by utilizing an anode N+ region photoetching plate;
step S9, anode N+ region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, carrying out phosphorus diffusion doping on an anode N+ region diffusion window on the upper surface of a silicon wafer, wherein the pre-deposition temperature is 1100-1150 ℃, the pre-deposition time is 2-3 h, the diffusion square resistance is 0.5-0.8Ω/≡, and the diffusion temperature is 1250+/-5 ℃ for 10-12 h;
step S10, cathodic N+ region lithography
Forming a cathode N+ region diffusion window on the lower surface of the silicon wafer by utilizing a photoetching principle;
step S11, cathode N+ region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, carrying out phosphorus diffusion doping on a cathode N+ region diffusion window on the lower surface of a silicon wafer, wherein the pre-deposition temperature is 1000-1100 ℃, the pre-deposition time is 1.5-2 h, the diffusion square resistance is 1.5-2 Ω/≡, and the diffusion temperature is 1200+/-5 ℃ for 2h-5h;
Step S12, lead hole photoetching
Forming a metal ohmic contact window on the upper surface and the lower surface of the silicon wafer by utilizing a photoetching principle;
Step S13, aluminum steaming
Evaporating a metal aluminum layer with the thickness of 5+/-2 mu m on the upper surface of the silicon wafer;
Step S14, aluminum back etching
Forming a metal aluminum electrode region on the upper surface of the silicon wafer by utilizing a photoetching principle;
Step S15, back side metallization
Evaporating a titanium-nickel-silver composite metal layer on the lower surface of the silicon wafer, wherein the thicknesses of the titanium-nickel-silver composite metal layer and the silicon wafer are respectively titanium layersNickel layer/>Silver layer/>And alloying at 510+ -5deg.C for 30-45min to form the easily welded layer.
The technical principle of the invention is as follows:
As shown in fig. 2, the low clamp voltage unidirectional TVS device of the present invention integrates a pn junction diode with an NPN triode, and when the reverse voltage across the TVS device AK is low, the TVS device discharges a small current, a portion of which is used as the base current of the NPN triode; when the reverse voltage across the TVS device AK reaches the reverse breakdown voltage of the pn junction diode, avalanche breakdown of the pn junction diode occurs. The current discharged by the TVS device is gradually increased along with the increase of the reverse voltage, the base current of the NPN triode is also gradually increased, when the base current of the NPN triode enables the emitter junction of the NPN triode to be positively biased, electrons are injected into the substrate base region by the emitter electrode of the NPN triode, more electrons are injected into the substrate base region by the emitter region of the NPN triode along with the increase of the reverse voltage among AKs, the resistance of the base region is reduced by the electrons injected into the substrate base region, and accordingly negative resistance effect appears among AKs along with the increase of the reverse current, and overvoltage at two ends of the TVS is clamped at a lower level.
Compared with the prior art, the invention has the beneficial effects that:
According to the unidirectional TVS device, the NPN triode is integrated in the traditional unidirectional TVS diode, the reverse breakdown negative resistance effect of the NPN triode is utilized, so that the clamping voltage of the unidirectional TVS device can be effectively reduced when the surge current is increased, a protected circuit can normally work, the service life of the circuit is prolonged, the possibility of damage or misoperation of a rear-end circuit is reduced, and the safety of the circuit is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
Fig. 1 is a schematic diagram of a low clamping voltage unidirectional TVS device according to the present invention;
Fig. 2 is a schematic diagram of a low clamp voltage unidirectional TVS device provided by the present invention;
In the figure: 1. a P-type semiconductor substrate; 2. an N-type isolation region; 3. an N-type upper doped region; 4. a P-type doped region; 5. an N-type lower doped region; 6. an insulating layer on the silicon dioxide; 7. a metal layer is arranged on the upper surface; 8. a silicon dioxide lower insulating layer; 9. a lower metal layer; 10. an anode electrode; 11. and a cathode electrode.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The low clamping voltage unidirectional TVS device shown in fig. 1 comprises a P-type semiconductor substrate 1, N-type isolation regions 2 positioned at two sides of the TVS device, the width of the isolation regions is 50-100 mu m, the area ratio of the N-type upper doped region 3 to the P-type doped region 4 positioned at the upper part of the substrate is 4:1 to 1:1, an N-type lower doped region 5 positioned at the lower part of the substrate, a silicon dioxide upper insulating layer 6 and an upper metal layer 7 positioned at the upper end surface of the semiconductor substrate, the thickness of the insulating layer 6 is 1.2-1.5 mu m, a silicon dioxide lower insulating layer 8 and a lower metal layer 9 positioned at the lower end surface of the semiconductor substrate, the upper metal layer 7 serves as an anode electrode 10 of the TVS device, and the lower metal layer 9 serves as a cathode electrode 11 of the TVS device.
Example 1
A method of manufacturing a low clamp voltage unidirectional TVS device, the method comprising the steps of:
Step S1, substrate preparation
Selecting a P-type silicon single crystal wafer, wherein the thickness of the P-type silicon single crystal wafer is 257 mu m;
Step S2, polishing
Polishing the silicon single crystal wafer to a thickness of 197 mu m by adopting a chemical mechanical polishing method;
Step S3, oxidizing
Growing a silicon dioxide insulating layer on the surface of a silicon wafer by adopting an oxyhydrogen synthesis method, wherein the oxidation temperature is 1050 ℃, t=6h, and the thickness T OX =1.3 mu m;
Step S4, N-type isolation region photoetching
Forming isolation region windows on the upper and lower surfaces of the silicon wafer simultaneously by using an isolation region photoetching plate and a double-sided photoetching machine;
Step S5, N-type isolation region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, firstly carrying out phosphorus pre-deposition diffusion doping at the windows of isolation areas on two sides of a silicon wafer, wherein the pre-deposition temperature is 1140 ℃, the pre-deposition time is 3h, the diffusion square resistance is 0.3 omega/≡, and the two phosphorus diffusion areas on two sides are connected together to form an isolation area through long-time re-diffusion push junction, and the re-diffusion temperature is 1265 ℃ and the time is 110h;
step S6, anodic P+ region lithography
Forming a P+ region diffusion window on the upper surface of the silicon wafer by utilizing an anode P+ region photoetching plate;
Step S7, anode P+ region diffusion
Adopting a boron liquid source diffusion method, carrying out boron diffusion doping on a P+ region diffusion window on the upper surface of a silicon wafer, pre-depositing at 1050 ℃ for 1.5h, diffusing square resistance 7Ω/≡, and diffusing at 1197 ℃ for 3.5h;
Step S8, anode N+ region photoetching
Forming an anode N+ region diffusion window on the upper surface of the silicon wafer by utilizing an anode N+ region photoetching plate;
step S9, anode N+ region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, carrying out phosphorus diffusion doping on an anode N+ region diffusion window on the upper surface of a silicon wafer, wherein the pre-deposition temperature is 1120 ℃, the pre-deposition time is 2.2h, the diffusion square resistance is 0.7Ω/≡, and the diffusion temperature is 1247 ℃ and the time is 10.5h;
step S10, cathodic N+ region lithography
Forming a cathode N+ region diffusion window on the lower surface of the silicon wafer by utilizing a photoetching principle;
step S11, cathode N+ region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, carrying out phosphorus diffusion doping on a cathode N+ region diffusion window on the lower surface of a silicon wafer, wherein the pre-deposition temperature is 1050 ℃, the pre-deposition time is 1.7h, the diffusion square resistance is 1.6Ω/≡, and the diffusion temperature is 1198 ℃ and the time is 2.4h;
Step S12, lead hole photoetching
Forming a metal ohmic contact window on the upper surface and the lower surface of the silicon wafer by utilizing a photoetching principle;
Step S13, aluminum steaming
Evaporating a metal aluminum layer with the thickness of 4 mu m on the upper surface of the silicon wafer;
Step S14, aluminum back etching
Forming a metal aluminum electrode region on the upper surface of the silicon wafer by utilizing a photoetching principle;
Step S15, back side metallization
Evaporating a titanium-nickel-silver composite metal layer on the lower surface of the silicon wafer, wherein the thicknesses of the titanium-nickel-silver composite metal layer and the silicon wafer are respectively titanium layersNickel layerSilver layer/>And alloying at 507 deg.c for 38min to form easy-to-weld layer.
Example 2
A method of manufacturing a low clamp voltage unidirectional TVS device, the method comprising the steps of:
Step S1, substrate preparation
Selecting a P-type silicon single crystal wafer with the thickness of 260 mu m;
Step S2, polishing
Polishing the silicon single crystal wafer to a thickness of 200 mu m by adopting a chemical mechanical polishing method;
Step S3, oxidizing
Growing a silicon dioxide insulating layer on the surface of a silicon wafer by adopting an oxyhydrogen synthesis method, wherein the oxidation temperature is 1000 ℃, t=5 h, and the thickness T OX =1.4 mu m;
Step S4, N-type isolation region photoetching
Forming isolation region windows on the upper and lower surfaces of the silicon wafer simultaneously by using an isolation region photoetching plate and a double-sided photoetching machine;
Step S5, N-type isolation region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, firstly carrying out phosphorus pre-deposition diffusion doping at the windows of isolation areas on two sides of a silicon wafer at the same time, wherein the pre-deposition temperature is 1100 ℃, the pre-deposition time is 2 hours, the diffusion square resistance is 0.1 omega/≡, and the two phosphorus diffusion areas on two sides are connected together to form an isolation area through long-time re-diffusion push junction, and the re-diffusion temperature is 1270 ℃ and the time is 80 hours;
step S6, anodic P+ region lithography
Forming a P+ region diffusion window on the upper surface of the silicon wafer by utilizing an anode P+ region photoetching plate;
Step S7, anode P+ region diffusion
Adopting a boron liquid source diffusion method, carrying out boron diffusion doping on a P+ region diffusion window on the upper surface of a silicon wafer, pre-depositing at 1000 ℃ for 1h, diffusing square resistance 5Ω/≡and then diffusing at 1200 ℃ for 3h;
Step S8, anode N+ region photoetching
Forming an anode N+ region diffusion window on the upper surface of the silicon wafer by utilizing an anode N+ region photoetching plate;
step S9, anode N+ region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, carrying out phosphorus diffusion doping on an anode N+ region diffusion window on the upper surface of a silicon wafer, pre-depositing at 1100 ℃ for 2 hours, diffusing square resistance at 0.5 omega/≡, and diffusing at 1250 ℃ for 10 hours;
step S10, cathodic N+ region lithography
Forming a cathode N+ region diffusion window on the lower surface of the silicon wafer by utilizing a photoetching principle;
step S11, cathode N+ region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, carrying out phosphorus diffusion doping on a cathode N+ region diffusion window on the lower surface of a silicon wafer, pre-depositing at 1000 ℃ for 1.5 hours, diffusing square resistance for 1.5 omega/≡, and diffusing at 1200 ℃ for 2 hours;
Step S12, lead hole photoetching
Forming a metal ohmic contact window on the upper surface and the lower surface of the silicon wafer by utilizing a photoetching principle;
Step S13, aluminum steaming
Evaporating a metal aluminum layer with the thickness of 5 mu m on the upper surface of the silicon wafer;
Step S14, aluminum back etching
Forming a metal aluminum electrode region on the upper surface of the silicon wafer by utilizing a photoetching principle;
Step S15, back side metallization
Evaporating a titanium-nickel-silver composite metal layer on the lower surface of the silicon wafer, wherein the thicknesses of the titanium-nickel-silver composite metal layer and the silicon wafer are respectively titanium layersNickel layerSilver layer/>And alloying at 510 ℃ for 30min to form an easy-to-weld layer.
Example 3
A method of manufacturing a low clamp voltage unidirectional TVS device, the method comprising the steps of:
Step S1, substrate preparation
Selecting a P-type silicon single crystal wafer with the thickness of 263 mu m;
Step S2, polishing
Polishing the silicon single crystal wafer to a thickness of 203 mu m by adopting a chemical mechanical polishing method;
Step S3, oxidizing
Growing a silicon dioxide insulating layer on the surface of a silicon wafer by adopting an oxyhydrogen synthesis method, wherein the oxidation temperature is 1080 ℃, t=9h, and the thickness T OX =1.5 mu m;
Step S4, N-type isolation region photoetching
Forming isolation region windows on the upper and lower surfaces of the silicon wafer simultaneously by using an isolation region photoetching plate and a double-sided photoetching machine;
Step S5, N-type isolation region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, firstly carrying out phosphorus pre-deposition diffusion doping at the windows of isolation areas on two sides of a silicon wafer, wherein the pre-deposition temperature is 1170 ℃, the pre-deposition time is 6h, the diffusion square resistance is 0.5 omega/≡, and the two phosphorus diffusion areas on two sides are connected together to form an isolation area through long-time re-diffusion push junction, and the re-diffusion temperature is 1273 ℃ and the time is 140h;
step S6, anodic P+ region lithography
Forming a P+ region diffusion window on the upper surface of the silicon wafer by utilizing an anode P+ region photoetching plate;
Step S7, anode P+ region diffusion
Adopting a boron liquid source diffusion method, carrying out boron diffusion doping on a P+ region diffusion window on the upper surface of a silicon wafer, pre-depositing at 1100 ℃ for 3 hours, diffusing square resistance 15 omega/≡and then diffusing at 1205 ℃ for 5 hours;
Step S8, anode N+ region photoetching
Forming an anode N+ region diffusion window on the upper surface of the silicon wafer by utilizing an anode N+ region photoetching plate;
step S9, anode N+ region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, carrying out phosphorus diffusion doping on an anode N+ region diffusion window on the upper surface of a silicon wafer, pre-depositing at 1150 ℃ for 3 hours, diffusing square resistance at 0.8Ω/≡, and diffusing at 1255 ℃ for 12 hours;
step S10, cathodic N+ region lithography
Forming a cathode N+ region diffusion window on the lower surface of the silicon wafer by utilizing a photoetching principle;
step S11, cathode N+ region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, carrying out phosphorus diffusion doping on a cathode N+ region diffusion window on the lower surface of a silicon wafer, pre-depositing at 1100 ℃ for 2h, diffusing square resistance 2Ω/≡, and diffusing at 1205 ℃ for 5h;
Step S12, lead hole photoetching
Forming a metal ohmic contact window on the upper surface and the lower surface of the silicon wafer by utilizing a photoetching principle;
Step S13, aluminum steaming
Evaporating a metal aluminum layer with the thickness of 7 mu m on the upper surface of the silicon wafer;
Step S14, aluminum back etching
Forming a metal aluminum electrode region on the upper surface of the silicon wafer by utilizing a photoetching principle;
Step S15, back side metallization
Evaporating a titanium-nickel-silver composite metal layer on the lower surface of the silicon wafer, wherein the thicknesses of the titanium-nickel-silver composite metal layer and the silicon wafer are respectively titanium layersNickel layerSilver layer/>And alloying at 514 ℃ for 45min to form an easy-to-weld layer.
According to the unidirectional TVS device, the NPN triode is integrated in the traditional unidirectional TVS diode, the reverse breakdown negative resistance effect of the NPN triode is utilized, so that the clamping voltage of the unidirectional TVS device can be effectively reduced when the surge current is increased, a protected circuit can normally work, the service life of the circuit is prolonged, the possibility of damage or misoperation of a rear-end circuit is reduced, and the safety of the circuit is improved.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims.
Claims (1)
1. A method of manufacturing a low clamp voltage unidirectional TVS device, the method comprising the steps of:
Step S1, substrate preparation
Selecting a P-type silicon single crystal wafer with the thickness of 260+/-5 mu m;
Step S2, polishing
Polishing the silicon single crystal wafer to a thickness of 200+/-5 mu m by adopting a chemical mechanical polishing method;
Step S3, oxidizing
Growing a silicon dioxide insulating layer on the surface of a silicon wafer by adopting an oxyhydrogen synthesis method, wherein the oxidation temperature is 1000-1100 ℃, t=5-10 h, and the thickness TOX of the oxide layer is=1.2-1.5 mu m;
Step S4, N-type isolation region photoetching
Forming isolation region windows on the upper and lower surfaces of the silicon wafer simultaneously by using an isolation region photoetching plate and a double-sided photoetching machine;
Step S5, N-type isolation region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, firstly carrying out phosphorus pre-deposition diffusion doping at the windows of isolation areas on two sides of a silicon wafer at the same time, wherein the pre-deposition temperature is 1100-1170 ℃, the pre-deposition time is 2-6 h, the diffusion square resistance is 0.1-0.5 omega/≡, the two phosphorus diffusion areas on two sides are connected together to form an isolation area through long-time re-diffusion push junction, and the re-diffusion temperature is 1270+/-5 ℃ for 80-140 h;
step S6, anodic P+ region lithography
Forming a P+ region diffusion window on the upper surface of the silicon wafer by utilizing an anode P+ region photoetching plate;
Step S7, anode P+ region diffusion
Adopting a boron liquid source diffusion method, carrying out boron diffusion doping on a P+ region diffusion window on the upper surface of a silicon wafer, wherein the pre-deposition temperature is 1000-1100 ℃, the pre-deposition time is 1-3 h, the diffusion square resistance is 5-15 omega/≡and the diffusion temperature is 1200+/-5 ℃ for 3-5 h;
Step S8, anode N+ region photoetching
Forming an anode N+ region diffusion window on the upper surface of the silicon wafer by utilizing an anode N+ region photoetching plate;
step S9, anode N+ region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, carrying out phosphorus diffusion doping on an anode N+ region diffusion window on the upper surface of a silicon wafer, wherein the pre-deposition temperature is 1100-1150 ℃, the pre-deposition time is 2-3 h, the diffusion square resistance is 0.5-0.8Ω/≡, and the diffusion temperature is 1250+/-5 ℃ for 10-12 h;
step S10, cathodic N+ region lithography
Forming a cathode N+ region diffusion window on the lower surface of the silicon wafer by utilizing a photoetching principle;
step S11, cathode N+ region diffusion
Adopting a phosphorus oxychloride liquid source diffusion method, carrying out phosphorus diffusion doping on a cathode N+ region diffusion window on the lower surface of a silicon wafer, wherein the pre-deposition temperature is 1000-1100 ℃, the pre-deposition time is 1.5-2 h, the diffusion square resistance is 1.5-2 Ω/≡, and the diffusion temperature is 1200+/-5 ℃ for 2h-5h;
Step S12, lead hole photoetching
Forming a metal ohmic contact window on the upper surface and the lower surface of the silicon wafer by utilizing a photoetching principle;
Step S13, aluminum steaming
Evaporating a metal aluminum layer with the thickness of 5+/-2 mu m on the upper surface of the silicon wafer;
Step S14, aluminum back etching
Forming a metal aluminum electrode region on the upper surface of the silicon wafer by utilizing a photoetching principle;
Step S15, back side metallization
Evaporating a titanium nickel silver composite metal layer on the lower surface of the silicon wafer, and alloying the titanium nickel silver layer and the nickel silver layer in the thickness direction at the temperature of 510+/-5 ℃ for 30-45min so as to form an easy-to-weld layer.
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