CN111933718A - Novel low-capacitance TVS structure and manufacturing method thereof - Google Patents
Novel low-capacitance TVS structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN111933718A CN111933718A CN202010954549.XA CN202010954549A CN111933718A CN 111933718 A CN111933718 A CN 111933718A CN 202010954549 A CN202010954549 A CN 202010954549A CN 111933718 A CN111933718 A CN 111933718A
- Authority
- CN
- China
- Prior art keywords
- layer
- resistance
- doping
- doping layer
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 238000005516 engineering process Methods 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims description 13
- 230000008901 benefit Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention is suitable for the technical field of semiconductors, and provides a novel low-capacitance TVS structure and a manufacturing method thereof, wherein the novel low-capacitance TVS structure comprises a high-resistance substrate, the high-resistance substrate forms a first doping layer and a high-resistance layer positioned above the first doping layer through a triple diffusion process, the high-resistance layer is provided with a groove isolation structure, the groove isolation structure divides the high-resistance layer into a left channel, a middle channel and a right channel, the middle channel forms a second doping layer, a well region is formed in the right channel, and third doping layers are formed in the well region, the left channel and the middle channel; compared with the high-resistance layer obtained by an epitaxial technology, the method has the advantages of small realization difficulty and low manufacturing cost, and the formed TVS structure has the performances of low capacitance and high surge.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a novel low-capacitance TVS structure and a manufacturing method thereof.
Background
At present, the integration level of electronic products is higher and higher, and the size is smaller and smaller, the impact resistance of functional modules against surge, ESD and the like is weakened, and the increase of protection devices in related interfaces and circuits is a necessary trend. In order to prevent data distortion, strict requirements are imposed on the capacitance of a protective device for protecting a communication interface, the capacitance of the protective device is generally required to be less than 1uA, and the capacitance of the protective device is required to be smaller when the frequency of the communication interface is higher. A low-capacitance TVS (Transient Voltage Suppressor) is a protection device specially used for communication interface protection.
Taking a unidirectional low-capacitance TVS as an example, a TVS structure with strong surge resistance is mainly used in series with a low-capacitance diode to realize low capacitance. Wherein the low capacitance diode is realized by a PN junction prepared on a P type or N type high resistance layer.
At present, the traditional low-capacitance TVS device is used for forming a high-resistance layer of a low-capacitance diode structure, which is realized by growing a high-resistance epitaxial layer on a low-resistance substrate, and then preparing a low-capacitance diode on the high-resistance epitaxial layer. The high-resistance epitaxy is grown on the low-resistance substrate, so that the difficulty is very high, the epitaxy can be realized only by means of inhibiting the substrate from self-doping, and the manufacturing cost of the high-resistance layer structure obtained by growing the high-resistance epitaxy on the low-resistance substrate is high.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiencies in the prior art, and provides a novel low-capacitance TVS structure with low manufacturing cost and a manufacturing method thereof.
The invention provides a novel low-capacitance TVS structure which comprises a high-resistance substrate, wherein a first doping layer and a high-resistance layer positioned above the first doping layer are formed on the high-resistance substrate through a triple diffusion process, a plurality of groove isolation structures are arranged on the high-resistance layer, the high-resistance layer is divided into a left channel, a middle channel and a right channel by the groove isolation structures, a second doping layer is formed on the middle channel, a well region is formed in the right channel, and third doping layers are formed in the well region, the left channel and the middle channel.
Further, the high-resistance substrate is a P-high-resistance substrate, the high-resistance layer is a P-high-resistance layer, the first doping layer and the second doping layer are both N + doping layers, the third doping layer is a P + doping layer, and the well region is an N well region.
Further, the high-resistance substrate is an N-high-resistance substrate, the high-resistance layer is an N-high-resistance layer, the first doping layer and the second doping layer are P + doping layers, the third doping layer is an N + doping layer, and the well region is a P well region.
Further, the right channel is filled with N-type poly to form the N well region; or the right channel is filled with P-type poly to form the P well region.
Further, the bottom end of the trench isolation structure penetrates through the high-resistance substrate to reach the inside of the first doping layer.
Furthermore, the trench isolation structure is provided with lead holes on a third doping layer on the left channel, a third doping layer and a second doping layer on the middle channel, and a third doping layer on the right channel; and the third doping layer on the left channel, the second doping layer on the middle channel, the third doping layer on the middle channel and the third doping layer on the right channel are electrically connected through the lead holes.
Further, the thickness of the high-resistance substrate is smaller than 100 um.
The invention also provides a manufacturing method of the novel low-capacitance TVS structure, which comprises the following steps:
s1, forming first doped layers on the front surface and the back surface of the high-resistance substrate through a triple diffusion process on the high-resistance substrate, and reserving the first doped layers on the back surface of the high-resistance substrate through a thinning process so as to form a high-resistance layer;
s2, forming a trench isolation structure on the high-resistance layer, wherein the trench isolation structure penetrates through the high-resistance substrate and reaches the first doping layer on the back of the high-resistance substrate, so that the high-resistance substrate is isolated to form a left channel, a middle channel and a right channel, and a well region is formed in the right channel;
s3, forming a second doped layer on the high-resistance layer of the middle channel to form a low-capacitance diode;
s4, forming third doped layers on the high-resistance layers of the left channel and the middle channel respectively, wherein the third doped layers are used for forming ohmic contact with subsequent electrodes, and forming third doped layers on the well region of the right channel;
s5, arranging lead holes on the third doping layer on the left channel and the second doping layer on the middle channel, and enabling the left channel and the middle channel to form ohmic contact with the electrode metal through the lead holes; lead holes are also formed in the third doping layer on the middle channel and the third doping layer on the right channel and used for forming metal interconnection with the third doping layers of the middle channel and the right channel through the lead holes in a follow-up mode;
s6, forming a front electrode above the third doping layer of the left channel and the second doping layer on the middle channel, and forming metal leads above the third doping layer on the middle channel and the third doping layer on the right channel for interconnection;
and S7, forming a back electrode on the back surface of the first doped layer.
Further, the high-resistance substrate is a P-high-resistance substrate, the high-resistance layer is a P-high-resistance layer, the first doping layer and the second doping layer are both N + doping layers, the third doping layer is a P + doping layer, the well region is an N well region, and N-type poly is filled in the right channel to form the N well region.
Further, the high-resistance substrate is an N-high-resistance substrate, the high-resistance layer is an N-high-resistance layer, the first doping layer and the second doping layer are P + doping layers, the third doping layer is an N + doping layer, the well region is a P well region, and P-type poly is filled in the right channel to form the P well region.
According to the novel low-capacitance TVS structure with low manufacturing cost and the manufacturing method thereof, the high-resistance layer is formed in a triple diffusion process mode to obtain the ultra-low-capacitance TVS structure, compared with the high-resistance layer obtained by an epitaxial technology, the method is low in implementation difficulty and low in manufacturing cost, and the formed TVS structure has low capacitance and high surge performance.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
The drawings are only for purposes of illustrating and explaining the present invention and are not to be construed as limiting the scope of the present invention.
Fig. 1 is a schematic structural diagram of a low-capacitance TVS structure according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a low-capacitance TVS structure according to another embodiment of the present invention.
The reference numbers illustrate: 1. a high-resistance substrate; 2. a first doped layer; 3. a high resistance layer; 4. a trench isolation structure; 5. a left channel; 6. a middle channel; 7. a right channel; 8. a second doped layer; 9. a well region; 10. a third doped layer; 11. and a lead hole.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1 to 2, a novel low-capacitance TVS structure disclosed in the present invention includes a high-resistance substrate 1, a first doped layer 2 and a high-resistance layer 3 located above the first doped layer 2 are formed on the high-resistance substrate 1 through a triple diffusion process, the thickness of the high-resistance layer 3 is less than 100 μm, and the thickness can effectively improve the control capability of a subsequent production line, so as to obtain a good high-resistance layer 3.
The high-resistance layer 3 is provided with a plurality of trench isolation structures 4, the bottom ends of the trench isolation structures 4 penetrate through the high-resistance substrate 1 and reach the inside of the first doped layer 2, the trench isolation structures 4 divide the high-resistance layer 3 into a plurality of channels, preferably but not limited to a left channel 5, a middle channel 6 and a right channel 7, and the middle channel 6 is formed with a second doped layer 8, so that a low-capacitance diode is formed.
And a well region 9 is formed in the right channel 7, and the well region 9 can provide a low-resistance channel, reduce power loss and improve surge characteristics.
The invention also provides a manufacturing method of the novel low-capacitance TVS structure, which comprises the following steps:
s1, forming first doping layers 2 on the front side and the back side of the high-resistance substrate 1 through a triple diffusion process on the high-resistance substrate 1, and reserving the first doping layers 2 on the back side of the high-resistance substrate through thinning, polishing and other processes to form a high-resistance layer 3, wherein the thickness of the high-resistance layer 3 is smaller than 100 microns, the thickness can effectively improve the control capability of a production line, a good high-resistance layer 3 structure can be obtained through the triple diffusion process, the cost of the triple diffusion process is low, and the economic benefit is improved;
s2, forming a trench isolation structure 4 on the high-resistance layer 3 through technologies such as oxidation, photoetching, trench etching, SiO2 filling and the like, wherein the trench isolation structure 4 penetrates through the high-resistance substrate 1 and reaches the first doping layer 2 on the back of the high-resistance substrate 1, so that the high-resistance substrate 1 is isolated to form a left channel 5, a middle channel 6 and a right channel 7, and a well region 9 is formed in the right channel 7, wherein the well region 9 is used for providing a low-resistance channel for large current after TVS reverse breakdown, reducing power loss and improving surge characteristics;
s3, forming a second doping layer 8 on the high-resistance layer 3 of the middle channel 6 through technologies such as photoetching, corrosion, injection, annealing and the like to form a low-capacitance diode;
s4, forming third doping layers 10 on the high-resistance layers 3 of the left channel 5 and the middle channel 6 respectively through technologies such as photoetching, corrosion, injection, annealing and the like for forming ohmic contact with subsequent electrodes, and forming the third doping layers 10 on the well region 9 of the right channel to form a TVS structure with high surge capacity;
s5, forming lead holes 11 on the third doped layer 10 on the left channel 5 and the second doped layer 8 on the middle channel 6 through photolithography and etching processes, for forming ohmic contacts with the left channel 5 and the middle channel 6 and the electrode metal through the lead holes 11; lead holes 11 are also formed in the third doping layer 10 on the middle channel 6 and the third doping layer 10 of the right channel 7 and are used for forming metal interconnection with the third doping layers 10 of the middle channel 6 and the right channel 7 through the lead holes 11 in a subsequent process, so that a low-capacitance diode is connected with the TVS in series, and low-capacitance and high-surge performance of the device is achieved;
s6, forming front electrodes above the third doping layer 10 of the left channel 5 and the second doping layer 8 on the middle channel 6 through sputtering or evaporation, metal photoetching, etching and other technologies, and forming metal leads above the third doping layer 10 on the middle channel 6 and the third doping layer 10 of the right channel 7 for interconnection;
and S7, forming a back electrode on the back of the first doping layer 2 by thinning, back evaporation and other technologies so as to communicate the whole TVS structure.
If the front electrode is negatively biased, the left channel 5 is reversely biased and has higher voltage resistance, and the current preferably flows through a lower voltage-resistant channel, namely, the current flows in from the back electrode, flows through a TVS structure reversely biased by the right channel, the metal leads of the right channel 7 and the middle channel 6 are interconnected and transversely flow into the middle channel 6, and then flows out from the front electrode through a low-capacitance diode which is forwardly biased by the middle channel 6, the low-capacitance diode of the middle channel 6 is connected in series with the TVS of the right channel 7, and in addition, if the front electrode is positively biased, the reverse bias voltage of the low-capacitance diode which is connected in series with the middle channel 6 and the right channel 7 is higher, so the current preferably flows through the left channel 5 which is forwardly biased after flowing in from the front electrode and flows out from the back electrode, and the performances of low capacitance.
In an embodiment of the present application, as shown in fig. 1, the high resistance substrate 1 is a P-high resistance substrate 1, the high resistance layer 3 is a P-high resistance layer, the first doping layer 2 and the second doping layer 8 are both N + doping layers, the third doping layer 10 is a P + doping layer, the well region 9 is an N well region, and for the N well region, preferably but not limited to, the right channel 7 is filled with N-type poly to form the N well region.
In other embodiments of the present application, as shown in fig. 2, the high resistance substrate 1 may be an N-high resistance substrate 1, the high resistance layer 3 is an N-high resistance layer, the first doping layer 2 and the second doping layer 8 are both P + doping layers, the third doping layer 10 is an N + doping layer, the well region 9 is a P well region, and for the P well region, preferably, but not limited to, the right channel 7 is filled with P-type poly to form the P well region.
The present invention is not limited to the above preferred embodiments, and any modification, equivalent replacement or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A novel low electric capacity TVS structure which characterized in that: including high resistant substrate (1), be formed with first doping layer (2) and be located high resistance layer (3) of first doping layer (2) top through triple diffusion technology on high resistant substrate (1), be equipped with a plurality of trench isolation structure (4), a plurality of on high resistance layer (3) trench isolation structure (4) divide into left passageway (5), intermediate passage (6) and right passageway (7) with high resistance layer (3), intermediate passage (6) are formed with second doping layer (8), be formed with well region (9) in right side passageway (7), all be formed with third doping layer (10) in well region (9), left side passageway (5) and intermediate passage (6).
2. The novel low capacitance TVS structure of claim 1, wherein: the high-resistance substrate (1) is a P-high-resistance substrate, the high-resistance layer (3) is a P-high-resistance layer, the first doping layer (2) and the second doping layer (8) are both N + doping layers, the third doping layer (10) is a P + doping layer, and the well region (9) is an N well region.
3. The novel low capacitance TVS structure of claim 1, wherein: the high-resistance substrate (1) is an N-high-resistance substrate, the high-resistance layer (3) is an N-high-resistance layer, the first doping layer (2) and the second doping layer (8) are P + doping layers, the third doping layer (10) is an N + doping layer, and the well region (9) is a P well region.
4. The TVS structure of claim 2, wherein: the right channel (7) is filled with N-type poly to form the N well region; or,
the right channel (7) is filled with P-type poly to form the P well region.
5. A novel low capacitance TVS structure as claimed in claim 2 or 3, wherein: the bottom end of the trench isolation structure (4) penetrates through the high-resistance substrate (1) to reach the interior of the first doping layer (2).
6. A novel low capacitance TVS structure as claimed in claim 2 or 3, wherein: the groove isolation structure (4) is provided with lead holes (11) on the third doping layer (10) on the left channel (5), the third doping layer (10) and the second doping layer (8) on the middle channel (6) and the third doping layer (10) on the right channel (7);
and the third doped layer (10) on the left channel (5), the second doped layer (8) on the middle channel (6), the third doped layer (10) on the middle channel (6) and the third doped layer (10) on the right channel (7) are electrically connected through the lead holes (11).
7. The novel low capacitance TVS structure of claim 1, wherein: the thickness of the high-resistance layer (3) is less than 100 um.
8. A manufacturing method of a novel low-capacitance TVS structure is characterized by comprising the following steps: the method comprises the following steps:
s1, forming first doping layers (2) on the front surface and the back surface of the high-resistance substrate (1) through a triple diffusion process on the high-resistance substrate (1), and reserving the first doping layers (2) on the back surface of the high-resistance substrate through a thinning process to form a high-resistance layer (3);
s2, forming a trench isolation structure (4) on the high-resistance layer (3), wherein the trench isolation structure (4) penetrates through the high-resistance substrate (1) to reach the first doping layer (2) on the back of the high-resistance substrate (1), so that the high-resistance layer (3) is isolated to form a left channel (5), a middle channel (6) and a right channel (7), and a well region (9) is formed in the right channel (7);
s3, forming a second doped layer (8) on the high-resistance layer (3) of the middle channel (6) to form a low-capacitance diode;
s4, forming a third doping layer (10) on the high-resistance layer (3) of the left channel (5) and the middle channel (6) respectively for forming ohmic contact with a subsequent electrode, and forming the third doping layer (10) on the well region (9) of the right channel;
s5, arranging lead holes (11) in the third doped layer (10) on the left channel (5) and the second doped layer (8) on the middle channel (6) for forming ohmic contact with the left channel (5) and the middle channel (6) and the electrode metal through the lead holes (11) in the following process; lead holes (11) are also formed in the third doping layer (10) on the middle channel (6) and the third doping layer (10) of the right channel (7) and are used for forming metal interconnection with the third doping layer (10) of the middle channel (6) and the right channel (7) through the lead holes (11);
s6, forming a front electrode above the third doping layer (10) of the left channel (5) and the second doping layer (8) on the middle channel (6), and simultaneously forming metal lead interconnection above the third doping layer (10) on the middle channel (6) and the third doping layer (10) of the right channel (7);
and S7, forming a back electrode on the back surface of the first doping layer (2).
9. The method of claim 8, wherein the step of forming the TVS structure further comprises: the high-resistance substrate (1) is a P-high-resistance substrate, the high-resistance layer (3) is a P-high-resistance layer, the first doping layer (2) and the second doping layer (8) are N + doping layers, the third doping layer (10) is a P + doping layer, the well region (9) is an N well region, and N-type poly is filled in the right channel (7) to form the N well region.
10. The method of claim 8, wherein the step of forming the TVS structure further comprises: the high-resistance substrate (1) is an N-high-resistance substrate, the high-resistance layer (3) is an N-high-resistance layer, the first doping layer (2) and the second doping layer (8) are P + doping layers, the third doping layer (10) is an N + doping layer, the well region (9) is a P well region, and P type poly is filled in the right channel (7) to form the P well region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010954549.XA CN111933718A (en) | 2020-09-11 | 2020-09-11 | Novel low-capacitance TVS structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010954549.XA CN111933718A (en) | 2020-09-11 | 2020-09-11 | Novel low-capacitance TVS structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111933718A true CN111933718A (en) | 2020-11-13 |
Family
ID=73309356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010954549.XA Pending CN111933718A (en) | 2020-09-11 | 2020-09-11 | Novel low-capacitance TVS structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111933718A (en) |
-
2020
- 2020-09-11 CN CN202010954549.XA patent/CN111933718A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101394913B1 (en) | Latch-Up Free Vertical TVS Diode Array Structure Using Trench Isolation | |
| US10037987B2 (en) | Semiconductor structure of ESD protection device and method for manufacturing the same | |
| CN102867857B (en) | Semiconductor device and method for manufacturing the same | |
| CN105186478A (en) | Transient voltage suppressor | |
| US11233045B2 (en) | Transient voltage suppression device and manufacturing method therefor | |
| CN107919355B (en) | Ultralow-residual-voltage low-capacity transient voltage suppressor and manufacturing method thereof | |
| CN204885150U (en) | Transient voltage inhibitor encapsulation subassembly | |
| CN105185782A (en) | Capacitive diode assembly and manufacturing method of the capacitive diode assembly | |
| CN106169508B (en) | Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof | |
| CN106158851B (en) | Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof | |
| JP2015126149A (en) | Low capacity semiconductor device and method of manufacturing the same | |
| CN204886173U (en) | Transient voltage inhibitor | |
| JP2022132663A (en) | Tvs diode and assembly having asymmetric breakdown voltage | |
| CN212676278U (en) | Novel low-capacitance TVS structure | |
| CN108428699B (en) | TVS device with bidirectional large snapback SCR (selective catalytic reduction) characteristic and ultra-low capacitance and manufacturing method thereof | |
| CN111933718A (en) | Novel low-capacitance TVS structure and manufacturing method thereof | |
| KR101006768B1 (en) | Structure of a tvs diode array and its fabrication method | |
| CN206301790U (en) | A kind of two-way ultra-low capacitance Transient Voltage Suppressor | |
| US8704270B2 (en) | Shockley diode having a low turn-on voltage | |
| CN205092242U (en) | Capacitive diode cluster spare | |
| CN105185783A (en) | Capacitive diode assembly and manufacturing method of the capacitive diode assembly | |
| CN108198812B (en) | Transient voltage suppressor and method of manufacturing the same | |
| KR100945626B1 (en) | Transient voltage suppressor circuit | |
| CN205016525U (en) | Capacitive diode cluster spare | |
| CN110600468B (en) | TVS device with ultralow residual voltage drop capacity tube and SCR (selective catalytic reduction) characteristic and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Country or region after: China Address after: 518000 406, building A1, Fuhai information port, Qiaotou community, Fuhai street, Bao'an District, Shenzhen City, Guangdong Province Applicant after: Shenzhen Hongtai Microelectronics Co.,Ltd. Address before: 518000 406, building A1, Fuhai information port, Qiaotou community, Fuhai street, Bao'an District, Shenzhen City, Guangdong Province Applicant before: Shenzhen Hongtai integrated circuit technology Co.,Ltd. Country or region before: China |
|
| CB02 | Change of applicant information | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20240613 Address after: 528300 No. 13 Guangjiao Industrial Avenue, Guangjiao Community, Beijiao Town, Shunde District, Foshan City, Guangdong Province (Residence application) Applicant after: Foshan Xinzhantong Electronics Co.,Ltd. Country or region after: China Address before: 518000 406, building A1, Fuhai information port, Qiaotou community, Fuhai street, Bao'an District, Shenzhen City, Guangdong Province Applicant before: Shenzhen Hongtai Microelectronics Co.,Ltd. Country or region before: China |
|
| TA01 | Transfer of patent application right |