CN111933718A - Novel low-capacitance TVS structure and manufacturing method thereof - Google Patents

Novel low-capacitance TVS structure and manufacturing method thereof Download PDF

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CN111933718A
CN111933718A CN202010954549.XA CN202010954549A CN111933718A CN 111933718 A CN111933718 A CN 111933718A CN 202010954549 A CN202010954549 A CN 202010954549A CN 111933718 A CN111933718 A CN 111933718A
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王洋
施锦源
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Foshan Xinzhantong Electronics Co ltd
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Shenzhen Hongtai Integrated Circuit Technology Co ltd
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Abstract

本发明适用于半导体技术领域,提供了一种新型低电容TVS结构及其制作方法,该新型低电容TVS结构包括高阻衬底,高阻衬底通过三重扩散工艺形成第一掺杂层及位于第一掺杂层上方的高阻层,高阻层设有沟槽隔离结构,所述沟槽隔离结构将高阻层分为左通道、中间通道和右通道,中间通道形成第二掺杂层,右通道内形成阱区,阱区内、左通道和中间通道内均形成第三掺杂层;采用三重扩散工艺的方式形成高阻层,获得超低电容TVS结构,相对于外延技术获得的高阻层,本发明所述方法实现难度小且制作成本低,所形成的TVS结构具有低电容和高浪涌的性能。

Figure 202010954549

The invention is applicable to the field of semiconductor technology, and provides a novel low-capacitance TVS structure and a manufacturing method thereof. The novel low-capacitance TVS structure includes a high-resistance substrate, and the high-resistance substrate forms a first doped layer through a triple diffusion process and is located in the high-resistance substrate. A high-resistance layer above the first doped layer, the high-resistance layer is provided with a trench isolation structure, and the trench isolation structure divides the high-resistance layer into a left channel, a middle channel and a right channel, and the middle channel forms the second doped layer , a well region is formed in the right channel, and a third doped layer is formed in the well region, the left channel and the middle channel; a high-resistance layer is formed by a triple diffusion process to obtain an ultra-low capacitance TVS structure. For the high resistance layer, the method of the present invention is less difficult to implement and has low manufacturing cost, and the formed TVS structure has the properties of low capacitance and high surge.

Figure 202010954549

Description

一种新型低电容TVS结构及其制作方法A novel low-capacitance TVS structure and its fabrication method

技术领域technical field

本发明属于半导体技术领域,具体涉及到一种新型低电容TVS结构及其制作方法。The invention belongs to the technical field of semiconductors, and specifically relates to a novel low-capacitance TVS structure and a manufacturing method thereof.

背景技术Background technique

当下电子产品集成度越来越高,尺寸越做越小,功能模块抗浪涌、ESD等冲击能力随之变弱,在相关接口及电路内部增加保护器件已成必然趋势。其中,为防止数据失真,对用于通讯接口保护的防护器件的电容有着严格要求,此类防护器件普遍要求电容要小于1uA,且通讯接口频率越高,要求其电容越小。低电容TVS(Transient Voltage Suppressor,瞬态抑制二极管)是一种专门用于通讯接口保护的防护器件。Nowadays, the integration of electronic products is getting higher and higher, and the size is getting smaller and smaller, and the ability of functional modules to resist surge, ESD and other shocks is weakened. It has become an inevitable trend to add protection devices in related interfaces and circuits. Among them, in order to prevent data distortion, there are strict requirements on the capacitance of protective devices used for communication interface protection. Such protective devices generally require a capacitance of less than 1uA, and the higher the frequency of the communication interface, the smaller the capacitance is required. Low-capacitance TVS (Transient Voltage Suppressor, transient suppression diode) is a protection device specially used for communication interface protection.

以单向低电容TVS为例,主要采用抗浪涌能力较强的TVS结构与低容二极管串联的方式实现低电容。其中低容二极管是通过在P型或N型高阻层上制备的PN结来实现的。Taking a unidirectional low-capacitance TVS as an example, a TVS structure with strong anti-surge capability is mainly used in series with a low-capacitance diode to achieve low-capacitance. The low-capacitance diode is realized by a PN junction prepared on a P-type or N-type high-resistance layer.

目前传统低电容TVS器件用来形成低容二极管结构的高阻层,都是通过在低阻衬底上生长高阻外延层来实现的,再在高阻外延层上制备低电容二极管。由于在低阻衬底生长高阻外延,难度非常大,需要通过一些特殊抑制衬底自掺杂的手段才能实现,这种在低阻衬底生长高阻外延层获得的高阻层结构的制造成本较高。At present, traditional low-capacitance TVS devices are used to form high-resistance layers of low-capacitance diode structures by growing high-resistance epitaxial layers on low-resistance substrates, and then preparing low-capacitance diodes on the high-resistance epitaxial layers. Because it is very difficult to grow high-resistance epitaxy on a low-resistance substrate, it needs some special means to suppress the self-doping of the substrate. higher cost.

发明内容SUMMARY OF THE INVENTION

本发明的目的在于克服上述现有技术的不足,提供了一种低制作成本的新型低电容TVS结构及其制作方法。The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art, and to provide a novel low-capacitance TVS structure with low manufacturing cost and a manufacturing method thereof.

本发明提供了一种新型低电容TVS结构,包括高阻衬底,所述高阻衬底上通过三重扩散工艺形成有第一掺杂层及位于第一掺杂层上方的高阻层,所述高阻层上设有若干个沟槽隔离结构,若干个所述沟槽隔离结构将高阻层分为左通道、中间通道和右通道,所述中间通道形成有第二掺杂层,所述右通道内形成有阱区,所述阱区内、左通道和中间通道内均形成有第三掺杂层。The present invention provides a novel low-capacitance TVS structure, including a high-resistance substrate on which a first doped layer and a high-resistance layer located above the first doped layer are formed through a triple diffusion process, so the The high-resistance layer is provided with a plurality of trench isolation structures, the plurality of trench isolation structures divide the high-resistance layer into a left channel, a middle channel and a right channel, and the middle channel is formed with a second doped layer, so A well region is formed in the right channel, and a third doped layer is formed in the well region, the left channel and the middle channel.

进一步的,所述高阻衬底为P-高阻衬底,所述高阻层为P-高阻层,所述第一掺杂层和第二掺杂层均为N+掺杂层,所述第三掺杂层为P+掺杂层,所述阱区为N阱区。Further, the high-resistance substrate is a P-high-resistance substrate, the high-resistance layer is a P-high-resistance layer, the first doped layer and the second doped layer are both N+ doped layers, so The third doping layer is a P+ doping layer, and the well region is an N well region.

进一步的,所述高阻衬底为N-高阻衬底,所述高阻层为N-高阻层,所述第一掺杂层和第二掺杂层均为P+掺杂层,所述第三掺杂层为N+掺杂层,所述阱区为P阱区。Further, the high-resistance substrate is an N-high-resistance substrate, the high-resistance layer is an N-high-resistance layer, and the first doped layer and the second doped layer are both P+ doped layers, so The third doping layer is an N+ doping layer, and the well region is a P well region.

进一步的,所述右通道内填充有N型poly以形成所述N阱区;或者,所述右通道内填充有P型poly以形成所述P阱区。Further, the right channel is filled with N-type poly to form the N-well region; or, the right channel is filled with P-type poly to form the P-well region.

进一步的,所述沟槽隔离结构的底端穿过所述高阻衬底到达所述第一掺杂层的内部。Further, the bottom end of the trench isolation structure passes through the high resistance substrate to reach the inside of the first doped layer.

进一步的,所述沟槽隔离结构在所述左通道上的第三掺杂层、中间通道上的第三掺杂层和第二掺杂层、右通道上的第三掺杂层上均开设有引线孔;所述左通道上的第三掺杂层和中间通道上的第二掺杂层、所述中间通道上的第三掺杂层和右通道上的第三掺杂层均通过所述引线孔电连接。Further, the trench isolation structure is provided on the third doped layer on the left channel, the third doped layer and the second doped layer on the middle channel, and the third doped layer on the right channel. There are lead holes; the third doped layer on the left channel and the second doped layer on the middle channel, the third doped layer on the middle channel and the third doped layer on the right channel all pass through all the The lead holes are electrically connected.

进一步的,所述高阻衬底的厚度小于100um。Further, the thickness of the high resistance substrate is less than 100um.

本发明还提供了形成上述一种新型低电容TVS结构的一种新型低电容TVS结构的制作方法,包括如下步骤:The present invention also provides a manufacturing method of a novel low-capacitance TVS structure for forming the above-mentioned novel low-capacitance TVS structure, comprising the following steps:

S1、在高阻衬底上,通过三重扩散工艺在高阻衬底的正面和背面均形成第一掺杂层,通过剪薄工艺,保留阻衬底背面的第一掺杂层,从而形成高阻层;S1. On the high-resistance substrate, a first doped layer is formed on both the front and the back of the high-resistance substrate through a triple diffusion process, and the first doped layer on the back of the resistive substrate is retained through a thinning process, thereby forming a high-resistance substrate. barrier layer;

S2、在高阻层上形成沟槽隔离结构,沟槽隔离结构穿过高阻衬底到达高阻衬底背面的第一掺杂层中,从而将高阻衬底隔离形成左通道、中间通道和右通道,并在右通道内形成阱区;S2. A trench isolation structure is formed on the high-resistance layer, and the trench isolation structure passes through the high-resistance substrate and reaches the first doped layer on the back of the high-resistance substrate, thereby isolating the high-resistance substrate to form a left channel and a middle channel and the right channel, and a well region is formed in the right channel;

S3、在中间通道的高阻层上形成第二掺杂层,以形成低电容二极管;S3, forming a second doped layer on the high-resistance layer of the middle channel to form a low-capacitance diode;

S4、分别在左通道和中间通道的高阻层上形成第三掺杂层,用于与后续电极形成欧姆接触,在右侧通道的阱区上也形成第三掺杂层;S4, respectively forming a third doped layer on the high-resistance layers of the left channel and the middle channel for forming an ohmic contact with the subsequent electrodes, and also forming a third doped layer on the well region of the right channel;

S5、在所述左通道上的第三掺杂层、中间通道上的第二掺杂层上均开设引线孔,用于与后续通过该引线孔使这左通道、中间通道与电极金属形成欧姆接触;在中间通道上的第三掺杂层和右通道的第三掺杂层也开设引线孔,用于与后续通过该引线孔使中间通道和右通道的第三掺杂层形成金属互联;S5. Lead holes are provided on the third doped layer on the left channel and the second doped layer on the middle channel, so that the left channel, the middle channel and the electrode metal can form ohmic through the lead holes subsequently. contact; lead holes are also provided on the third doped layer on the middle channel and the third doped layer on the right channel, for forming metal interconnection with the third doped layer of the middle channel and the right channel through the lead hole subsequently;

S6、在左通道的第三掺杂层、中间通道上的第二掺杂层上方形成正面电极,同时在中间通道上的第三掺杂层和右通道的第三掺杂层的上方形成金属引线互联;S6. A front electrode is formed over the third doped layer on the left channel and the second doped layer on the middle channel, and a metal is formed on the third doped layer on the middle channel and the third doped layer on the right channel at the same time lead interconnection;

S7、在第一掺杂层的背面形成背面电极。S7, forming a back electrode on the back surface of the first doped layer.

进一步的,所述高阻衬底为P-高阻衬底,所述高阻层为P-高阻层,所述第一掺杂层和第二掺杂层均为N+掺杂层,所述第三掺杂层为P+掺杂层,所述阱区为N阱区,所述右通道内填充有N型poly以形成所述N阱区。Further, the high-resistance substrate is a P-high-resistance substrate, the high-resistance layer is a P-high-resistance layer, the first doped layer and the second doped layer are both N+ doped layers, so The third doped layer is a P+ doped layer, the well region is an N well region, and the right channel is filled with N-type poly to form the N well region.

进一步的,所述高阻衬底为N-高阻衬底,所述高阻层为N-高阻层,所述第一掺杂层和第二掺杂层均为P+掺杂层,所述第三掺杂层为N+掺杂层,所述阱区为P阱区,所述右通道内填充有P型poly以形成所述P阱区。Further, the high-resistance substrate is an N-high-resistance substrate, the high-resistance layer is an N-high-resistance layer, and the first doped layer and the second doped layer are both P+ doped layers, so The third doped layer is an N+ doped layer, the well region is a P well region, and the right channel is filled with P-type poly to form the P well region.

本发明提供的一种低制作成本的新型低电容TVS结构及其制作方法,采用三重扩散工艺的方式形成高阻层,获得超低电容TVS结构,相对于外延技术获得的高阻层,本发明所述方法实现难度小且制作成本低,所形成的TVS结构具有低电容和高浪涌的性能。The present invention provides a novel low-capacitance TVS structure with low fabrication cost and a fabrication method thereof. A high-resistance layer is formed by a triple diffusion process to obtain an ultra-low-capacitance TVS structure. Compared with the high-resistance layer obtained by epitaxy, the present invention The method is easy to implement and low in manufacturing cost, and the formed TVS structure has the properties of low capacitance and high surge.

附图说明Description of drawings

为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are For some embodiments of the present invention, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

以下附图仅旨在于对本发明做示意性说明和解释,并不限定本发明的范围。The following drawings are only intended to illustrate and explain the present invention schematically, and do not limit the scope of the present invention.

图1是本发明一实施例的低电容TVS结构的结构示意图。FIG. 1 is a schematic structural diagram of a low-capacitance TVS structure according to an embodiment of the present invention.

图2是本发明其他实施例的低电容TVS结构的结构示意图。FIG. 2 is a schematic structural diagram of a low-capacitance TVS structure according to another embodiment of the present invention.

附图标号说明:1、高阻衬底;2、第一掺杂层;3、高阻层;4、沟槽隔离结构;5、左通道;6、中间通道;7、右通道;8、第二掺杂层;9、阱区;10、第三掺杂层;11、引线孔。Description of reference numerals: 1, high resistance substrate; 2, first doped layer; 3, high resistance layer; 4, trench isolation structure; 5, left channel; 6, middle channel; 7, right channel; 8, The second doped layer; 9, the well region; 10, the third doped layer; 11, the lead hole.

具体实施方式Detailed ways

为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

请参阅图1至图2,为发明公开的一种新型低电容TVS结构,包括高阻衬底1,所述高阻衬底1上通过三重扩散工艺形成有第一掺杂层2,及位于第一掺杂层2上方的高阻层3,所述高阻层3的厚度小于100um,该厚度能有效提高后续产线的控制能力,以获得良好的高阻层3。Please refer to FIG. 1 to FIG. 2 , which is a novel low-capacitance TVS structure disclosed by the invention, comprising a high-resistance substrate 1, on which a first doped layer 2 is formed by a triple diffusion process, and is located on the high-resistance substrate 1. The thickness of the high-resistance layer 3 above the first doped layer 2 is less than 100 μm, which can effectively improve the controllability of subsequent production lines to obtain a good high-resistance layer 3 .

所述高阻层3上设有若干个沟槽隔离结构4,所述沟槽隔离结构4的底端穿过所述高阻衬底1到达所述第一掺杂层2的内部,若干个所述沟槽隔离结构4将高阻层3分为若干通道,优选但不限于分为左通道5、中间通道6和右通道7,所述中间通道6形成有第二掺杂层8,以此形成了低电容二极管。The high-resistance layer 3 is provided with a plurality of trench isolation structures 4 , and the bottom ends of the trench isolation structures 4 pass through the high-resistance substrate 1 to the interior of the first doped layer 2 . The trench isolation structure 4 divides the high-resistance layer 3 into several channels, preferably but not limited to a left channel 5, a middle channel 6 and a right channel 7, and the middle channel 6 is formed with a second doped layer 8 to This forms a low capacitance diode.

所述右通道7内形成有阱区9,所述阱区9能提供低阻通道,减少功率损耗,提高浪涌特性。A well region 9 is formed in the right channel 7, and the well region 9 can provide a low-resistance channel, reduce power loss, and improve surge characteristics.

所述阱区9内、左通道5和中间通道6内均形成有第三掺杂层10,待与后续电极形成欧姆接触,形成超高浪涌能力的TVS结构,所述沟槽隔离结构4在所述左通道5上的第三掺杂层10、中间通道6上的第三掺杂层10和第二掺杂层8、右通道7上的第三掺杂层10上均开设有引线孔11,所述左通道5上的第三掺杂层10和中间通道6上的第二掺杂层8通过引线孔11电连接,具体表现为左通道5上的第三掺杂层10和中间通道6上的第二掺杂层8上形成有正面电极,通过引线孔11使这左通道5和中间通道6分别与正面电极形成欧姆接触;所述中间通道6上的第三掺杂层10和右通道7上的第三掺杂层10均通过所述引线孔11电连接,具体表现为在中间通道6上的第三掺杂层10和右通道7上的第三掺杂层10上形成金属引线,通过引线孔11使这中间通道6和右通道7的第三掺杂层10上形成金属互联,使低电容二极管与TVS形成串联,以实现器件低电容与高浪涌性能。A third doped layer 10 is formed in the well region 9, the left channel 5 and the middle channel 6, and is to be in ohmic contact with the subsequent electrodes to form a TVS structure with ultra-high surge capability. The trench isolation structure 4 Leads are provided on the third doped layer 10 on the left channel 5 , the third doped layer 10 and the second doped layer 8 on the middle channel 6 , and the third doped layer 10 on the right channel 7 Hole 11, the third doped layer 10 on the left channel 5 and the second doped layer 8 on the middle channel 6 are electrically connected through the lead hole 11, which is embodied as the third doped layer 10 on the left channel 5 and the second doped layer 8 on the middle channel 6. A front electrode is formed on the second doped layer 8 on the middle channel 6, and the left channel 5 and the middle channel 6 are respectively in ohmic contact with the front electrode through the lead hole 11; the third doped layer on the middle channel 6 10 and the third doped layer 10 on the right channel 7 are electrically connected through the lead holes 11 , specifically the third doped layer 10 on the middle channel 6 and the third doped layer 10 on the right channel 7 A metal lead is formed on the lead hole 11, and metal interconnection is formed on the third doped layer 10 of the middle channel 6 and the right channel 7 through lead holes 11, so that the low capacitance diode and the TVS are connected in series, so as to realize the low capacitance and high surge performance of the device.

本发明还提供了形成上述一种新型低电容TVS结构的一种新型低电容TVS结构的制作方法,包括如下步骤:The present invention also provides a manufacturing method of a novel low-capacitance TVS structure for forming the above-mentioned novel low-capacitance TVS structure, comprising the following steps:

S1、在高阻衬底1上,通过三重扩散工艺在高阻衬底1的正面和背面均形成第一掺杂层2,通过减薄,抛光等工艺,保留阻衬底背面的第一掺杂层2,从而形成高阻层3,所述高阻层3的厚度小于100um,该厚度能有效提高产线的控制能力,利用三重扩散工艺能获得良好的高阻层3结构,且三重扩散工艺的成本低,提高经济效益;S1. On the high-resistance substrate 1, a first doped layer 2 is formed on both the front and the back of the high-resistance substrate 1 through a triple diffusion process. Impurity layer 2 to form a high-resistance layer 3. The thickness of the high-resistance layer 3 is less than 100um, which can effectively improve the controllability of the production line, and a good structure of the high-resistance layer 3 can be obtained by using the triple diffusion process. The cost of the process is low, and the economic benefit is improved;

S2、通过氧化,光刻,沟槽刻蚀及SiO2填充等技术,在高阻层3上形成沟槽隔离结构4,沟槽隔离结构4穿过高阻衬底1到达高阻衬底1背面的第一掺杂层2中,从而将高阻衬底1隔离形成左通道5、中间通道6和右通道7,并在右通道7内形成阱区9,阱区9是为TVS反向击穿后的大电流提供低阻通道,减少功率损耗,提高浪涌特性;S2. Through oxidation, photolithography, trench etching and SiO2 filling techniques, a trench isolation structure 4 is formed on the high resistance layer 3, and the trench isolation structure 4 passes through the high resistance substrate 1 to the back of the high resistance substrate 1 In the first doped layer 2, the high-resistance substrate 1 is isolated to form a left channel 5, a middle channel 6 and a right channel 7, and a well region 9 is formed in the right channel 7, and the well region 9 is used for the reverse strike of TVS. The large current after passing through provides a low-resistance channel, reducing power loss and improving surge characteristics;

S3、通过光刻,腐蚀,注入,退火等技术,在中间通道6的高阻层3上形成第二掺杂层8,以形成低电容二极管;S3. Through photolithography, etching, implantation, annealing and other techniques, a second doped layer 8 is formed on the high-resistance layer 3 of the intermediate channel 6 to form a low-capacitance diode;

S4、通过光刻,腐蚀,注入,退火等技术,分别在左通道5和中间通道6的高阻层3上形成第三掺杂层10,用于与后续电极形成欧姆接触,在右侧通道的阱区9上也形成第三掺杂层10,以形成高浪涌能力的TVS结构;S4. Through photolithography, etching, implantation, annealing and other techniques, a third doped layer 10 is formed on the high-resistance layer 3 of the left channel 5 and the middle channel 6 respectively, for forming ohmic contact with the subsequent electrodes, and on the right channel A third doped layer 10 is also formed on the well region 9 of the 10000 to form a TVS structure with high surge capability;

S5、通过光刻,腐蚀工艺,在所述左通道5上的第三掺杂层10、中间通道6上的第二掺杂层8上均开设引线孔11,用于与后续通过该引线孔11使这左通道5、中间通道6与电极金属形成欧姆接触;在中间通道6上的第三掺杂层10和右通道7的第三掺杂层10也开设引线孔11,用于与后续通过该引线孔11使中间通道6和右通道7的第三掺杂层10形成金属互联,使低电容二极管与TVS形成串联,以实现器件低电容与高浪涌性能;S5. Through the photolithography and etching process, lead holes 11 are opened on the third doped layer 10 on the left channel 5 and the second doped layer 8 on the middle channel 6, which are used to pass through the lead holes later. 11 Make the left channel 5 and the middle channel 6 form ohmic contact with the electrode metal; lead holes 11 are also opened on the third doped layer 10 on the middle channel 6 and the third doped layer 10 on the right channel 7 for connecting with the subsequent Through the lead hole 11, the third doped layers 10 of the middle channel 6 and the right channel 7 form metal interconnection, so that the low capacitance diode and the TVS are connected in series, so as to realize the low capacitance and high surge performance of the device;

S6、通过溅射或蒸发,及金属光刻,刻蚀等技术,在左通道5的第三掺杂层10、中间通道6上的第二掺杂层8上方形成正面电极,同时在中间通道6上的第三掺杂层10和右通道7的第三掺杂层10的上方形成金属引线互联;S6. Through sputtering or evaporation, and metal lithography, etching and other techniques, a front electrode is formed on the third doping layer 10 of the left channel 5 and the second doping layer 8 on the middle channel 6, and at the same time in the middle channel. A metal wire interconnection is formed above the third doped layer 10 on 6 and the third doped layer 10 of the right channel 7;

S7、通过减薄,背蒸等技术,在第一掺杂层2的背面形成背面电极,以串通整个TVS结构。S7 , forming a back electrode on the back surface of the first doped layer 2 by techniques such as thinning and back steaming, so as to connect the entire TVS structure.

如正面电极加负偏压时,左通道5反偏且耐压较高,电流优选较低耐压通道流通,即电流由背面电极流入,流经右侧通道反偏的TVS结构,右通道7与中间通道6的金属引线互联横向流入中间通道6,再经中间通道6正向偏置的低电容二极管由正面电极流出,中间通道6的低电容二极管与右通道7的TVS串联,另外,如正面电极加正偏压,中间通道6及右通道7串联的低电容二极管反偏电压较高,故电流由正面电极流入后,优选流经处于正向偏置的左通道5,由背面电极流出,故实现了低电容、高浪涌的性能。For example, when the front electrode is negatively biased, the left channel 5 is reverse biased and has a high withstand voltage, and the current preferably flows through the channel with lower withstand voltage, that is, the current flows from the back electrode and flows through the TVS structure of the reverse bias of the right channel, and the right channel 7 The metal lead interconnected with the middle channel 6 flows into the middle channel 6 laterally, and then flows out from the front electrode through the low-capacitance diode of the forward bias of the middle channel 6. The low-capacitance diode of the middle channel 6 is connected in series with the TVS of the right channel 7. In addition, such as The front electrode is positively biased, and the low-capacitance diode connected in series with the middle channel 6 and the right channel 7 has a higher reverse bias voltage. Therefore, after the current flows from the front electrode, it preferably flows through the left channel 5, which is in forward bias, and flows out from the back electrode. , so the performance of low capacitance and high surge is realized.

在本申请的一实施例中,如图1所示,所述高阻衬底1为P-高阻衬底1,所述高阻层3为P-高阻层,所述第一掺杂层2和第二掺杂层8均为N+掺杂层,所述第三掺杂层10为P+掺杂层,且所述阱区9为N阱区,对于N阱区,优选但不限于在所述右通道7内填充有N型poly以形成所述N阱区。In an embodiment of the present application, as shown in FIG. 1 , the high-resistance substrate 1 is a P-high-resistance substrate 1 , the high-resistance layer 3 is a P-high-resistance layer, and the first doping The layer 2 and the second doped layer 8 are both N+ doped layers, the third doped layer 10 is a P+ doped layer, and the well region 9 is an N well region. For the N well region, preferably but not limited to The right channel 7 is filled with N-type poly to form the N well region.

在本申请的其他实施例中,如图2所示,述高阻衬底1可以为N-高阻衬底1,所述高阻层3为N-高阻层,所述第一掺杂层2和第二掺杂层8均为P+掺杂层,所述第三掺杂层10为N+掺杂层,所述阱区9为P阱区,对于P阱区,优选但不限于在所述右通道7内填充有P型poly以形成所述P阱区。In other embodiments of the present application, as shown in FIG. 2 , the high-resistance substrate 1 may be an N-high-resistance substrate 1 , the high-resistance layer 3 is an N-high-resistance layer, and the first doping Layer 2 and the second doped layer 8 are both P+ doped layers, the third doped layer 10 is an N+ doped layer, and the well region 9 is a P well region. The right channel 7 is filled with P-type poly to form the P well region.

以上仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换或改进等,均应包含在本发明的保护范围之内。The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modification, equivalent replacement or improvement made within the spirit and principle of the present invention shall be included in the protection scope of the present invention. Inside.

Claims (10)

1. A novel low electric capacity TVS structure which characterized in that: including high resistant substrate (1), be formed with first doping layer (2) and be located high resistance layer (3) of first doping layer (2) top through triple diffusion technology on high resistant substrate (1), be equipped with a plurality of trench isolation structure (4), a plurality of on high resistance layer (3) trench isolation structure (4) divide into left passageway (5), intermediate passage (6) and right passageway (7) with high resistance layer (3), intermediate passage (6) are formed with second doping layer (8), be formed with well region (9) in right side passageway (7), all be formed with third doping layer (10) in well region (9), left side passageway (5) and intermediate passage (6).
2. The novel low capacitance TVS structure of claim 1, wherein: the high-resistance substrate (1) is a P-high-resistance substrate, the high-resistance layer (3) is a P-high-resistance layer, the first doping layer (2) and the second doping layer (8) are both N + doping layers, the third doping layer (10) is a P + doping layer, and the well region (9) is an N well region.
3. The novel low capacitance TVS structure of claim 1, wherein: the high-resistance substrate (1) is an N-high-resistance substrate, the high-resistance layer (3) is an N-high-resistance layer, the first doping layer (2) and the second doping layer (8) are P + doping layers, the third doping layer (10) is an N + doping layer, and the well region (9) is a P well region.
4. The TVS structure of claim 2, wherein: the right channel (7) is filled with N-type poly to form the N well region; or,
the right channel (7) is filled with P-type poly to form the P well region.
5. A novel low capacitance TVS structure as claimed in claim 2 or 3, wherein: the bottom end of the trench isolation structure (4) penetrates through the high-resistance substrate (1) to reach the interior of the first doping layer (2).
6. A novel low capacitance TVS structure as claimed in claim 2 or 3, wherein: the groove isolation structure (4) is provided with lead holes (11) on the third doping layer (10) on the left channel (5), the third doping layer (10) and the second doping layer (8) on the middle channel (6) and the third doping layer (10) on the right channel (7);
and the third doped layer (10) on the left channel (5), the second doped layer (8) on the middle channel (6), the third doped layer (10) on the middle channel (6) and the third doped layer (10) on the right channel (7) are electrically connected through the lead holes (11).
7. The novel low capacitance TVS structure of claim 1, wherein: the thickness of the high-resistance layer (3) is less than 100 um.
8. A manufacturing method of a novel low-capacitance TVS structure is characterized by comprising the following steps: the method comprises the following steps:
s1, forming first doping layers (2) on the front surface and the back surface of the high-resistance substrate (1) through a triple diffusion process on the high-resistance substrate (1), and reserving the first doping layers (2) on the back surface of the high-resistance substrate through a thinning process to form a high-resistance layer (3);
s2, forming a trench isolation structure (4) on the high-resistance layer (3), wherein the trench isolation structure (4) penetrates through the high-resistance substrate (1) to reach the first doping layer (2) on the back of the high-resistance substrate (1), so that the high-resistance layer (3) is isolated to form a left channel (5), a middle channel (6) and a right channel (7), and a well region (9) is formed in the right channel (7);
s3, forming a second doped layer (8) on the high-resistance layer (3) of the middle channel (6) to form a low-capacitance diode;
s4, forming a third doping layer (10) on the high-resistance layer (3) of the left channel (5) and the middle channel (6) respectively for forming ohmic contact with a subsequent electrode, and forming the third doping layer (10) on the well region (9) of the right channel;
s5, arranging lead holes (11) in the third doped layer (10) on the left channel (5) and the second doped layer (8) on the middle channel (6) for forming ohmic contact with the left channel (5) and the middle channel (6) and the electrode metal through the lead holes (11) in the following process; lead holes (11) are also formed in the third doping layer (10) on the middle channel (6) and the third doping layer (10) of the right channel (7) and are used for forming metal interconnection with the third doping layer (10) of the middle channel (6) and the right channel (7) through the lead holes (11);
s6, forming a front electrode above the third doping layer (10) of the left channel (5) and the second doping layer (8) on the middle channel (6), and simultaneously forming metal lead interconnection above the third doping layer (10) on the middle channel (6) and the third doping layer (10) of the right channel (7);
and S7, forming a back electrode on the back surface of the first doping layer (2).
9. The method of claim 8, wherein the step of forming the TVS structure further comprises: the high-resistance substrate (1) is a P-high-resistance substrate, the high-resistance layer (3) is a P-high-resistance layer, the first doping layer (2) and the second doping layer (8) are N + doping layers, the third doping layer (10) is a P + doping layer, the well region (9) is an N well region, and N-type poly is filled in the right channel (7) to form the N well region.
10. The method of claim 8, wherein the step of forming the TVS structure further comprises: the high-resistance substrate (1) is an N-high-resistance substrate, the high-resistance layer (3) is an N-high-resistance layer, the first doping layer (2) and the second doping layer (8) are P + doping layers, the third doping layer (10) is an N + doping layer, the well region (9) is a P well region, and P type poly is filled in the right channel (7) to form the P well region.
CN202010954549.XA 2020-09-11 2020-09-11 Novel low-capacitance TVS structure and manufacturing method thereof Pending CN111933718A (en)

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US6724043B1 (en) * 1999-09-08 2004-04-20 De Montfort University Bipolar MOSFET device
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