CN111933718A - Novel low-capacitance TVS structure and manufacturing method thereof - Google Patents

Abstract

The invention is applicable to the field of semiconductor technology, and provides a novel low-capacitance TVS structure and a manufacturing method thereof. The novel low-capacitance TVS structure includes a high-resistance substrate, and the high-resistance substrate forms a first doped layer through a triple diffusion process and is located in the high-resistance substrate. A high-resistance layer above the first doped layer, the high-resistance layer is provided with a trench isolation structure, and the trench isolation structure divides the high-resistance layer into a left channel, a middle channel and a right channel, and the middle channel forms the second doped layer , a well region is formed in the right channel, and a third doped layer is formed in the well region, the left channel and the middle channel; a high-resistance layer is formed by a triple diffusion process to obtain an ultra-low capacitance TVS structure. For the high resistance layer, the method of the present invention is less difficult to implement and has low manufacturing cost, and the formed TVS structure has the properties of low capacitance and high surge.

Description

A novel low-capacitance TVS structure and its fabrication method

technical field

The invention belongs to the technical field of semiconductors, and specifically relates to a novel low-capacitance TVS structure and a manufacturing method thereof.

Background technique

Nowadays, the integration of electronic products is getting higher and higher, and the size is getting smaller and smaller, and the ability of functional modules to resist surge, ESD and other shocks is weakened. It has become an inevitable trend to add protection devices in related interfaces and circuits. Among them, in order to prevent data distortion, there are strict requirements on the capacitance of protective devices used for communication interface protection. Such protective devices generally require a capacitance of less than 1uA, and the higher the frequency of the communication interface, the smaller the capacitance is required. Low-capacitance TVS (Transient Voltage Suppressor, transient suppression diode) is a protection device specially used for communication interface protection.

Taking a unidirectional low-capacitance TVS as an example, a TVS structure with strong anti-surge capability is mainly used in series with a low-capacitance diode to achieve low-capacitance. The low-capacitance diode is realized by a PN junction prepared on a P-type or N-type high-resistance layer.

At present, traditional low-capacitance TVS devices are used to form high-resistance layers of low-capacitance diode structures by growing high-resistance epitaxial layers on low-resistance substrates, and then preparing low-capacitance diodes on the high-resistance epitaxial layers. Because it is very difficult to grow high-resistance epitaxy on a low-resistance substrate, it needs some special means to suppress the self-doping of the substrate. higher cost.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art, and to provide a novel low-capacitance TVS structure with low manufacturing cost and a manufacturing method thereof.

The present invention provides a novel low-capacitance TVS structure, including a high-resistance substrate on which a first doped layer and a high-resistance layer located above the first doped layer are formed through a triple diffusion process, so the The high-resistance layer is provided with a plurality of trench isolation structures, the plurality of trench isolation structures divide the high-resistance layer into a left channel, a middle channel and a right channel, and the middle channel is formed with a second doped layer, so A well region is formed in the right channel, and a third doped layer is formed in the well region, the left channel and the middle channel.

Further, the high-resistance substrate is a P-high-resistance substrate, the high-resistance layer is a P-high-resistance layer, the first doped layer and the second doped layer are both N+ doped layers, so The third doping layer is a P+ doping layer, and the well region is an N well region.

Further, the high-resistance substrate is an N-high-resistance substrate, the high-resistance layer is an N-high-resistance layer, and the first doped layer and the second doped layer are both P+ doped layers, so The third doping layer is an N+ doping layer, and the well region is a P well region.

Further, the right channel is filled with N-type poly to form the N-well region; or, the right channel is filled with P-type poly to form the P-well region.

Further, the bottom end of the trench isolation structure passes through the high resistance substrate to reach the inside of the first doped layer.

Further, the trench isolation structure is provided on the third doped layer on the left channel, the third doped layer and the second doped layer on the middle channel, and the third doped layer on the right channel. There are lead holes; the third doped layer on the left channel and the second doped layer on the middle channel, the third doped layer on the middle channel and the third doped layer on the right channel all pass through all the The lead holes are electrically connected.

Further, the thickness of the high resistance substrate is less than 100um.

The present invention also provides a manufacturing method of a novel low-capacitance TVS structure for forming the above-mentioned novel low-capacitance TVS structure, comprising the following steps:

S1. On the high-resistance substrate, a first doped layer is formed on both the front and the back of the high-resistance substrate through a triple diffusion process, and the first doped layer on the back of the resistive substrate is retained through a thinning process, thereby forming a high-resistance substrate. barrier layer;

S2. A trench isolation structure is formed on the high-resistance layer, and the trench isolation structure passes through the high-resistance substrate and reaches the first doped layer on the back of the high-resistance substrate, thereby isolating the high-resistance substrate to form a left channel and a middle channel and the right channel, and a well region is formed in the right channel;

S3, forming a second doped layer on the high-resistance layer of the middle channel to form a low-capacitance diode;

S4, respectively forming a third doped layer on the high-resistance layers of the left channel and the middle channel for forming an ohmic contact with the subsequent electrodes, and also forming a third doped layer on the well region of the right channel;

S5. Lead holes are provided on the third doped layer on the left channel and the second doped layer on the middle channel, so that the left channel, the middle channel and the electrode metal can form ohmic through the lead holes subsequently. contact; lead holes are also provided on the third doped layer on the middle channel and the third doped layer on the right channel, for forming metal interconnection with the third doped layer of the middle channel and the right channel through the lead hole subsequently;

S6. A front electrode is formed over the third doped layer on the left channel and the second doped layer on the middle channel, and a metal is formed on the third doped layer on the middle channel and the third doped layer on the right channel at the same time lead interconnection;

S7, forming a back electrode on the back surface of the first doped layer.

Further, the high-resistance substrate is a P-high-resistance substrate, the high-resistance layer is a P-high-resistance layer, the first doped layer and the second doped layer are both N+ doped layers, so The third doped layer is a P+ doped layer, the well region is an N well region, and the right channel is filled with N-type poly to form the N well region.

Further, the high-resistance substrate is an N-high-resistance substrate, the high-resistance layer is an N-high-resistance layer, and the first doped layer and the second doped layer are both P+ doped layers, so The third doped layer is an N+ doped layer, the well region is a P well region, and the right channel is filled with P-type poly to form the P well region.

The present invention provides a novel low-capacitance TVS structure with low fabrication cost and a fabrication method thereof. A high-resistance layer is formed by a triple diffusion process to obtain an ultra-low-capacitance TVS structure. Compared with the high-resistance layer obtained by epitaxy, the present invention The method is easy to implement and low in manufacturing cost, and the formed TVS structure has the properties of low capacitance and high surge.

Description of drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are For some embodiments of the present invention, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

The following drawings are only intended to illustrate and explain the present invention schematically, and do not limit the scope of the present invention.

FIG. 1 is a schematic structural diagram of a low-capacitance TVS structure according to an embodiment of the present invention.

FIG. 2 is a schematic structural diagram of a low-capacitance TVS structure according to another embodiment of the present invention.

Description of reference numerals: 1, high resistance substrate; 2, first doped layer; 3, high resistance layer; 4, trench isolation structure; 5, left channel; 6, middle channel; 7, right channel; 8, The second doped layer; 9, the well region; 10, the third doped layer; 11, the lead hole.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

Please refer to FIG. 1 to FIG. 2 , which is a novel low-capacitance TVS structure disclosed by the invention, comprising a high-resistance substrate 1, on which a first doped layer 2 is formed by a triple diffusion process, and is located on the high-resistance substrate 1. The thickness of the high-resistance layer 3 above the first doped layer 2 is less than 100 μm, which can effectively improve the controllability of subsequent production lines to obtain a good high-resistance layer 3 .

The high-resistance layer 3 is provided with a plurality of trench isolation structures 4 , and the bottom ends of the trench isolation structures 4 pass through the high-resistance substrate 1 to the interior of the first doped layer 2 . The trench isolation structure 4 divides the high-resistance layer 3 into several channels, preferably but not limited to a left channel 5, a middle channel 6 and a right channel 7, and the middle channel 6 is formed with a second doped layer 8 to This forms a low capacitance diode.

A well region 9 is formed in the right channel 7, and the well region 9 can provide a low-resistance channel, reduce power loss, and improve surge characteristics.

A third doped layer 10 is formed in the well region 9, the left channel 5 and the middle channel 6, and is to be in ohmic contact with the subsequent electrodes to form a TVS structure with ultra-high surge capability. The trench isolation structure 4 Leads are provided on the third doped layer 10 on the left channel 5 , the third doped layer 10 and the second doped layer 8 on the middle channel 6 , and the third doped layer 10 on the right channel 7 Hole 11, the third doped layer 10 on the left channel 5 and the second doped layer 8 on the middle channel 6 are electrically connected through the lead hole 11, which is embodied as the third doped layer 10 on the left channel 5 and the second doped layer 8 on the middle channel 6. A front electrode is formed on the second doped layer 8 on the middle channel 6, and the left channel 5 and the middle channel 6 are respectively in ohmic contact with the front electrode through the lead hole 11; the third doped layer on the middle channel 6 10 and the third doped layer 10 on the right channel 7 are electrically connected through the lead holes 11 , specifically the third doped layer 10 on the middle channel 6 and the third doped layer 10 on the right channel 7 A metal lead is formed on the lead hole 11, and metal interconnection is formed on the third doped layer 10 of the middle channel 6 and the right channel 7 through lead holes 11, so that the low capacitance diode and the TVS are connected in series, so as to realize the low capacitance and high surge performance of the device.

The present invention also provides a manufacturing method of a novel low-capacitance TVS structure for forming the above-mentioned novel low-capacitance TVS structure, comprising the following steps:

S1. On the high-resistance substrate 1, a first doped layer 2 is formed on both the front and the back of the high-resistance substrate 1 through a triple diffusion process. Impurity layer 2 to form a high-resistance layer 3. The thickness of the high-resistance layer 3 is less than 100um, which can effectively improve the controllability of the production line, and a good structure of the high-resistance layer 3 can be obtained by using the triple diffusion process. The cost of the process is low, and the economic benefit is improved;

S2. Through oxidation, photolithography, trench etching and SiO2 filling techniques, a trench isolation structure 4 is formed on the high resistance layer 3, and the trench isolation structure 4 passes through the high resistance substrate 1 to the back of the high resistance substrate 1 In the first doped layer 2, the high-resistance substrate 1 is isolated to form a left channel 5, a middle channel 6 and a right channel 7, and a well region 9 is formed in the right channel 7, and the well region 9 is used for the reverse strike of TVS. The large current after passing through provides a low-resistance channel, reducing power loss and improving surge characteristics;

S3. Through photolithography, etching, implantation, annealing and other techniques, a second doped layer 8 is formed on the high-resistance layer 3 of the intermediate channel 6 to form a low-capacitance diode;

S4. Through photolithography, etching, implantation, annealing and other techniques, a third doped layer 10 is formed on the high-resistance layer 3 of the left channel 5 and the middle channel 6 respectively, for forming ohmic contact with the subsequent electrodes, and on the right channel A third doped layer 10 is also formed on the well region 9 of the 10000 to form a TVS structure with high surge capability;

S5. Through the photolithography and etching process, lead holes 11 are opened on the third doped layer 10 on the left channel 5 and the second doped layer 8 on the middle channel 6, which are used to pass through the lead holes later. 11 Make the left channel 5 and the middle channel 6 form ohmic contact with the electrode metal; lead holes 11 are also opened on the third doped layer 10 on the middle channel 6 and the third doped layer 10 on the right channel 7 for connecting with the subsequent Through the lead hole 11, the third doped layers 10 of the middle channel 6 and the right channel 7 form metal interconnection, so that the low capacitance diode and the TVS are connected in series, so as to realize the low capacitance and high surge performance of the device;

S6. Through sputtering or evaporation, and metal lithography, etching and other techniques, a front electrode is formed on the third doping layer 10 of the left channel 5 and the second doping layer 8 on the middle channel 6, and at the same time in the middle channel. A metal wire interconnection is formed above the third doped layer 10 on 6 and the third doped layer 10 of the right channel 7;

S7 , forming a back electrode on the back surface of the first doped layer 2 by techniques such as thinning and back steaming, so as to connect the entire TVS structure.

For example, when the front electrode is negatively biased, the left channel 5 is reverse biased and has a high withstand voltage, and the current preferably flows through the channel with lower withstand voltage, that is, the current flows from the back electrode and flows through the TVS structure of the reverse bias of the right channel, and the right channel 7 The metal lead interconnected with the middle channel 6 flows into the middle channel 6 laterally, and then flows out from the front electrode through the low-capacitance diode of the forward bias of the middle channel 6. The low-capacitance diode of the middle channel 6 is connected in series with the TVS of the right channel 7. In addition, such as The front electrode is positively biased, and the low-capacitance diode connected in series with the middle channel 6 and the right channel 7 has a higher reverse bias voltage. Therefore, after the current flows from the front electrode, it preferably flows through the left channel 5, which is in forward bias, and flows out from the back electrode. , so the performance of low capacitance and high surge is realized.

In an embodiment of the present application, as shown in FIG. 1 , the high-resistance substrate 1 is a P-high-resistance substrate 1 , the high-resistance layer 3 is a P-high-resistance layer, and the first doping The layer 2 and the second doped layer 8 are both N+ doped layers, the third doped layer 10 is a P+ doped layer, and the well region 9 is an N well region. For the N well region, preferably but not limited to The right channel 7 is filled with N-type poly to form the N well region.

In other embodiments of the present application, as shown in FIG. 2 , the high-resistance substrate 1 may be an N-high-resistance substrate 1 , the high-resistance layer 3 is an N-high-resistance layer, and the first doping Layer 2 and the second doped layer 8 are both P+ doped layers, the third doped layer 10 is an N+ doped layer, and the well region 9 is a P well region. The right channel 7 is filled with P-type poly to form the P well region.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modification, equivalent replacement or improvement made within the spirit and principle of the present invention shall be included in the protection scope of the present invention. Inside.

Claims (10)

1. A novel low electric capacity TVS structure which characterized in that: including high resistant substrate (1), be formed with first doping layer (2) and be located high resistance layer (3) of first doping layer (2) top through triple diffusion technology on high resistant substrate (1), be equipped with a plurality of trench isolation structure (4), a plurality of on high resistance layer (3) trench isolation structure (4) divide into left passageway (5), intermediate passage (6) and right passageway (7) with high resistance layer (3), intermediate passage (6) are formed with second doping layer (8), be formed with well region (9) in right side passageway (7), all be formed with third doping layer (10) in well region (9), left side passageway (5) and intermediate passage (6).

2. The novel low capacitance TVS structure of claim 1, wherein: the high-resistance substrate (1) is a P-high-resistance substrate, the high-resistance layer (3) is a P-high-resistance layer, the first doping layer (2) and the second doping layer (8) are both N + doping layers, the third doping layer (10) is a P + doping layer, and the well region (9) is an N well region.

3. The novel low capacitance TVS structure of claim 1, wherein: the high-resistance substrate (1) is an N-high-resistance substrate, the high-resistance layer (3) is an N-high-resistance layer, the first doping layer (2) and the second doping layer (8) are P + doping layers, the third doping layer (10) is an N + doping layer, and the well region (9) is a P well region.

4. The TVS structure of claim 2, wherein: the right channel (7) is filled with N-type poly to form the N well region; or,

the right channel (7) is filled with P-type poly to form the P well region.

5. A novel low capacitance TVS structure as claimed in claim 2 or 3, wherein: the bottom end of the trench isolation structure (4) penetrates through the high-resistance substrate (1) to reach the interior of the first doping layer (2).

6. A novel low capacitance TVS structure as claimed in claim 2 or 3, wherein: the groove isolation structure (4) is provided with lead holes (11) on the third doping layer (10) on the left channel (5), the third doping layer (10) and the second doping layer (8) on the middle channel (6) and the third doping layer (10) on the right channel (7);

and the third doped layer (10) on the left channel (5), the second doped layer (8) on the middle channel (6), the third doped layer (10) on the middle channel (6) and the third doped layer (10) on the right channel (7) are electrically connected through the lead holes (11).

7. The novel low capacitance TVS structure of claim 1, wherein: the thickness of the high-resistance layer (3) is less than 100 um.

8. A manufacturing method of a novel low-capacitance TVS structure is characterized by comprising the following steps: the method comprises the following steps:

s1, forming first doping layers (2) on the front surface and the back surface of the high-resistance substrate (1) through a triple diffusion process on the high-resistance substrate (1), and reserving the first doping layers (2) on the back surface of the high-resistance substrate through a thinning process to form a high-resistance layer (3);

s2, forming a trench isolation structure (4) on the high-resistance layer (3), wherein the trench isolation structure (4) penetrates through the high-resistance substrate (1) to reach the first doping layer (2) on the back of the high-resistance substrate (1), so that the high-resistance layer (3) is isolated to form a left channel (5), a middle channel (6) and a right channel (7), and a well region (9) is formed in the right channel (7);

s3, forming a second doped layer (8) on the high-resistance layer (3) of the middle channel (6) to form a low-capacitance diode;

s4, forming a third doping layer (10) on the high-resistance layer (3) of the left channel (5) and the middle channel (6) respectively for forming ohmic contact with a subsequent electrode, and forming the third doping layer (10) on the well region (9) of the right channel;

s5, arranging lead holes (11) in the third doped layer (10) on the left channel (5) and the second doped layer (8) on the middle channel (6) for forming ohmic contact with the left channel (5) and the middle channel (6) and the electrode metal through the lead holes (11) in the following process; lead holes (11) are also formed in the third doping layer (10) on the middle channel (6) and the third doping layer (10) of the right channel (7) and are used for forming metal interconnection with the third doping layer (10) of the middle channel (6) and the right channel (7) through the lead holes (11);

s6, forming a front electrode above the third doping layer (10) of the left channel (5) and the second doping layer (8) on the middle channel (6), and simultaneously forming metal lead interconnection above the third doping layer (10) on the middle channel (6) and the third doping layer (10) of the right channel (7);

and S7, forming a back electrode on the back surface of the first doping layer (2).

9. The method of claim 8, wherein the step of forming the TVS structure further comprises: the high-resistance substrate (1) is a P-high-resistance substrate, the high-resistance layer (3) is a P-high-resistance layer, the first doping layer (2) and the second doping layer (8) are N + doping layers, the third doping layer (10) is a P + doping layer, the well region (9) is an N well region, and N-type poly is filled in the right channel (7) to form the N well region.

10. The method of claim 8, wherein the step of forming the TVS structure further comprises: the high-resistance substrate (1) is an N-high-resistance substrate, the high-resistance layer (3) is an N-high-resistance layer, the first doping layer (2) and the second doping layer (8) are P + doping layers, the third doping layer (10) is an N + doping layer, the well region (9) is a P well region, and P type poly is filled in the right channel (7) to form the P well region.

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