WO2017118028A1

WO2017118028A1 - Surge protector device

Info

Publication number: WO2017118028A1
Application number: PCT/CN2016/095630
Authority: WO
Inventors: 骆生辉
Original assignee: 深圳市槟城电子有限公司
Priority date: 2016-01-05
Filing date: 2016-08-17
Publication date: 2017-07-13
Also published as: CN105552873B; CN105552873A

Abstract

A surge protector device comprises: an N-type substrate having a rear P-well layer over the entirety of a rear surface thereof and a front P-well layer on a front surface of the N-type substrate, wherein a side of the front P-well layer is provided with N+ implant regions. A TVS and a TSS are integrated, such that the device displays TVS characteristics when subjected to a forward surge, and displays TSS characteristics when subjected to a reverse surge, thus solving the problem in applications in which a TVS and a TSS connected in series are required to be employed. The surge protector device has a high level of integration and a low product cost, facilitates connection to an external circuit, and can be easily and conveniently applied.

Description

Surge protection device

This application claims the priority of the Chinese Patent Application, filed on Jan. 5, 2016, the application Serial No.

Technical field

The present invention relates to the field of overvoltage protection products, and more particularly to a surge protection device.

Background technique

At present, there are two main types of semiconductor devices commonly used as surge protection devices: one is a transient suppression diode (English translated as TRANSENT VOLTAGE SUPPRESSOR, TVS for short), and TVS is a voltage clamp type protection device. When the voltage at the terminal exceeds the reverse breakdown voltage, the TVS rapidly changes from a high-impedance state to a low-resistance state, and the voltage is stabilized at the clamp voltage, thereby protecting other electronic devices connected in parallel thereto. The second is a semiconductor discharge tube. THYRISTOR SURGE SUPPRESSOR (TSS) is a voltage switching protection device. When the voltage across it exceeds the reverse breakdown voltage, the TSS rapidly changes from a high-impedance state to a low-resistance state, reducing the voltage to almost Zero, thus protecting other electronic devices in parallel with it.

In a specific application scenario, it is necessary to select an appropriate surge protection device according to the working performance of the protected electronic device. For example, in the case where the surge voltage may be either positive or negative, the unidirectional TVS needs to be used in series with the TSS. When subjected to a forward surge, the unidirectional TVS clamps the surge voltage to the Protects the electronics from operating within the normal operating voltage range; when subjected to a reverse surge, the TSS releases the surge voltage close to a short circuit, preventing the protected electronic device from being damaged by excessive reverse voltage. At the same time, in order to make the circuit more simplified and integrated, it is common practice to manually stack the unidirectional TVS and TSS wafers that need to be connected in series, and the package has a complicated structure and high cost.

Summary of the invention

The object of the present invention is to provide a surge protection device capable of providing forward surge protection and reverse surge protection for a circuit, and having higher integration, simple structure and low cost.

In view of this, an embodiment of the present invention provides a surge protection device, including:

The N-type substrate is provided with a back surface P well layer on the entire back surface, a front surface P well layer on the front surface of the N type substrate, and an N+ implantation region on one side of the front surface P well layer.

Further, the front P well layer is a front deep P well layer and a front shallow P well layer respectively located on both sides, and the front shallow P well layer is disposed on a side where the N+ implant region is provided.

Further, a front deep N-well is disposed under the front shallow P-well layer.

Further, the back surface P well layer is a back surface deep P well layer and a back surface shallow P well layer respectively located on both sides, and the back surface deep P well layer is disposed on a side where the N+ implant region is provided.

Further, a back deep N-well is provided on the back shallow P well layer.

Further, the back deep P well layer is provided with a plurality of separate deep P wells.

Further, the N+ injection zone is provided in plurality.

Further, a short circuit hole is disposed between the plurality of N+ implant regions, and the short circuit hole has a large impedance.

The surge protection device of the present invention integrates TVS and TSS together, and exhibits TVS characteristics when subjected to a forward surge; and exhibits TSS characteristics when subjected to a negative surge, completely solving the needs in the application. The problem of using a TVS in series with a TSS. Moreover, the surge protection device has high integration degree and low product cost, and is convenient for connecting external circuits and being simple in application.

DRAWINGS

In order to make the content of the present invention easier to understand, the present invention will be further described in detail below with reference to the accompanying drawings

1 is a schematic cross-sectional view of a surge protection device according to Embodiment 1 of the present invention;

2 is an equivalent circuit diagram of a surge protection device according to an embodiment of the present invention;

3 is a schematic cross-sectional view of a surge protection device according to Embodiment 2 of the present invention;

4 is a cross-sectional view showing a surge protection device according to Embodiment 3 of the present invention;

5 is a cross-sectional view showing a surge protection device according to Embodiment 4 of the present invention;

6 is a cross-sectional view of a surge protection device according to a fifth embodiment of the present invention.

detailed description

The invention will be further illustrated by the following examples in conjunction with the accompanying drawings.

Please refer to FIG. 1. FIG. 1 is a cross-sectional view of a surge protection device according to Embodiment 1 of the present invention. As shown in FIG. 1, the surge protection device 1 of the present embodiment includes: a metal layer 11 of an external conductor, an N-type substrate, and a back surface P well layer on the entire back surface of the N-type substrate, the N-type substrate The front side is provided with a front P-well layer, and one side of the front P-well layer is provided with an N+ implanted region.

Preferably, the N+ implant region is provided with a plurality of electrodes for adjusting the sustain current and the sustain voltage of the device. In another preferred embodiment, a short circuit hole 12 is provided between the plurality of N+ implant regions, and the short circuit hole 12 has a large impedance. The shorting holes are used to improve the anti-interference ability of the device. Since the device area is too large, if there is no short-circuit hole, the device will concentrate current in one part, while the other part has no current, which will adversely affect the performance of the device.

Referring to FIG. 2, FIG. 2 is an equivalent circuit diagram of a surge protection device according to an embodiment of the present invention. The working process of the surge protection device provided by the present invention will be described below with reference to FIG. 1 and FIG.

1. When the device is subjected to a forward surge, the reverse PN junction formed by the N-type substrate-back P well undergoes avalanche breakdown, thereby discharging the surge current. At the same time, the structure on the right side of the device is N+ implant-front P-type-substrate-back P-well, which will not turn on due to high withstand voltage. So when a positive surge comes, the surge is vented through the front P-well-N-substrate-back P-well region on the left side of the device. At this point, the device exhibits TVS performance. When the surge is over, the device shuts down immediately and there is no problem with freewheeling.

2. When the device is subjected to a negative surge, the reverse diode formed by the N+ implant-front P well has a high withstand voltage, and the reverse diode formed by the N-type substrate-front P well has a low withstand voltage, so the N-type liner Avalanche breakdown occurs in the bottom-front P-well, and a leakage current forms a voltage drop through the short-circuit hole after breakdown. When the voltage drop is greater than the forward voltage drop of the front P-well-N+ implant, the PNPN structure formed by the backside P-well-N-substrate-front P-well-N+ implant produces positive feedback. When the surge passes, the device is turned off immediately due to the low potential of the back P-well, and there is no problem of freewheeling.

As can be seen from the above description, the working circuit of the device is equivalent to the circuit in which TVS and TSS are connected in parallel in FIG.

This embodiment has the following advantages:

Please refer to FIG. 3. FIG. 3 is a cross-sectional view of a surge protection device according to Embodiment 2 of the present invention. As shown in FIG. 3, the surge protection device of this embodiment includes: an N-type substrate having a back surface P well layer on the entire back surface, and a front surface P well layer on the front surface of the N type substrate The front P well layer is a front deep P well layer and a front shallow P well layer respectively located on both sides, and the front shallow P well layer is disposed on the side where the N+ implant region is provided.

The first embodiment corresponding to FIG. 1 has the following differences: the front P-well layer is a front deep P well layer and a front shallow P well layer on both sides, and the front shallow P well layer is disposed on the N+ implant. The side of the district. The remaining components are the same as those in the first embodiment, and are not described herein again. The advantages are:

1. When the device is subjected to a forward surge, the reverse PN junction formed by the N-type substrate-back P well undergoes avalanche breakdown, thereby discharging the surge current. The front deep P-well-N-substrate-backside P-well structure has a small negative-resistance characteristic, which can effectively reduce the residual voltage and improve the surge discharge capability. At the same time, the structure on the right side of the device is N+ implant-front shallow P-well-N-substrate-back P-well, which will not turn on due to high withstand voltage. So when a positive surge comes, the surge is vented through the front deep P-well-N-substrate-back P-well region on the left side of the device. At this point, the device exhibits TVS performance. When the surge is over, the device shuts down immediately and there is no problem with freewheeling.

2. When the device is subjected to a negative surge, the reverse diode formed by the N+ implant-front deep P-well has a high withstand voltage, and the reverse diode formed by the N-type substrate-front shallow P-well has a low withstand voltage, so N The substrate-formal shallow P-well undergoes avalanche breakdown, and a leakage current forms a voltage drop through the short-circuit hole after breakdown. When the voltage drop is greater than the forward voltage drop of the front shallow P-N+ implant, the PNPN structure formed by the backside P-N-substrate-front shallow P-N+ implant produces positive feedback. When the surge passes, the device is turned off immediately due to the low potential of the back P-well, and there is no problem of freewheeling.

This embodiment has the following advantages:

Please refer to FIG. 4. FIG. 4 is a cross-sectional view of a surge protection device according to Embodiment 3 of the present invention. As shown in FIG. 4, the surge protection device of this embodiment includes: an N-type substrate having a back surface P well layer on the entire back surface, and a front surface P well layer on the front surface of the N type substrate An N+ implant region is disposed on a right side of the front P well layer, and the back P well layer is a back deep P well layer and a back shallow P well layer respectively disposed on both sides, and the back deep P well layer is disposed There is the side of the N+ injection zone.

The embodiment 1 corresponding to FIG. 1 has the following difference: the back surface P well layer is a back surface deep P well layer and a back surface shallow P well layer respectively located on both sides, and the back surface deep P well layer is disposed in the The side of the N+ injection zone. The remaining components are the same as those in the first embodiment, and are not described herein again. The advantage is that when the device is affected In the case of a reverse surge, the deep P-well layer on the back side can increase the surge bleed capacity of the device and reduce residual voltage.

In another preferred embodiment 4, referring to FIG. 5, the back deep P well layer is provided with a plurality of separate deep P wells. The advantage is that the junction area of the back deep P-well-N substrate is increased, and the reverse surge bleed capability of the device is further improved.

The working process is the same as that of the embodiment shown in FIG. 1, and details are not described herein again.

This embodiment has the following advantages:

Referring to FIG. 6, FIG. 6 is a cross-sectional view of a surge protection device according to Embodiment 5 of the present invention. As shown in FIG. 5, the surge protection device of this embodiment includes: an N-type substrate, and the back surface of the N-type substrate is provided with a back deep P well layer and a back shallow P well layer respectively on both sides, a back deep P well layer is disposed on a side where the N+ implant region is disposed, and the front surface of the N type substrate is provided with a front deep P well layer and a front shallow P well layer respectively on both sides, and the front shallow P well layer An N+ implant region is disposed thereon, and a front deep N well is disposed under the front shallow P well layer, and a back deep N well is disposed on the back shallow P well layer.

The third embodiment corresponding to FIG. 4 has the following difference: a front deep N well is disposed under the front shallow P well layer, and a back deep N well is disposed on the back shallow P well layer. The remaining components are the same as those in the third embodiment, and are not described here. The advantage is that the breakdown voltage when the device is subjected to the reverse surge can be adjusted by adjusting the front deep N-well; the breakdown voltage when the device is subjected to the forward surge can be adjusted by adjusting the back deep N-well, At the same time, the forward surge capability of the device is further improved, and the residual voltage is reduced.

This embodiment has the following advantages:

Obviously, the above embodiments are merely examples for clarity of explanation, and are not for the embodiments. limited. Other variations or modifications of the various forms may be made by those skilled in the art in light of the above description. There is no need and no way to exhaust all of the implementations. Obvious changes or variations resulting therefrom are still within the scope of the invention.

Claims

A surge protection device, comprising:

The N-type substrate is provided with a back surface P well layer on the entire back surface, a front surface P well layer on the front surface of the N type substrate, and an N+ implantation region on one side of the front surface P well layer.
The surge protection device of claim 1 wherein:

The front P well layer is a front deep P well layer and a front shallow P well layer respectively located on both sides, and the front shallow P well layer is disposed on the side where the N+ implant region is provided.
The surge protection device of claim 2 wherein:

A front deep N-well is disposed under the front shallow P-well layer.
The surge protection device of claim 1 wherein:

The back surface P well layer is a back surface deep P well layer and a back surface shallow P well layer respectively located on both sides, and the back surface deep P well layer is disposed on the side where the N+ implant region is provided.
A surge protection device according to claim 4, wherein:

A back deep N well is provided on the back shallow P well layer.
A surge protection device according to claim 4, wherein:

The back deep P well layer is provided with a plurality of separate deep P wells.
The surge protection device of claim 1 wherein:

The N+ injection zone is provided in plurality.
The surge protection device of claim 7 wherein:

A short-circuit hole is disposed between the plurality of N+ implant regions, and the short-circuit hole has a large impedance.