CN112614782A - Manufacturing method of unidirectional negative resistance surge protection chip - Google Patents
Manufacturing method of unidirectional negative resistance surge protection chip Download PDFInfo
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- CN112614782A CN112614782A CN202011476918.5A CN202011476918A CN112614782A CN 112614782 A CN112614782 A CN 112614782A CN 202011476918 A CN202011476918 A CN 202011476918A CN 112614782 A CN112614782 A CN 112614782A
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- oxide film
- negative resistance
- surge protection
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 12
- 239000011574 phosphorus Substances 0.000 claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052796 boron Inorganic materials 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 9
- 239000007788 liquid Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 150000001204 N-oxides Chemical class 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000012858 packaging process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66121—Multilayer diodes, e.g. PNPN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A method for manufacturing a unidirectional negative resistance surge protection chip. The invention relates to the field of chip processing, in particular to a manufacturing method of a unidirectional negative resistance surge protection chip. The manufacturing method of the unidirectional negative resistance surge protection chip enables the product to have negative resistance characteristics and low positive contact voltage under the condition of not needing thinning of the thickness limit of a wafer. The invention comprises a P-type substrate primary silicon wafer in operation; forming N-diffusion regions by performing light phosphorus doping on two sides of a P-type silicon substrate; and carrying out concentrated boron doping on the upper N-region to form a P + region, doping concentrated phosphorus in the lower N-region to form an N + + region, and simultaneously changing the lower N-region into an N + region, thereby preparing the unidirectional negative resistance surge protection chip. The invention avoids the stress caused by the over-thin wafer in the packaging process and improves the reliability of the product.
Description
Technical Field
The invention relates to the field of chip processing, in particular to a manufacturing method of a unidirectional negative resistance surge protection chip.
Background
The surge protection device is required to absorb large surge current so as to protect the rear-stage circuit from being damaged. In the application range of the circuit, the device shows residual voltage after absorbing surge current, the smaller the residual voltage is, the smaller the influence of the surge and the residual voltage on the rear-stage circuit is, and the smaller the influence of the rear-stage circuit on the rear-stage circuit is, the better the protection is.
The negative resistance characteristic of the device requires that the device has a narrow base region width, and the traditional manufacturing process cannot make the base region narrow due to the limitations of a diffusion process, high difficulty in sheet production operation and the like, so that the negative resistance characteristic is difficult to realize.
Today, the competition of the semiconductor market is more and more intense, a first-class test technology is provided, and the guarantee of the product quality is a necessary tool for each semiconductor discrete device manufacturing factory, so that the research of a surge protection product with high reliability has important significance for guaranteeing the use reliability of the semiconductor discrete device.
Disclosure of Invention
The invention aims at the problems and provides a manufacturing method of a unidirectional negative resistance surge protection chip which enables a product to have negative resistance characteristics and low positive contact voltage under the condition of not needing thinning of the thickness limit of a wafer.
The technical scheme of the invention is as follows: the method comprises the following steps:
s1, initial oxidation: growing a layer of compact oxide film on the surface of the wafer;
s2, selective photoetching: exposing the oxide films of the N-region and the N-ring regions on two sides of the P-type wafer, and protecting the other regions with a photoresist;
s3, removing the N-oxide film: removing the exposed oxide film on the upper and lower sides of the wafer;
s4, N-zone phosphorus pre-deposition: pre-depositing low concentration N-on the exposed silicon surface above and below the wafer;
s5, N-region re-expansion: advancing the N-region again;
s6, selective photoetching: exposing part of the oxide film in the N-region above the wafer, and protecting the other regions with a photoresist;
s7, removing the oxide film in the P + region: removing the oxide film exposed on the N-region part above the wafer;
s8, P + region diffusion: pre-depositing a layer of concentrated boron on the exposed silicon surface of the N-region by using a liquid boron source;
s9, P + region re-expansion: advancing the P + region again;
s10, selective photoetching: exposing the surface oxide film of the N-region below the P region above the wafer, and protecting the other regions with a photoresist;
s11, removing the oxide film: removing the exposed oxide film of the N-region under the wafer;
s12, N-zone phosphorus pre-deposition: pre-depositing high concentration N + + on the exposed silicon surface under the wafer;
s13, expanding an N + + region again: the N + + region is pushed again, meanwhile, the N-region is changed into an N + region under the influence of the concentration of the N + + region, and the junction depth is further pushed;
s14, metallization: and plating a layer of electrode metal on the surface of the wafer, and finishing the processing.
In step S1, the thickness of the oxide film is 20000-30000 angstroms.
In steps S3, S7, and S11, the oxide film is removed using a BOE etching solution, respectively.
In steps S4 and S12, the POCL3 liquid source is used for diffusion.
The invention comprises a P-type substrate primary silicon wafer in operation; forming N-diffusion regions by performing light phosphorus doping on two sides of a P-type silicon substrate; and carrying out concentrated boron doping on the upper N-region to form a P + region, doping concentrated phosphorus in the lower N-region to form an N + + region, and simultaneously changing the lower N-region into an N + region, thereby preparing the unidirectional negative resistance surge protection chip.
The invention avoids the stress caused by the over-thin wafer in the packaging process and improves the reliability of the product.
Drawings
Figure 1 is a schematic representation of S1 in the present invention,
figure 2 is a schematic representation of S2 in the present invention,
figure 3 is a schematic representation of S3 in the present invention,
figure 4 is a schematic representation of S4 in the present invention,
figure 5 is a schematic representation of S5 in the present invention,
figure 6 is a schematic representation of S6 in the present invention,
figure 7 is a schematic representation of S7 in the present invention,
figure 8 is a schematic representation of S8 in the present invention,
figure 9 is a schematic representation of S9 in the present invention,
figure 10 is a schematic representation of S10 in the present invention,
figure 11 is a schematic representation of S11 in the present invention,
figure 12 is a schematic representation of S12 in the present invention,
figure 13 is a schematic representation of S13 in the present invention,
fig. 14 is a schematic view of S14 in the present invention.
Detailed Description
The present invention, as shown in fig. 1-14, comprises the steps of:
s1, initial oxidation: growing a layer of compact oxide film on the surface of the wafer;
s2, selective photoetching: exposing the oxide films of the N-region and the N-ring regions on both sides of the P-type wafer, and protecting the other regions with a photoresist (the lower part of the wafer is not coated with the photoresist);
s3, removing the N-oxide film: removing the exposed oxide film on the upper and lower sides of the wafer;
s4, N-zone phosphorus pre-deposition: using POCL3 liquid source diffusion to pre-deposit low concentration N-on the exposed silicon surface above and below the wafer;
s5, N-region re-expansion: the N-region is pushed again, and the reverse voltage of the diode is increased;
s6, selective photoetching: exposing part of the oxide film in the N-region above the wafer, and protecting the other regions with a photoresist;
s7, removing the oxide film in the P + region: removing the oxide film exposed on the N-region part above the wafer;
s8, P + region diffusion: pre-depositing a layer of concentrated boron on the exposed silicon surface of the N-region by using a liquid boron source;
s9, P + region re-expansion: the P + region is further pushed to a certain depth;
s10, selective photoetching: exposing the surface oxide film of the N-region below the P region above the wafer, and protecting the other regions with a photoresist;
s11, removing the oxide film: removing the exposed oxide film of the N-region under the wafer;
s12, N-zone phosphorus pre-deposition: using a POCL3 liquid source diffusion to pre-deposit a high concentration of N + + on the exposed silicon surface under the wafer;
s13, expanding an N + + region again: the N + + region is further advanced to a certain depth, meanwhile, the N-region is changed into an N + region under the influence of the concentration of the N + + region, and the junction depth is further advanced;
s14, metallization: and plating an electrode metal (TI/NI/AG or NI/Au) layer on the surface of the wafer, and finishing the processing.
In step S1, the thickness of the oxide film is 20000-30000 angstroms.
In steps S3, S7, and S11, the oxide film is removed using a BOE etching solution, respectively.
The invention comprises a P-type substrate primary silicon wafer in operation; forming N-diffusion regions by performing light phosphorus doping on two sides of a P-type silicon substrate; and carrying out concentrated boron doping on the upper N-region to form a P + region, doping concentrated phosphorus in the lower N-region to form an N + + region, and simultaneously changing the lower N-region into an N + region, thereby preparing the unidirectional negative resistance surge protection chip.
Claims (4)
1. A manufacturing method of a unidirectional negative resistance surge protection chip is characterized by comprising the following steps:
s1, initial oxidation: growing a layer of compact oxide film on the surface of the wafer;
s2, selective photoetching: exposing the oxide films of the N-region and the N-ring regions on two sides of the P-type wafer, and protecting the other regions with a photoresist;
s3, removing the N-oxide film: removing the exposed oxide film on the upper and lower sides of the wafer;
s4, N-zone phosphorus pre-deposition: pre-depositing low concentration N-on the exposed silicon surface above and below the wafer;
s5, N-region re-expansion: advancing the N-region again;
s6, selective photoetching: exposing part of the oxide film in the N-region above the wafer, and protecting the other regions with a photoresist;
s7, removing the oxide film in the P + region: removing the oxide film exposed on the N-region part above the wafer;
s8, P + region diffusion: pre-depositing a layer of concentrated boron on the exposed silicon surface of the N-region by using a liquid boron source;
s9, P + region re-expansion: advancing the P + region again;
s10, selective photoetching: exposing the surface oxide film of the N-region below the P region above the wafer, and protecting the other regions with a photoresist;
s11, removing the oxide film: removing the exposed oxide film of the N-region under the wafer;
s12, N-zone phosphorus pre-deposition: pre-depositing high concentration N + + on the exposed silicon surface under the wafer;
s13, expanding an N + + region again: the N + + region is pushed again, meanwhile, the N-region is changed into an N + region under the influence of the concentration of the N + + region, and the junction depth is further pushed;
s14, metallization: and plating a layer of electrode metal on the surface of the wafer, and finishing the processing.
2. The method as claimed in claim 1, wherein in step S1, the thickness of the oxide film is 20000-30000 angstroms.
3. The method as claimed in claim 1, wherein in steps S3, S7 and S11, BOE etching solution is used to remove the oxide film.
4. The method as claimed in claim 1, wherein the step S4, S12 are performed by using POCL3 liquid source diffusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011476918.5A CN112614782A (en) | 2020-12-15 | 2020-12-15 | Manufacturing method of unidirectional negative resistance surge protection chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011476918.5A CN112614782A (en) | 2020-12-15 | 2020-12-15 | Manufacturing method of unidirectional negative resistance surge protection chip |
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| Publication Number | Publication Date |
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| CN112614782A true CN112614782A (en) | 2021-04-06 |
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| CN202011476918.5A Pending CN112614782A (en) | 2020-12-15 | 2020-12-15 | Manufacturing method of unidirectional negative resistance surge protection chip |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017118028A1 (en) * | 2016-01-05 | 2017-07-13 | 深圳市槟城电子有限公司 | Surge protector device |
| CN109390385A (en) * | 2017-12-05 | 2019-02-26 | 上海长园维安微电子有限公司 | A kind of unidirectional TVS device and preparation method thereof with negative resistance charactertistic |
| CN111223914A (en) * | 2019-07-01 | 2020-06-02 | 上海维安半导体有限公司 | Semiconductor discharge tube with negative resistance characteristic and manufacturing method thereof |
| CN211654822U (en) * | 2020-05-09 | 2020-10-09 | 捷捷半导体有限公司 | Unidirectional negative resistance electrostatic discharge protection device |
-
2020
- 2020-12-15 CN CN202011476918.5A patent/CN112614782A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017118028A1 (en) * | 2016-01-05 | 2017-07-13 | 深圳市槟城电子有限公司 | Surge protector device |
| CN109390385A (en) * | 2017-12-05 | 2019-02-26 | 上海长园维安微电子有限公司 | A kind of unidirectional TVS device and preparation method thereof with negative resistance charactertistic |
| CN111223914A (en) * | 2019-07-01 | 2020-06-02 | 上海维安半导体有限公司 | Semiconductor discharge tube with negative resistance characteristic and manufacturing method thereof |
| CN211654822U (en) * | 2020-05-09 | 2020-10-09 | 捷捷半导体有限公司 | Unidirectional negative resistance electrostatic discharge protection device |
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