CN210607274U

CN210607274U - Shallow trench high-voltage GPP chip

Info

Publication number: CN210607274U
Application number: CN201921665201.8U
Authority: CN
Inventors: 潘蔡军; 王成森; 张超
Original assignee: Jiejie Semiconductor Co ltd
Current assignee: Jiejie Semiconductor Co ltd
Priority date: 2019-03-13
Filing date: 2019-10-08
Publication date: 2020-05-22
Anticipated expiration: 2029-10-08

Abstract

The utility model discloses a shallow trench high pressure GPP chip, the chip includes the N-substrate layer, the lower surface of N-substrate layer is formed with the N + substrate layer, the lower surface of N + substrate layer is formed with the cathode metal layer, the upper surface of N-substrate layer is formed with P-isolating ring, the upper surface of the N-substrate layer in the P-isolating ring is formed with the P anode layer, the upper surface of P anode layer is formed with the P + anode layer, the P-isolating ring not with P anode layer and P + anode layer contact, the upper surface of P-isolating ring is formed with the passivation slot, the passivation ditch inslot is formed with the passivation layer, the inboard of passivation layer with P anode layer and P + anode layer contact, the upper surface of P + anode layer is formed with the anode metal layer. The grooves in the GPP chip are shallow in depth, Wafer warping can be effectively reduced in the preparation process, internal stress of the chip is reduced, fragments are reduced, and the yield is improved.

Description

Shallow trench high-voltage GPP chip

Technical Field

The utility model relates to a diode technical field especially relates to a shallow trench high pressure GPP chip.

Background

At present, for silicon power diodes with medium and small currents and breakdown voltages lower than 1600V, the most common cutting patterns in the market are squares, and then are regular hexagons; the product with higher market price, performance requirement and high reliability is designed into a circular figure. In recent years, there has been an increasing demand for the use of a more reliable glass passivated (GPP) silicon diode in the market and has gained widespread acceptance by those in the electronics industry. The GPP chip uses a photoresist mask and etched V-grooves or mechanically scribed V-groove mesas prior to silicon diffuser metallization. However, in the current manufacturing process of the high-voltage GPP chip, the chip has large internal stress, warpage and easy fragmentation.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem how to provide a shallow trench high pressure GPP chip that chip internal stress is little, the piece is few, the output rate is high.

In order to solve the technical problem, the utility model discloses the technical scheme who takes is: a shallow trench high voltage GPP chip is characterized in that: the anode structure comprises an N-substrate layer, wherein an N + substrate layer is formed on the lower surface of the N-substrate layer, a cathode metal layer is formed on the lower surface of the N + substrate layer, a P-isolating ring is formed on the upper surface of the N-substrate layer in the P-isolating ring, a P anode layer is formed on the upper surface of the N-substrate layer, a P + anode layer is formed on the upper surface of the P anode layer, the P-isolating ring is not in contact with the P anode layer and the P + anode layer, a passivation groove is formed on the upper surface of the P-isolating ring, a passivation layer is formed in the passivation groove, the inner side of the passivation layer is in contact with the P anode layer and the P + anode layer, and an anode metal layer is formed on the upper surface.

Preferably, the depth of the passivation groove is 50 um-200 um, and the width is 100-1000 um.

Preferably, the depth of the P-isolating ring is 50um to 150um away from the upper surface of the chip.

Adopt the produced beneficial effect of above-mentioned technical scheme to lie in: the grooves in the GPP chip are shallow in depth, so that Wafer warping can be effectively reduced in the preparation process, internal stress of the chip is reduced, fragments are reduced, and the yield is improved; can be used for Wafer production of 4 inches and larger.

Drawings

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

FIG. 1 is a schematic structural diagram of a silicon wafer after a photolithography ring step is performed by the method according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a silicon wafer after an aluminum plug implantation step is performed according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a silicon wafer after a window photolithography step is performed by the method according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a silicon wafer after a high temperature diffusion step is performed by the method according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a silicon wafer after a photolithography step is performed by the method according to an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a silicon wafer after a trench etching step is performed by the method according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a silicon wafer after a passivation step is performed by the method according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a chip according to an embodiment of the present invention;

wherein: 1. an N-substrate layer; 2. an N + substrate layer; 3. a P-spacer ring; 4. a P anode layer; 5. a P + anode layer; 6. passivating the trench; 7. a passivation layer; 8. an anode metal layer; 9. photoresist; 10. silicon oxide.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be implemented in other ways different from the specific details set forth herein, and one skilled in the art may similarly generalize the present invention without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

As shown in fig. 8, the embodiment of the present invention discloses a shallow trench high voltage GPP chip, which includes an N-substrate layer 1, wherein an N + substrate layer 2 is formed on a lower surface of the N-substrate layer 1, a cathode metal layer 11 is formed on a lower surface of the N + substrate layer 2, a P-isolating ring 3 is formed on an upper surface of the N-substrate layer 1, a P anode layer 4 is formed on an upper surface of the N-substrate layer 1 in the P-isolating ring 3, a P + anode layer 5 is formed on an upper surface of the P anode layer 4, the P-isolating ring 3 is not in contact with the P anode layer 4 and the P + anode layer 5, a passivation trench 6 is formed on an upper surface of the P-isolating ring 3, a passivation layer 7 is formed in the passivation trench 6, an inner side of the passivation layer 7 is in contact with the P anode layer 4 and the P + anode layer 5, an anode metal layer 8 is formed on the upper surface of the P + anode layer 5. Preferably, the depth of the passivation groove 6 can be 50 um-200 um, and the width is 100-1000 um. Preferably, the depth of the P-isolating ring 3 is 50um to 150um away from the upper surface of the chip.

The embodiment of the utility model also discloses a preparation method of shallow trench high pressure GPP chip, including following step:

carrying out phosphorus diffusion on the N-type monocrystalline silicon: the diffusion temperature is 1180 +/-20 ℃/240 +/-20 min, and the resistance R after diffusion is 0.2-0.5 omega/□; the requirements of N-type monocrystalline silicon are as follows: rho is 50-60 omega cm, and the thickness t of the monocrystalline silicon wafer is (350-500) ± 5 um;

grinding on the front side: the thickness of the diffused N-type monocrystalline silicon residual silicon wafer is 310 +/-20 um;

front polishing: polishing the front side to remove 10 +/-5 um of N-type monocrystalline silicon;

first oxidation: the temperature is 1140 +/-20 ℃, the time is 4.0 +/-1H, and the thickness of the oxide layer is 1.0-1.5 um;

and (3) photoetching ring: etching a surface pattern of the P-isolation ring groove by glue homogenizing, exposure and development, as shown in figure 1;

injecting aluminum and pushing knots: injecting aluminum into the surface of the P-isolating ring by adopting ion injection equipment, and performing high-temperature knot pushing; the implantation dose is 1E15 pieces/cm²The knot pushing condition is 1250 +/-20 ℃/20 +/-3H, as shown in figure 2;

and (3) second oxidation: the temperature T is 1180 +/-20 ℃, the time T is 10 +/-2H, and the thickness of an oxide layer is 1.8-2.5 um;

photoetching a window: through glue spreading, exposure and development, a surface pattern of a P + anode area is engraved, as shown in FIG. 3;

window sand blasting: roughening the surface of the P + area, wherein the sand blasting pressure is 0.05 +/-0.01 MPa;

coating a boron-aluminum source: after rinsing and acid cleaning, coating a boron-aluminum source on the front surface;

high-temperature diffusion: 1265 ± 20 ℃/20 ± 3H, front side boron-aluminum junction depth ALXj is 85 ± 10um, back side phosphorus junction depth N + Xj is 70 ± 10um, P-isolation ring junction depth is 120 ± 20um, as shown in fig. 4;

and (3) photoetching grooves: etching a surface pattern of the passivation groove by spin coating, exposing and developing, as shown in fig. 5;

and (3) etching the groove: etching the passivated groove by using mixed acid, wherein the depth of the passivated groove is 50 +/-10 um, and the width of the passivated groove is 300 +/-100 um, as shown in figure 6;

passivation: passivating and cleaning the surface of the passivated groove, and passivating the surface of the groove by adopting SIPOS + GLASS + LTO, as shown in FIG. 7;

surface metallization: evaporating the alloy to form a surface cathode metal layer and an anode metal layer, as shown in FIG. 8;

scribing: after dicing, individual GPP chips are formed.

The grooves in the GPP chip are shallow in depth, so that Wafer warping can be effectively reduced in the preparation process, internal stress of the chip is reduced, fragments are reduced, and the yield is improved; can be used for Wafer production of 4 inches and larger.

Claims

1. A shallow trench high voltage GPP chip is characterized in that: the device comprises an N-substrate layer (1), wherein an N + substrate layer (2) is formed on the lower surface of the N-substrate layer (1), a cathode metal layer (11) is formed on the lower surface of the N + substrate layer (2), a P-isolating ring (3) is formed on the upper surface of the N-substrate layer (1) in the P-isolating ring (3), a P anode layer (4) is formed on the upper surface of the P anode layer (4), a P + anode layer (5) is formed on the upper surface of the P anode layer (4), the P-isolating ring (3) is not in contact with the P anode layer (4) and the P + anode layer (5), a passivation groove (6) is formed on the upper surface of the P-isolating ring (3), a passivation layer (7) is formed in the passivation groove (6), and the inner side of the passivation layer (7) is in contact with the P anode layer (4) and the P + anode layer (5), and an anode metal layer (8) is formed on the upper surface of the P + anode layer (5).

2. The shallow trench high voltage GPP chip of claim 1, wherein: the depth of the passivation groove (6) is 50 um-200 um, and the width is 100-1000 um.

3. The shallow trench high voltage GPP chip of claim 1, wherein: the depth of the P-isolating ring (3) is 50 um-150 um away from the upper surface of the chip.