CN211045439U

CN211045439U - Bidirectional programmable overvoltage protection device based on silicon controlled rectifier principle

Info

Publication number: CN211045439U
Application number: CN201921457687.6U
Authority: CN
Inventors: 张超; 王成森; 朱明�
Original assignee: Jiejie Semiconductor Co ltd
Current assignee: Jiejie Semiconductor Co ltd
Priority date: 2019-09-03
Filing date: 2019-09-03
Publication date: 2020-07-17
Anticipated expiration: 2029-09-03

Abstract

The utility model discloses a two-way overvoltage protection device able to programme based on silicon controlled rectifier principle contains: an N-type substrate silicon wafer; the P-type through area is arranged in the N-type substrate; the NPN triode is arranged between the first and second through regions and comprises a back deep phosphorus N + diffusion region, an N-type substrate, a P-type base region, an N + emitter region and a P + base ohmic contact region; the bidirectional NPNPN controlled silicon arranged between the second and third through areas comprises an N-type back K area, a P-type back short base area, an N-type substrate silicon wafer, a P-type front short base area and an N-type front K area, wherein the P-type back short base area and the P-type front short base area are formed by photoetching and diffusion at the same time, and the N-type back K area and the N-type front K area are formed by photoetching and diffusion at the same time. The utility model discloses both can realize two-way able to programme, two-way excessive pressure protection can realize higher integrated level again, have simpler and easy technology, littleer chip area.

Description

Bidirectional programmable overvoltage protection device based on silicon controlled rectifier principle

Technical Field

The utility model relates to a semiconductor power device technical field specifically is a two-way overvoltage protection device able to programme of integrated form based on bidirectional thyristor principle for protect communications facilities speech processing chip (S L IC IC) and avoid the excessive pressure to damage.

Background

The semiconductor overvoltage protection device is used as an important component for preventing surge overvoltage, and has a plurality of types, including TVS devices, fixed voltage discharge tube devices, electrostatic protection devices, programmable overvoltage protection devices and the like.

With the coming of the 5G communication era, the number of micro communication base station devices will be increased, and people have higher and higher requirements for the reliability of the communication system. The voice processing chip in the communication system is a sensitive IC, is easy to be damaged by factors such as power grid overvoltage or thunder, and once the voice processing chip is damaged, communication faults are conducted, information is interrupted, equipment fails, and therefore protection of the voice processing chip is of great importance.

The traditional programmable overvoltage protection device is provided with negative overvoltage protection and positive overvoltage protection by two unidirectional thyristors and two diodes respectively, such as a 61089 programmable semiconductor surge protection device commonly seen in the market, as shown in fig. 1.

The technical problem to be solved by the utility model is to realize both-way programmable and higher integration level, simpler process and smaller chip area.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a two-way overvoltage protection device able to programme based on silicon controlled rectifier principle has the integrated level height, simple process, and two-way voltage is characteristics able to programme to solve the problem that proposes among the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme: a bidirectional programmable overvoltage protection device based on thyristor principle, comprising:

an N-type substrate silicon wafer;

the P-type through area is arranged in the N-type substrate;

the NPN triode is arranged between the first and second through regions and comprises a back deep phosphorus N + diffusion region, an N-type substrate silicon wafer, a P-type base region, an N + emitter region and a P + base ohmic contact region;

the bidirectional NPNPN controlled silicon arranged between the second and third through areas comprises an N-type back K area, a P-type back short base area, an N-type substrate silicon wafer, a P-type front short base area and an N-type front K area, wherein the P-type back short base area and the P-type front short base area are formed by photoetching and diffusion at the same time, and the N-type back K area and the N-type front K area are formed by photoetching and diffusion at the same time;

the PNP triode is arranged in the rightmost through region and comprises a P-type through region, an N-type base region, a P-type emitting region and an N + base region ohmic contact region, wherein the N + base region ohmic contact region is formed by photoetching and diffusing the N-type front K region at the same time;

the passivation layer and the corresponding through hole are arranged on the surface of the front side of the chip;

the metal layers are arranged on the front side and the back side of the chip and comprise metal connected with an ohmic contact region P + of a base region of an NPN triode, a metal connecting wire connected with an emitting region of the NPN triode and a base region G1 of a bidirectional controllable silicon to provide a trigger signal of a quadrant I of the controllable silicon, metal III connected with an ohmic contact region N + of a base region of a PNP triode, a metal connecting wire II connected with an emitting region of the PNP triode and a base region G2 of the bidirectional controllable silicon to provide a trigger signal of a quadrant III of the controllable silicon, and metal II arranged on the front side of the bidirectional controllable silicon to serve as an electrode K of the bidirectional controllable silicon to be connected with signal input.

Preferably, the passivation layer is any one of silicon dioxide, silicon nitride and glass insulation passivation layer.

The utility model provides a two-way overvoltage protection device able to programme based on silicon controlled rectifier principle, the beneficial effects of the utility model are that: the bidirectional programmable overvoltage protection device can realize bidirectional programmable and bidirectional overvoltage protection, and can also realize higher integration level, simpler process and smaller chip area.

Drawings

Fig. 1 is a schematic diagram of a bidirectional programmable overvoltage protection device according to the present invention;

fig. 2 is a structural diagram of a bidirectional programmable overvoltage protection device according to the present invention;

fig. 3 is a schematic diagram of the operation of a bidirectional programmable overvoltage protection device according to the present invention;

fig. 4 is a schematic diagram of a conventional one-way programmable overvoltage protection device 61089;

fig. 5 is a schematic diagram of a disclosed bidirectional symmetrical high-speed overvoltage protection device.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1-3, the present invention provides a technical solution: a bidirectional programmable overvoltage protection device based on thyristor principle, comprising:

an N-type substrate silicon wafer 1;

a P-type punch-through region 2 arranged inside the N-type substrate;

the NPN triode is arranged between the first and second through regions and comprises a back deep phosphorus N + diffusion region 3, an N-type substrate silicon wafer 1, a P-type base region 4, an N + emitter region 8 and a P + base ohmic contact region 9 a;

the bidirectional NPNPN controlled silicon arranged between the second and third through areas comprises an N-type back K area 10B, a P-type back short base area 5B, an N-type substrate silicon wafer 1, a P-type front short base area 5a and an N-type front K area 10a, wherein the P-type back short base area 5B and the P-type front short base area 5a are formed by photoetching and diffusion at the same time, and the N-type back K area 10B and the N-type front K area 10a are formed by photoetching and diffusion at the same time;

the PNP triode arranged in the rightmost through region comprises a P-type through region 2, an N-type base region 6, a P-type emitting region 7 and an N + base region ohmic contact region 10b, wherein the N + base region ohmic contact region 10b is formed by photoetching and diffusing the same N-type front K region 10a at the same time;

the passivation layer 11 and the corresponding through hole are arranged on the surface of the front surface of the chip, and the passivation layer 11 is any one of silicon dioxide, silicon nitride and glass insulation passivation layers;

the metal layer arranged on the front surface and the back surface of the chip comprises metal 12 connected with an ohmic contact area P + of an NPN triode base region, metal connecting wire 13 connected with an emitting area of the NPN triode and a base region G1 of the bidirectional triode for providing a trigger signal of a thyristor I quadrant, metal 16 III connected with an ohmic contact area N + of the base region of the PNP triode, metal connecting wire 15 II connected with the emitting area of the PNP triode and the base region G2 of the bidirectional triode for providing a trigger signal of a thyristor III quadrant, metal 14 II arranged on the front surface of the bidirectional thyristor for serving as an electrode K of the bidirectional thyristor, the metal II 14 is used for connecting signal input, is arranged on the back surfaces of the NPN triode, the PNP triode and the bidirectional thyristor, is used as an electrode A of the bidirectional thyristor and is used for the common ground end of the devices;

the bidirectional programmable overvoltage protection device consists of an I, III-quadrant bidirectional controlled silicon, an NPN transistor and a PNP transistor, the structure is arranged on the same chip, the controlled silicon and the transistor are isolated through punch-through diffusion, and the PNP transistor is arranged in a punch-through diffusion region;

the emitter of the NPN transistor is connected with a gate G1 of the silicon controlled rectifier to provide an I-quadrant gate trigger signal for the silicon controlled rectifier, the base GN of the NPN transistor is used as a negative overvoltage reference potential of the device and can be connected with a negative terminal of a battery, the emitter of the PNP transistor is connected with a gate G2 of the silicon controlled rectifier to provide a III-quadrant gate trigger signal for the silicon controlled rectifier, the base GP of the PNP transistor is used as a positive overvoltage reference potential of the device and can be connected with a positive terminal of the battery, the common electrode A of the bidirectional silicon controlled rectifier, the NPN transistor and the PNP transistor is used as a common ground terminal, and a silicon controlled electrode K is used as a signal terminal (TIP or Ring), the device can realize bidirectional programming according to different voltages of external batteries, and performs;

the unit structure can be repeated on the same chip according to actual requirements, and the integration of multiple protection units can be realized on the chip, so that more multi-path overvoltage protection is realized;

the N-type substrate silicon wafer 1 is an N-type substrate material; 2 is a punch-through diffusion region, and one structural unit comprises three punch-through diffusion regions; the NPN triode is arranged between the first through area and the second through area and consists of a back deep phosphorus N + diffusion area 3, an N-type substrate 1, a P-type short base area 4, an N + emitter area 8 and a P + base ohmic contact area 9 a; the NPNPNPN bidirectional controlled silicon is arranged between the second and third through areas and is composed of an N-type back K area 10B, a P-type back short base area 5B, an N-type long base area substrate 1, a P-type front short base area 5a, an N-type front K area 10a and a P + front base ohmic contact area 9B; the PNP triode arranged in the third through ring is composed of a P-type through region 2, an N-type base region 6, a P-type emitter region 7 and an N + base region ohmic contact region 10 b; the front surface of the device is provided with a passivation layer 11 and a corresponding short circuit hole or lead hole; the front surface of the device is respectively provided with

metals

12, 13, 14, 15 and 16, the back surface of the device is provided with a metal 17, wherein the metal 12 is used as an electrode GN, the metal III 16 is used as an electrode GP, the metal II 14 is used as an electrode K, the metal 17 is used as an electrode A, and the

metals

13 and 15 play the role of interconnection lines and are used for connecting a triode and a controllable silicon.

The specific embodiment is as follows:

s1, taking an N-type material with the resistivity rho of 10-40 omega cm, wherein the thickness of an initial material sheet is 260 +/-10 um;

s2, chemically corroding the silicon wafer, and polishing the two sides of the silicon wafer by using a polishing machine, wherein the thickness of the polished silicon wafer is 200 +/-5 um;

s3, cleaning the silicon wafer, and putting the silicon wafer into a furnace for wet oxygen oxidation at the temperature of 1100-1180 ℃ for 3-5 hours to grow a 1.1-1.4 um oxide layer;

s4, leveling photoresist on both sides, and photoetching to form a through diffusion region 2;

s5, introducing high-concentration boron doping into the punch-through diffusion region pattern by adopting a method of coating a liquid source, wherein R is typically about 4 +/-1;

s6, cleaning the silicon wafer, and putting the silicon wafer into a furnace for wet oxygen oxidation at the temperature of 1100-1180 ℃ for 3-5 hours to grow a 1.1-1.4 um oxide layer;

s7, carrying out single-side photoetching on the back surface, and simultaneously forming a pattern of a back surface deep phosphorus N + diffusion region 3;

s8, adopting a POC L3 liquid source method, introducing high-concentration phosphorus doping into the pattern of the N + diffusion region 3, wherein R is typically about 1.5 +/-0.2;

s9, performing high-temperature long-time diffusion, wherein the typical temperature is 1275 +/-5 ℃, and forming a through diffusion region 2;

s10, carrying out double-sided photoetching again, and simultaneously forming the patterns of the P-type short base region 4, the P-type front-side short base region 5a and the P-type back-side short base region 5B;

s11, double-sided boron ion implantation is carried out, the dosage is 1E 15-1E 16, and the energy is 45-55 keV;

s12, photoetching the front surface, and forming a pattern of the PNP triode N-type base region 6 on the third punch-through diffusion;

s13, injecting phosphorus impurities with glue, wherein the dosage is 1E 14-1E 14, and the energy is 45-55 keV. Forming phosphorus doping in the N-type base region 6;

s14, removing photoresist and cleaning, carrying out impurity propulsion on a P-type region in a near-high-temperature diffusion furnace at 1150-1250 ℃ for 20-26h, and simultaneously forming the structures of a P-type short base region 4, a P-type front short base region 5a, a P-type back short base region 5B and an N-type base region 6;

s15, photoetching an emitting region 8 of the NPN triode and an emitting region 7 of the PNP triode on the front surface;

s16, respectively carrying out phosphorus doping on the NPN triode emission region 8 and carrying out boron doping on the PNP triode emission region;

s17, cleaning the silicon wafer, and performing high-temperature diffusion at 1200-1250 ℃ for 15-25 h in a furnace to form an emitting region structure of the NPN triode and the PNP triode;

s18, performing double-sided photoetching on the K region to form patterns of a front K region 10a, an N + base region ohmic contact region 10B and a back K region 10B of the bidirectional controllable silicon respectively;

s19, introducing phosphorus doping in the patterns of the front K region 10a, the N + base region ohmic contact region 10B and the back K region 10B by adopting a POC L3 liquid source method, wherein the typical R is approximately equal to 3 +/-0.2;

s20, cleaning the silicon wafer, entering a furnace for high-temperature diffusion at the temperature of 1100-1180 ℃ for 3-5 hours to form a front and back emitting region structure of the silicon controlled rectifier, and determining IH and IGT parameters of the bidirectional silicon controlled rectifier according to junction depth determined by the condition;

s21, front photoetching of P + front base ohmic contact regions 9a and 9 b;

s22, introducing high-concentration boron doping into the patterns of the front-surface base electrode ohmic contact regions 9a and 9b by adopting a method of coating a liquid source, wherein R is typically equal to 2 +/-1;

s23, cleaning the silicon wafer, and activating impurities by high-temperature diffusion at the temperature of 900-1000 ℃ for 1-3h in a furnace;

s24, photoetching a lead hole on the front side, and simultaneously etching a back oxide layer;

s25, evaporating Al on the front side to form a front metal electrode, and evaporating Ti-Ni-Ag on the back side to form a back metal electrode;

and S26, reversely etching metal on the front side to form an electrode pattern and an interconnection line, and alloying.

The detailed connection means is a technique known in the art, and the following mainly describes the working principle and process, and the specific operation is as follows.

The devices are connected in parallel between L ine-group of the circuit, i.e. the electrode K of the bidirectional thyristor is connected with L ine, the electrode A is connected with group, G_NTerminating negative overvoltage reference potential-VBAT, G_PTerminating the positive overvoltage reference potential + VBAT, when a negative surge voltage occurs on L ine, namely a surge voltage of group → L ine, once the surge voltage-Vpp is lower than the negative overvoltage reference potential-VBAT, the N-type substrate 1, the P-type base region 4 and the N + emitter regionWhen a positive surge voltage occurs on a L ine line, namely the surge voltage is L ine → group, once the surge voltage + Vpp is higher than a positive overvoltage reference potential + VBAT, a PNP triode composed of a P-type through region 2, an N-type base region 6 and a P-type emitting region 7 is turned on to provide III-quadrant gate driving current for the bidirectional thyristor, the bidirectional thyristor NPNPNPNPNPNPNPNPN is turned on, the current flows from K to A, the surge voltage is discharged to the Ground, and the device is turned off after the surge.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A bidirectional programmable overvoltage protection device based on thyristor principle, comprising:

an N-type substrate silicon wafer (1);

a P-type punch-through region (2) arranged inside the N-type substrate;

the NPN triode is arranged between the first and second through regions and comprises a back deep phosphorus N + diffusion region (3), an N-type substrate silicon wafer (1), a P-type base region (4), an N + emitter region (8) and a P + base ohmic contact region (9 a);

the bidirectional NPNPN controlled silicon arranged between the second and third through areas comprises an N-type back K area (10B), a P-type back short base area (5B), an N-type substrate silicon wafer (1), a P-type front short base area (5a) and an N-type front K area (10a), wherein the P-type back short base area (5B) and the P-type front short base area (5a) are formed by photoetching and diffusion at the same time, and the N-type back K area (10B) and the N-type front K area (10a) are formed by photoetching and diffusion at the same time;

the PNP triode is arranged in the rightmost through region and comprises a P-type through region (2), an N-type base region (6), a P-type emitting region (7) and an N + base region ohmic contact region (10b), wherein the N + base region ohmic contact region (10b) is formed by photoetching and diffusing the same with an N-type front K region (10a) at the same time;

the passivation layer (11) and the corresponding through hole are arranged on the front surface of the chip;

the metal layer arranged on the front surface and the back surface of the chip comprises metal (12) connected with an ohmic contact area P + of a base region of an NPN triode, metal connecting wire (13) connected with an emitting region of the NPN triode and a base region G1 of a bidirectional triode, metal III (16) connected with an ohmic contact area N + of the base region of the PNP triode, metal connecting wire II (15) connected with the emitting region of the PNP triode and the base region G2 of the bidirectional triode, metal II (14) arranged on the front surface of the bidirectional triode, and electrode K of the bidirectional triode, and the second metal (14) is used for connecting signal input, is arranged on the back surfaces of the NPN triode, the PNP triode and the bidirectional triode, is used as an electrode A of the bidirectional triode, and is used for the common ground end of the devices.

2. A bidirectional programmable overvoltage protection device based on thyristor principle according to claim 1, characterized in that: the passivation layer (11) is any one of silicon dioxide, silicon nitride and glass insulation passivation layers.